WO2008023152A1

WO2008023152A1 - Logic circuit

Info

Publication number: WO2008023152A1
Application number: PCT/GB2007/003152
Authority: WO
Inventors: Peter Y. K. Cheung; George A. Constantinides; Nicola Campregher
Original assignee: Imperial Innovations Limited
Priority date: 2006-08-25
Filing date: 2007-08-17
Publication date: 2008-02-28
Also published as: GB0616909D0

Abstract

A method is provided for designing a programmable logic integrated circuit for connecting a first logic lock having at least one terminal rail to a second logic lock having at least one terminal rail. The programmable logic integrated circuit includes a plurality of connection paths between respective rails and has at least one programmable device which is programmable to activate a signal path connection between the first and second logic blocks. The method comprises determining which signal paths are available using the existing programmable logic integrated circuit and calculating an optimum configuration of programmable devices required in this circuit, according to an optimization process, in order to provide a substitute signal path for each of said available signal paths.

Description

Logic Circuit

The present invention relates to integrated circuit (IC) technology. More specifically the present invention relates to user-configurable interconnects for array logic, field programmable gate arrays (FPGAs) and other circuitry.

Logic devices such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) consist of a plurality of logic blocks, each having a number of input and output terminals. Figure 1 shows a simplified prior art circuit with logic block A (101) and logic block B (102), each with five input/output terminals (Ii to I₅ for logic block A (101) and I₆ to Iio for logic block B (102)). It also shows a prior art interconnect scheme that allows any terminal from logic block A to be connected to logic block B. The terminals from the two logic blocks are connected to vertical wires (103) defining terminal rails in one layer of the integrated circuit (IC). A number of wires (shown as horizontal wires (104) in this diagram) defining connection paths between respective terminal rails are available on a different layer of the IC to route the signals, forming a routing channel between logic blocks A and B.

In one prior art implementation, the programmable property of the interconnect structure is achieved by placing user programmable switches (105), shown as "X" in the diagram, at each intersection of the vertical and horizontal wires. The programmable switches may be of the form of pass transistors which is controlled electronically. A storage element (such as a flip-flop circuit) is generally used to store the control signal to each programmable switch to determine whether the programmable switch should be ON or OFF. In this way, the interconnect configuration of the electronic circuit is programmable by the user changing the value (hence the control signal) stored in the storage elements. As part of the power-on sequence, the values to these storage elements are downloaded onto the device as a binary sequence known in the art as the configuration bit-stream. This scheme provides full flexibility in programming the interconnect but reduces the operating speed of the circuit because each programmable switch adds parasitic capacitance to the interconnect.

A known interconnect structure which aims to reduce the number of programmable switches (105) and hence to reduce parasitic capacitance is shown in Figure 2. A problem exists, however, with this structure as it reduces the flexibility in programming the interconnect, not enabling all terminals in logic block A (101) to be connected to logic block B (102).

A further problem arising in known logic devices is that of propagation delay. In the case of a logic device that contains many logic blocks in a row, the wires in the routing channel can be very long, and therefore incurring long propagation delay in the signal travelling on the wire. A known solution to this problem is to "break" the routing channel into two separate parts as shown in Figure 3. The routing channel (106) of logic block A (101) forms one routing segment consisting of wires L₁ to L₅, while the routine channel (107) of logic block B forms another routing segment consisting of wires L₆ to L₁₀. A programmable switchbox (108) is inserted between the two routing segments. One simple structure of the switch box (108) takes the form of a plurality of programmable switches (109) between L₁ and L₆, L₂ and L₇, and so on. If a switch (109), say, between L₁ and L₆ is OFF (not conducting), the left wire segment L₁ is isolated from the right wire segment L₆, and thereby reducing the capacitative loading on the circuit that is driving Lj.

Figure 4 shows a circuit according to a known solution with the following interconnect programmed: I₁ connected to I₆ (denoted as 1-6), 2-7, 3-8, 4-9 and 5-10. In this case, all the switches in the routing channels (106 and 107) shown as ® are switched ON and all the switches shown as x are switched OFF. All the switches in the switches in the switchbox (108) are ON.

As integrated circuit processing technology advances, the width of the wires in the routing channels and the separation between two such wires continue to be reduced. The probability of a defect occurring during the IC manufacturing process causing a fault on any part of the interconnect structure increases with these reduction. With the prior art interconnect structures as described above, if a defect falls on any part of the interconnect structure, the entire circuit is rendered non-functioning. For example, if a break (110) occurs in the wire segment L₅ of Figure 4 as shown in Figure 5, the connection between terminal I₂ and I₇ will fail.

In order to account for problems with faults in the interconnect structure, several known logic devices comprise extra hardware to provide redundancy for such faults, however this results in high area penalties in these devices, making them impractical for use. No known logic device provides sufficient redundancy means for dealing with faults throughout the interconnect structure in a compact and efficient manner. Furthermore, no existing logic device provides an interconnect structure with the minimum number of programmable switches which affords both fault redundancy and flexibility in programming the interconnect. In particular, no existing logic device can provide redundancy to deal with defective wire elements and defective programmable switches which can effect both the connections between logic blocks and local routing within a single logic block.

The invention is set out in the claims. Because a programmable logic integrated circuit (PLIC) for connecting a first logic block to a second logic block is provided which provides a substitution path for each available signal path between the two logic blocks, redundancy is introduced into the PLIC and hence into the logic device in which it is comprised. That is, a fault in a signal path between two respective logic block terminals can be bypassed and an alternative connection path between the two can be used. This ensures that the logic device will continue to function correctly regardless of the fault present. In addition, because a PLIC is provided in which an optimum configuration of programmable devices is provided in a connection path whilst still providing the required substitution paths between the two logic blocks, parasitic capacitance in the logic device is reduced. In particular, when said optimisation comprises minimising the number of programmable devices in the worst case substitution path, this reduces the difference in the number of programmable devices in different connection paths. This has the benefit of reducing and balancing the propagation delay in the logic device.

The method of designing the programmable logic integrated circuit (PLIC) preferably comprises adding an additional connection path to the circuit and using the integer linear programming technique to calculate the optimum number and locations of programmable devices required in the circuit in order to provide the required substitution paths between the first and second logic blocks. . Hence, an efficient and straight forward method of designing the logic device is provided. In addition, because during operation of the logic device the presence of the substitution paths allows a faulty interconnection between the first logic block and the second logic block of the logic device to be avoided, a higher manufacturing yield of the logic device is achieved.

Embodiments of the invention will now be described by way of examples, with reference to the drawings of which: Figure 1 is prior art interconnect structure between two logic blocks 101 and 102 with fully flexible programmable switches;

Figure 2 is a prior art interconnect structure between two logic blocks with reduced flexibility;

Figure 3 is a prior art interconnect structure in which a switchbox (108) is used to isolate the left and right interconnect structure;

Figure 4 is the interconnect structure of Figure 3 with all switches in the switchbox ON (conducting);

Figure 5 is a the interconnect structure of Figure 4 with an interconnect fault (110) on one connection path;.

Figure 6 is a possible structure for providing extra wiring and programmable switches that provides an alternative route to the faulty wire of Figure 5;

Figure 7 is an embodiment of the present invention where a reduced number of switches is used for the worst-case path, wherein the switches that are ON are chosen in order to avoid the faulty wire;

Figure 8 shows an adjacency matrix representation of the location of the programmable switches for the left side routing structure, the right side routing structure and the switchbox of Figure 7;

Figure 9 shows the overall connectivity matrix for the combined routing structure of Figure 7; and

Figure 10 shows the modified connectivity matrix for the overall routing structure of Figure 7 that provides one spare interconnect for every possible route.

In overview, a structure and method are provided for improving the programmable interconnect structure in a programmable logic integrated circuit in order to improve the manufacturing yield in the presence of interconnect faults by providing a substitute path for every available signal path in the circuit. The method includes adding an extra interconnect wire with programmable switches to provide an additional connection path in the circuit in such a way that optimises the configuration of the switches on that connection path. The method of designing the programmable logic integrated circuit comprises an efficient method of discovering the optimum configuration of the required programmable switches. The method uses adjacency matrices to describe the programmable switches that connect to the wires in the circuit and preferably an integer linear programming technique is applied. The number and locations of the switches can therefore be identified without performing an exhaustive search or by using trial and error. In operation, if any fault in the circuit is identified on an existing signal path an alternative signal path is used which avoids any connection path or switch in which the fault exists. Hence a precise and efficient method of providing alternative routes to a programmable logic integrated circuit is provided whereby one or pluralities of faults are avoided.

Referring now to the figures, the embodiments of the present invention can be understood in more detail below.

In order to cope with an interconnect fault such as the one shown in Figure 5, or any other fault in the interconnect structure, one solution is to add an extra wire to the routing channels 206 and 207, and to the switchbox 208 as shown in Figure 6. If programmable switches (209) are added to every intersection of this added wire (210) and the vertical wires 103, an alternative path to any interconnect faults in the original structure can be substituted. For example, the open-circuit fault 110 can be bypassed by routing I₂ to I₇ via switches marked as ® as shown in Figure 6. However, this method will add significant amount of parasitic capacitance to the substitution interconnect 210. In this particular case, the worst case substitution path would be loaded with 12 programmable switches which are OFF, each contributing some parasitic capacitance to the interconnect wire.

The present invention overcomes the above problem by using a reduced number of programmable switches in the worst-case path while ensuring that an alternative path to all original signal paths exists in order to make a substitution in case of a fault. One possible embodiment of the invention for the original interconnect structure of Figure 5 is shown in Figure 7. The additional wire 210 is now deployed with 3 added programmable switches 211 in the left routing channel, 3 added programmable switches 212 in the right routing channel, and 2 added switches 213 in the switchbox. Thus the worst-case loading of programmable OFF switches on the substitution connection path 210 is reduced from 11 to 8. With this embodiment, the connections I₁ to I₆ (denoted as 1-6, 2-7, 3-8, 4-9 and 5-10) can be achieved as shown in Figure 7 with the open-circuit faults 110 bypassed.

It will be appreciated from Figure 7 that, for any single fault in the interconnect network, a substitution path can now be found. Furthermore, the solution according to Figure 7 can easily be adapted to cope with more than one interconnect fault. By adding a plurality of N wires and programmable switches at the appropriate locations, a plurality of N faults can be bypassed. In each solution to accommodating N faults, the number of programmable switches in the worst-case path can be reduced whilst still ensuring an alternative signal path to all original signal paths exist. A substitute signal path can therefore be found in case of each of the N faults, and at the same time parasitic capacitance in the circuit is reduced.

The required locations for placing the programmable switches in order to guarantee that a substitution path exists for all possible interconnection between any terminals of one logic block to those of another logic block can be found by a number of methods. For example, it is possible to perform exhaustive search to discover these locations.

The present invention proposes an efficient method of discovering the minimum number and the locations of the required programmable switches as described below. The method uses adjacency matrices to describe the programmable switches that connect wires. Figure 8 a) shows the adjacency matrix A (301) for the left routing structure of Figure 3 which is shown in isolation as in Figure 8 b). The programmable switches 105 connect the terminal rails Il to 15 (103) of the logic block (101) to the wires of the routing channel (106) which define the connection paths in the interconnect structure. An entry of ' 1' and '0' in the adjacency matrix signifies that a programmable switch is present and absent respectively. Similarly Figure 8 c) shows the adjacency matrix S (302) for the switchbox (108) as shown in Figure 8d) which in this case shows a straightforward switch per routing channel and 8e) shows the adjacency matrix B (303) for the right routing structure (107) as shown in Figure 8f). Finally, the product of the three matrices AxSxB yields an overall connectivity matrix X (304) as shown in Figure 9. In this example, the entry of '0' (305) in row 1 indicates that there is no connection between Il to 17. The entry of '1' (306) in top- left corner indicates that there is one possible path between Il and 16. The entry of '2' (307) in row 2 indicates that there are two possible paths between 12 and 17, and so on.

As described above, to provide redundancy to any faults present in the interconnect structure, one alternative connection path must be added to provide a substitute signal path for each of the existing signal paths. This introduction of a substitute signal path for each and everyone of the existing signal path is equivalent to increasing every non-zero entry in the overall connectivity matrix X by at least one. Such modified overall connectivity matrix X' (308) is depicted in Figure 10. This solution can be generalised to accommodate a plurality of faults by increasing each non-zero entry in the overall connectivity matrix by more than 1. It is then necessary to identify the revised configuration of A, S or B, subject to device number minimisation or other optimisation constraints that will yield X'.

The introduction of at least one extra connection path by adding an extra horizontal interconnect wire to the interconnect is equivalent to increasing the dimension of the adjacency matrices. For this embodiment, A has a dimension of (m x n) where m is the number of terminal rails in each logic block, n is the number of connection paths in the circuit, and in this case m = n = 5. S has a dimension of (n x n), and B has a dimension of (n x m). In order to cope with one fault in the interconnect structure, the number of connection paths n is increased by 1 in order to provide a spare connection path. To cope with k independent faults, n is increased by k.

To identify the minimum number and the locations of the programmable switches, one approach is to search the possible locations to place the switches in an exhaustive way by trial and error. Alternatively, the Integer Linear Programming (ILP) technique (as explained in "Integer Programming" by Laurence A. Wolsey ISBN 0471283665) incorporated herein by reference, can be applied. An ILP formulation of the method is to split the overall connectivity matrix X' (308) into the product of an adjacency matrix Y and an arbitrary matrix Z, where matrix Y would represent the location of programmable switches in the left routing channel (i.e. a revised version of A with n increased) and matrix Z would correspond to the products of revised adjacency matrices S and B to represent the switches in the switchbox and the right routing channel respectively in an iterative process. Hence Z can be altered either by changing the switch configuration in the switchbox and/or the switch configuration in the right routing channel.

The main constraint in this approach is shown in equation (1) below where y,_k, zig and x,_j represent matrix elements of matrix Y, Z and X respectively and t is the size of routing channel 106 and routing channel 107, and therefore corresponds to n above.

Viyj∑y_ιkz_kJ ≥ ^χ _tJ +l (l) k=\

Constraints to preserve the regular structure and symmetry of some or all of the adjacency matrices may also exist.

It will be appreciated that in order to accommodate two faults in the logic device circuit two additional connection paths would have to be added and therefore the right hand side of equation (1) would read x_tJ + 2. In this case, t is also incremented by 1 to increase the matrix dimensionality. A constraint also may exist in that only the non-zero elements of matrix X should be increased.

The formal aim of the ILP formulation is to find the minimum number of programmable switches which will provide an alternative path to all existing signal paths, and is formulated mathematically in (2).

Constants to indicate the variable size of the transistors required to provide the programmable connections may be introduced in equation (2). Once the original interconnect structure is modified as described above, the following method is followed in order to avoid a fault in the interconnect structure:

1. The location of the fault, if any, is identified. Many algorithms and methods exist to detect such as fault in the FPGA interconnection. An example of one such algorithm is described in "BIST based Inter -cconect Fault Location for FPGAs" by N. Campregher and Cheung in LNCS, Springer- Verlag 2004.

2. When the bitstream which determines the signal paths which are to be used, and hence which terminals of the first and second logic blocks are to be connected to one another, is downloaded to the device (during configuration of the interconnect structure), this can be used to establish whether the faulty interconnect is used is detected.

3. If the faulty interconnect Pl is used to route a signal Sl, an alternative or substitute signal path P2 is found (which is guaranteed to exist by the present invention) and the faulty path Pl is substituted with the alternative path P2.

4. There is a possibility that the alternative path P2 is already used for routing another signal S2, in which case, an alternative path P3 to P2, if available, is used to substitute P2.

5. The above steps continue until no more substitution is needed.

As will be appreciated by a person skilled in the art, the above method can be extended for a circuit in which redundancy for a plurality of faults exists. The alternative signal path for each available signal path can be stored on a memory accessible during operation of the logic device.

Claims

1. A method of designing a programmable logic integrated circuit for connecting a first logic block having at least one terminal rail to a second logic block having at least one terminal rail, the programmable logic integrated circuit including a plurality of connection paths between respective rails and at least one programmable device programmable to activate a signal path connection between said first and second logic blocks, the method comprising determining which signal paths are available using the existing programmable logic integrated circuit and calculating according to an optimisation process an optimum configuration of programmable devices required in the circuit in order to provide a substitute signal path for each of said available signal paths.

2. A method as claimed in claim 1 in which the optimum configuration of programmable devices required is calculated using an Integer Linear Programming technique.

3. A method as claimed in claim 1 or claim 2 in which calculating the optimum configuration of programmable devices required includes the step of minimising the number of programmable devices in a connection path.

4. A method as claimed in any preceding claim wherein the programmable logic integrated circuit further includes a connection path switch assembly and in which calculating the optimum configuration of programmable devices required includes the step of changing the configuration of the connection path switch assembly.

5. A method as claimed in any preceding claim in which providing a substitute signal path for each of the available signal paths includes the step of adding a connection path to the circuit.

6. A method as claimed in any preceding claim in which calculating the optimum configuration of programmable devices required is calculated to provide two or more substitute paths.

7. A method as claimed in any preceding claim comprising identifying the number of available signal paths, identifying the number of additional desired substitute signal paths for each available path and identifying a revised programmable device configuration for at least one of connections between terminal rails and connection paths or within connection paths to obtain the revised programmable device configuration whilst minimising the number of additional programmable devices required.

8. A method as claimed in claim 7 in which the revised programmable device configuration includes at least one additional connection path

9. A method as claimed in claim 8 in which one additional connection path is provided for each additional substitute path per available path.

10. A method of operating a programmable logic integrated circuit for connecting a first logic block having at least one terminal rail to a second logic block having at least one terminal rail, the programmable logic integrated circuit including a plurality of connection paths and at least one programmable device programmable to activate an available signal path between said first and second logic blocks, wherein an optimum configuration of programmable devices is provided according to an optimisation process to provide a substitute signal path for each available signal path between the first and second logic blocks, the method comprising detecting a fault on an available signal paths and activating a corresponding substitute signal path on which no fault has been detected.

11. The method of claim 10 wherein, where a plurality of faults are detected, an additional substitute path is activated.

12. The method of claim 10 or claim 11 in which a substitute path is activated only if a fault is detected on an active signal path.

13. The method of any of claims 10 to 12 in which if the substitute path comprises a signal path already activated between the logic blocks then an additional substitute signal path is activated.

14. A programmable logic integrated circuit for connecting a first logic block having at least one terminal rail to a second logic block having at least one terminal rail, said programmable logic integrated circuit including a plurality of connection paths and at least one programmable device programmable to activate an available signal path between said first and second logic blocks, wherein an optimum configuration of programmable devices is provided according to an optimisation process to provide a substitute signal path for each available signal path between the first and second logic blocks.

15. A logic device comprising a programmable logic integrated circuit as claimed in claim 14.

16. A method of providing fault redundancy in a programmable logic integrated circuit for connecting a first logic block having at least one terminal rail to a second logic block having at least one terminal rail, the programmable logic integrated circuit including a plurality of connection paths and at least one programmable device programmable to activate an available signal path between said first and second logic blocks, the method comprising incrementing the number of connection paths in the circuit.