WO2008024171A8 - Dram transistor with recessed gates and methods of fabricating the same - Google Patents

Dram transistor with recessed gates and methods of fabricating the same Download PDF

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Publication number
WO2008024171A8
WO2008024171A8 PCT/US2007/016573 US2007016573W WO2008024171A8 WO 2008024171 A8 WO2008024171 A8 WO 2008024171A8 US 2007016573 W US2007016573 W US 2007016573W WO 2008024171 A8 WO2008024171 A8 WO 2008024171A8
Authority
WO
WIPO (PCT)
Prior art keywords
fabricating
methods
same
source
drain regions
Prior art date
Application number
PCT/US2007/016573
Other languages
French (fr)
Other versions
WO2008024171A1 (en
Inventor
Gordon A Haller
Sanh D Tang
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to CN2007800307677A priority Critical patent/CN101506966B/en
Priority to EP07810696A priority patent/EP2054928A1/en
Priority to JP2009525542A priority patent/JP5445944B2/en
Publication of WO2008024171A1 publication Critical patent/WO2008024171A1/en
Publication of WO2008024171A8 publication Critical patent/WO2008024171A8/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A memory array includes a plurality of memory cells (20) formed on a semiconductor substrate (22). Individual of the memory cells include first (24) and second (26) field effect transistors respectively comprising a gate (28/30), a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are formed in openings in the substrate and are hard wired together. A conductive data are formed in openings in the substrate and line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two.
PCT/US2007/016573 2006-08-21 2007-07-24 Dram transistor with recessed gates and methods of fabricating the same WO2008024171A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800307677A CN101506966B (en) 2006-08-21 2007-07-24 DRAM transistor with recessed gates and methods of fabricating the same
EP07810696A EP2054928A1 (en) 2006-08-21 2007-07-24 Dram transistor with recessed gates and methods of fabricating the same
JP2009525542A JP5445944B2 (en) 2006-08-21 2007-07-24 DRAM transistor with embedded gate and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/507,696 2006-08-21
US11/507,696 US7772632B2 (en) 2006-08-21 2006-08-21 Memory arrays and methods of fabricating memory arrays

Publications (2)

Publication Number Publication Date
WO2008024171A1 WO2008024171A1 (en) 2008-02-28
WO2008024171A8 true WO2008024171A8 (en) 2009-06-25

Family

ID=38835017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/016573 WO2008024171A1 (en) 2006-08-21 2007-07-24 Dram transistor with recessed gates and methods of fabricating the same

Country Status (8)

Country Link
US (2) US7772632B2 (en)
EP (1) EP2054928A1 (en)
JP (1) JP5445944B2 (en)
KR (1) KR101074594B1 (en)
CN (1) CN101506966B (en)
SG (1) SG174730A1 (en)
TW (1) TWI362743B (en)
WO (1) WO2008024171A1 (en)

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CN101506966A (en) 2009-08-12
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US20080042179A1 (en) 2008-02-21
JP5445944B2 (en) 2014-03-19
KR20090036595A (en) 2009-04-14
TW200816454A (en) 2008-04-01
CN101506966B (en) 2010-09-01
US8394699B2 (en) 2013-03-12
WO2008024171A1 (en) 2008-02-28
JP2010502008A (en) 2010-01-21
SG174730A1 (en) 2011-10-28
KR101074594B1 (en) 2011-10-17
US7772632B2 (en) 2010-08-10
EP2054928A1 (en) 2009-05-06

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