WO2008028330A1 - A programmable interconnect network for logic array - Google Patents
A programmable interconnect network for logic array Download PDFInfo
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- WO2008028330A1 WO2008028330A1 PCT/CN2006/002238 CN2006002238W WO2008028330A1 WO 2008028330 A1 WO2008028330 A1 WO 2008028330A1 CN 2006002238 W CN2006002238 W CN 2006002238W WO 2008028330 A1 WO2008028330 A1 WO 2008028330A1
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- Prior art keywords
- logic
- switch
- interconnect network
- programmable interconnect
- cells
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
Definitions
- This invention relates to an integrated circuit and, more specifically, a programmable interconnect network of logic array.
- FPGA Field Programmable Gate Array
- FPGA Field Programmable Gate Array
- field programmable logic cell array where logic cells are to be connected to each other by configurable interconnect networks.
- configurable logic cell arrays are widely used in numerous microelectronic devices.
- a conventional interconnect network for field programmable (FP) logic cell array is in planar structure, in which connection cells are configured to connect logic cells of the array to switch cells and connections are made between switch cells and their respective neighboring switch cells.
- FP field programmable
- Such a planar interconnect network is quite easy to build physically, but not straightforward to implement logic functions.
- the interconnect network would become quite complex in order to connect an arbitrary logic cell to another cell of the array.
- the planar interconnect network may result in a long routing delay for worst case, which is proportional to the square root of N, wherein N is number of cells in the logic cell array.
- the planar network lacks scalability. As the network expands, every switch cell should be expanded to accommodate changing interconnection demands.
- a tree-based network can provide a better solution for interconnection of logic cells.
- Such a tree-based interconnect network is illustrated in Fig. 1.
- l logic cells act as leaves of the tree. Neighboring leaves are connected to first-level switch boxes, and neighboring switch boxes of lower levels are connected to higher-level switch boxes.
- U.S. patent 6,693,456 and 6,940,308 disclosed a tree-based hierarchical interconnection architecture for integrated circuits, in which logic cells are in row-column layout and interconnections therebetween are of tree structure.
- the hierarchical interconnect architecture brought forth high efficiency and scalability in interconnection network.
- a programmable interconnect network for an array of logic cells.
- Said interconnect network comprises a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also comprises peripheral switch boxes, of which at least one is connected to an external logic.
- the present invention provides an integrated circuit.
- Said integrated circuit comprises an FP array of logic cells connected by the programmable interconnect network according to the first aspect and a mask programmable (MP) logic array.
- MP mask programmable
- Fig. 1 illustrates a tree-based interconnect network
- Fig. 2 illustrates a tree based hierarchical architecture of interconnect network for FP logic cells according to an embodiment of the present invention
- Fig. 3 illustrates a 6-level tree based interconnect network
- Fig. 4 A illustrates a block diagram of an internal HSB of the interconnect network
- Fig. 4B illustrates a block diagram of a peripheral HSB of the interconnect network
- Fig 5 is a signal flow chart illustrating how an LC G of Fig 2 will be connected to external logic
- Fig 6 is a signal flow chart illustrating how an LC E of Fig 2 will be connected to external logic
- Fig. 7 illustrates a logic diagram of the tree based hierarchical architecture of interconnect network according to present invention
- Fig. 8(A) shows a donut pattern formed by FP logic array and MP array
- Fig. 8(B) shows a sandwich pattern formed by FP logic array and MP array.
- Fig. 2 illustrates a tree based hierarchical architecture of interconnect network for FP logic cells according to an embodiment of the present invention.
- an 8*8 logic cell array consisting of 64 logic cells (LC) is provided.
- the LCs are interconnected by an interconnect network, which is formed by hierarchical switch boxes (HSBs) in a 3 -level quad-tree hierarchical architecture.
- the HSBs are configured to implement programmable routing paths to all the LCs. More specifically, four neighboring LCs are connected to one hierarchical switch box (HSB) in level Ll, i.e. HSBi. Four neighboring HSBs in Ll are connected to one HSB in level L2, i.e. HSB2.
- HSB hierarchical switch box
- HSBs in level L2 are connected to one HSB in level L3, i.e. HSBi.
- HSBs in lower level are referred to as children HSBs
- HSBs in higher level which are connected to the children HSBs, are referred to as parent HSBs.
- HLBi Hierarchical Logic Block in level 1
- HLBi Hierarchical Logic Block in level 1
- HLBi Hierarchical Logic Block in level 1
- HLBi Hierarchical Logic Block in level 1
- HLBi The whole block, which is formed by HSBi and the four HSBs in L2, is referred to as HLBi.
- HLBs in lower level are referred to as children HLBs
- HLB in higher level which is formed by the children HLBs, is referred to as parent HLB.
- HSB2-M a HSB is labeled as HSB2-M, where M is a position index and may have a value selected from 0, 1, 2 and 3, depending on the position of the HSB relative to the other three HSBs in L2.
- M a position index and may have a value selected from 0, 1, 2 and 3, depending on the position of the HSB relative to the other three HSBs in L2.
- the position index "0" represents the top left corner
- “1" represents the top right corner
- “2” represents the bottom left corner
- “3" represents the bottom right corner.
- a HSB is labeled as HSBi-MN, where M represents the position index of HSB2 to which the HSB is connected, and N represents the position index of the HSB relative to the other three HSBs belonging to the same HLB in L2 and may have a value from 0, 1, 2, and 3.
- Some HSBs located at peripheral of the logic cell array are provided with external multiplexer • switches (XMSs), for making connection to external logics.
- XMSs external multiplexer • switches
- the XMS included in HSB/ is referred to as XMSi, XMS of HSB2 as XMS2, and XMS of HSB3 as XMS3.
- the XMS may be replaced by pass transistors, pass gates, or other switch boxes that can execute logical selection and connection functions.
- an LC of the array may be connected to any other LC in the array.
- an LC labeled as E (LC E) may be connected to HSBi-21 of Ll, and then to an LC labeled as F (LC F).
- the routing path is preferred to include HSB1-21, HSB2-2, and HSBi-23.
- the routing path may include HSB7-21, HSB2-2, HSB3, HSB2-1 and HSBMO.
- an LC of the logic cell array can be connected to external logics.
- the logic cell array can generally be divided into peripheral LCs and internal LCs.
- the peripheral LCs may directly interact with external logics through their own inputs and outputs, without any further routing resource.
- the internal LCs on the other hand, can not directly interact with external logics. Therefore, the interconnect network having XMSs will facilitate establishing connection between the internal LCs and the external logics.
- a signal from an LC may be routed via HSBs to another HSB containing an XMS and then to external logics.
- the related EDA software needs to search the HLB holding the internal LC and its parent or grandparent HLBs for the one HSB containing XMS. If one found, the internal LC may be connected through this XMS externally. In case there are more than one HLB containing XMS, which may be in different hierarchical levels, the HLB providing the shortest routing path will be preferred.
- the LC G may be connected to HSBi-23 and its associated XMSi, and then to external logics.
- the LC E may be connected to HSB1-21, HSB2-2 and its associated XMS2, then to external logics.
- the routing path for LC H to external logics may include HSBi-IO and HSB2-1 and its associated XMS2.
- FIG. 3 illustrates a 6-level tree based interconnect network.
- each HLBJ represents the entire logic block of Fig 2.
- Four neighboring HLBs in L3 are connected to one HSB in level L4, i.e. HSB4.
- Four neighboring HLBs in L4 are connected to one HSB in level L5, i.e. HSB5.
- Four neighboring HLBs in level L5 are connected to one HSB in level L6, i.e. HSB ⁇ 5.
- the hierarchical architectures in Fig. 3 may be expanded and the number of the levels may not be limited to 6.
- the architecture may have L7, L8, and L9 ...
- the number of children HLBs in a parent HLB may differ from one another.
- Fig. 4A illustrates a block diagram of an internal HSB of the interconnect network.
- the HSB is labeled as HSBA;, where k represent the hierarchical level of the HSB so that HSBA: may represent any HSB in Fig 2 and Fig 3 or HSB of even higher level.
- HSBA comprises a plurality of switch cells implemented by multiplexers (MUXs), i.e., upstream MUX switch UMSA:, downstream MUX switch DMSAr-O, DMSA>1, DMS£-2, and DMS&-3.
- MUXs multiplexers
- the HSBA has downstream MUX inputs dmi0-dmi3, upstream MUX input umi, upstream MUX output umo and downstream MUX outputs dmoO-dmo3.
- the outputs dmoO-dmo3 will be connected to inputs of the four LCs connecting to the HSBA: when or to inputs of the four HSBs of level /c-1 connecting to the HSBA; when k is other than 1.
- the input umi will be connected to output of one of the HSBs of level k+1 connecting to the HSBA:.
- the output umo will be connected to input of one of the HSBs of level A:+l connecting to the HSBA:.
- the UMSA functions to receive input signals WDIA: from inputs dmiO-dmiJ and, under control of configuration bits, select one of the input signals WDIA: as WUO/c and output the same at umo.
- Fig. 4B illustrates block diagram of a peripheral HSB of the interconnect network.
- the peripheral HSBA differs from that of Fig. 4A by further comprising an XMSA:, input xmi and output xmo.
- the input xmi is an external MUX input and will be connected to output of external logic.
- the output xmo is an external MUX ouput and will be connected to input of the external logic.
- the XMSA functions to receive input signals WDIA: from inputs dmi ⁇ -dmi3 and input signal WUIA: from input umi. Then, XMSA: selects, under control of configuration bits, one of the input signals as WXOA: and output it to xmo. On the other hand, input signal from xmi is then sent to DMSA:-0, DMSA>2, DMSA:-2 and DMSA:-3, one of which selects, under control of respective configuration bits, the signal and output it to one of dmoO-dmo3. To the extreme, the XMSA: can be configured to receive input signal from input xmi as well.
- switch boxes as mentioned above may be implemented by pass transistors, pass gates, multiplexers or other elements that can execute logical selection and connectivity functions.
- the multiplexers (MUXs) are preferred since they need less space to store configuration bits compared to other switch boxes.
- Fig 5 is a signal flow chart illustrating how an LC G of Fig 2 could be connected to external logic.
- HSBi -23 receives at position dmii an output signal from LC G. Within the HSBi-23, the signal is routed to input dmfi of XMSi. The XMSi selects the signal and output the same via output xmo to external logic.
- HSBi-23 receives at position xmi a signal from external logic. The signal is then routed to input xmi of DMSi-I. The DMSi-I selects this signal and sends it to output dmoi, which is connected to the input of LC G.
- LC G can be connected to external logic via HSBi-23. It is noted that the j-indice of dmij, DMSi-j and dmoj represent the relative position for each of the signals to and from LC G to its parent HLB.
- Fig 6 is a signal flow chart illustrating how an LC E of Fig 2 will be connected to external logic.
- logic cell E may visit external logic via a routing path including HSBi-21 and HSB2-2, or alternatively, via a second routing path including HSBi-21, HSB2-2 and HSB.?.
- HSB5 there are three HSBs in different levels, i.e. HSB5, HSB2-2, and HSBi-21.
- Output umo and input umi of HSBi-21 are coupled respectively to input dmil and output dmol of HSB2-2.
- Output umo and input umi of HSB2-2 are coupled respectively to input dmi2 and output dmo2 of HSB5. Assume that input dmi2 and output dmo2 of HSBi-21 are coupled respectively to output and input of LC E.
- the signal When a signal needs to be routed to external logic from LC E, the signal goes into HSBi-21 via its input dmi2. Since HSBi-21 has no XMS, the signal is routed, via UMSl and output umo of HSBi-21, to input dm ⁇ of HSB2-2; and is subsequently routed to external logic via XMS2 of HSB2-2 by signal xmo.
- the signal goes into HSB2-2 via its input xmi.
- DMS2-1 selects the signal and routes it to dmoi. The signal dmoi is subsequently routed to HSBi -21 via its input umi.
- LC E can be connected through HSBi-21 and HSB2-2 to external logic.
- the routing path is shown as bold lines in Fig 6.
- the second routing path including HSB3 may be used instead.
- the signal is routed from UMS2 of HSB2-2 further to HSBi, where XMSJ selects the signal and routes it to external logic.
- the signal is first routed to input xmi of HSBJ, in which DMS3-2 selects the signal and sends it to DMS2-1 of HSB2-2, then to DMSi-2 of HSBi-21, and finally to LC E.
- the part of the second routing path in HSBJ is shown in dotted line. Similar to the routing path in Fig 5, all the indice of input, output, DMS in Fig 6 are selected based on the relative position indice of LC E and its parent HLBs.
- Fig. 7 illustrates a logic diagram of the tree based hierarchical architecture of interconnect network according to present invention.
- leaves at the bottom of the tree structure represent LCs in the FP logic cell array, and the trunks of various levels represent HSBs or HLBs.
- every four leaves (LCs) grow on and are supported by a trunk in level Ll (HSBi or HLBi).
- Every four (children) trunks (HSBi or HLBi) grow on and are supported by a parent trunk in level L2 (HSB2 or HLB2).
- Every four trunks (HSB2 or HLB2) grow on and are supported by a grandparent trunk in level L3 (HSBJ or HLBJ), and so on.
- the tree will be searched for a trunk with XMS and then a routing path between the leaf and the trunk should be identified.
- a preferred way is to search the parent trunks holding the leaf or LC. In particular, it is first to check whether the said leaf or said LC is a peripheral LC. If yes, make connection directly; if no, proceed to the next step to examine whether trunk or HSB of next higher level holding the said LC is with XMS. If yes, visit the XMS of the trunk or HSB, if no, proceed to check parent trunk(s) of higher levels, until a trunk with XMS is found.
- each internal LC can be connected via XMS of peripheral HSB to external logics with predictable timing, optimal path and high efficiency.
- FP logic array and MP logic elements may be integrated together as a circuit so as to achieve direct communication therebetween, increasing transmission efficiency.
- Fig. 8 illustrates two pattern of integration of FP logic array and MP array.
- Fig. 8(A) shows a donut pattern, in which FP array is surrounded by MP elements.
- Fig. 8(B) shows a sandwich pattern, in which MP array is consisted of three parts, between which is located FP elements.
- MP logic array can be replaced by any other external logic such as ASIC.
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PCT/CN2006/002238 WO2008028330A1 (en) | 2006-08-31 | 2006-08-31 | A programmable interconnect network for logic array |
US12/375,560 US7928764B2 (en) | 2006-08-31 | 2006-08-31 | Programmable interconnect network for logic array |
CN2006800555992A CN101517546B (en) | 2006-08-31 | 2006-08-31 | Programmable internet for logic array |
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PCT/CN2006/002238 WO2008028330A1 (en) | 2006-08-31 | 2006-08-31 | A programmable interconnect network for logic array |
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US7994818B2 (en) * | 2007-06-20 | 2011-08-09 | Agate Logic (Beijing), Inc. | Programmable interconnect network for logic array |
US9231594B2 (en) * | 2011-12-21 | 2016-01-05 | Ecole Polytechnique Federale De Lausanne (Epfl) | Non-LUT field-programmable gate arrays |
US9519360B2 (en) | 2014-12-11 | 2016-12-13 | Synaptics Incorporated | Palm rejection visualization for passive stylus |
Citations (3)
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US5880598A (en) * | 1997-01-10 | 1999-03-09 | Xilinx, Inc. | Tile-based modular routing resources for high density programmable logic device |
US5924115A (en) * | 1996-03-29 | 1999-07-13 | Interval Research Corporation | Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration |
US20050063373A1 (en) * | 2003-07-24 | 2005-03-24 | Dehon Andre | Method and apparatus for network with multilayer metalization |
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NL8600848A (en) * | 1986-04-03 | 1987-11-02 | Philips Nv | MEMORY WITH SIMULTANEOUSLY ADDRESSABLE MEMORY ELEMENTS. |
US5317209A (en) * | 1991-08-29 | 1994-05-31 | National Semiconductor Corporation | Dynamic three-state bussing capability in a configurable logic array |
EP0858168A1 (en) * | 1997-01-29 | 1998-08-12 | Hewlett-Packard Company | Field programmable processor array |
EP0858167A1 (en) * | 1997-01-29 | 1998-08-12 | Hewlett-Packard Company | Field programmable processor device |
GB9808609D0 (en) * | 1998-04-22 | 1998-06-24 | Automatic Parallel Designs Ltd | Method and apparatus for designing sequential circuits |
US6236229B1 (en) * | 1999-05-13 | 2001-05-22 | Easic Corporation | Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities |
US6756811B2 (en) * | 2000-03-10 | 2004-06-29 | Easic Corporation | Customizable and programmable cell array |
US6693456B2 (en) * | 2000-08-04 | 2004-02-17 | Leopard Logic Inc. | Interconnection network for a field programmable gate array |
US20040114436A1 (en) * | 2002-12-12 | 2004-06-17 | Actel Corporation | Programmable interconnect cell for configuring a field programmable gate array |
US7176714B1 (en) * | 2004-05-27 | 2007-02-13 | Altera Corporation | Multiple data rate memory interface architecture |
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- 2006-08-31 US US12/375,560 patent/US7928764B2/en active Active
- 2006-08-31 CN CN2006800555992A patent/CN101517546B/en not_active Expired - Fee Related
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Patent Citations (3)
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US5924115A (en) * | 1996-03-29 | 1999-07-13 | Interval Research Corporation | Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration |
US5880598A (en) * | 1997-01-10 | 1999-03-09 | Xilinx, Inc. | Tile-based modular routing resources for high density programmable logic device |
US20050063373A1 (en) * | 2003-07-24 | 2005-03-24 | Dehon Andre | Method and apparatus for network with multilayer metalization |
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CN101517546A (en) | 2009-08-26 |
US20090261858A1 (en) | 2009-10-22 |
CN101517546B (en) | 2011-12-07 |
US7928764B2 (en) | 2011-04-19 |
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