WO2008048940A3 - Graphics processing unit with shared arithmetic logic unit - Google Patents

Graphics processing unit with shared arithmetic logic unit Download PDF

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Publication number
WO2008048940A3
WO2008048940A3 PCT/US2007/081428 US2007081428W WO2008048940A3 WO 2008048940 A3 WO2008048940 A3 WO 2008048940A3 US 2007081428 W US2007081428 W US 2007081428W WO 2008048940 A3 WO2008048940 A3 WO 2008048940A3
Authority
WO
WIPO (PCT)
Prior art keywords
gpu
pipeline
attribute
stages
arithmetic logic
Prior art date
Application number
PCT/US2007/081428
Other languages
French (fr)
Other versions
WO2008048940A2 (en
Inventor
Guofang Jiao
Brain Ruttenberg
Chun Yu
Yun Du
Original Assignee
Qualcomm Inc
Guofang Jiao
Brain Ruttenberg
Chun Yu
Yun Du
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc, Guofang Jiao, Brain Ruttenberg, Chun Yu, Yun Du filed Critical Qualcomm Inc
Priority to EP07854073A priority Critical patent/EP2084670A2/en
Priority to CA002666064A priority patent/CA2666064A1/en
Priority to JP2009533470A priority patent/JP2010507175A/en
Publication of WO2008048940A2 publication Critical patent/WO2008048940A2/en
Publication of WO2008048940A3 publication Critical patent/WO2008048940A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing

Abstract

This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.
PCT/US2007/081428 2006-10-17 2007-10-15 Graphics processing unit with shared arithmetic logic unit WO2008048940A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP07854073A EP2084670A2 (en) 2006-10-17 2007-10-15 Graphics processing unit with shared arithmetic logic unit
CA002666064A CA2666064A1 (en) 2006-10-17 2007-10-15 Graphics processing unit with shared arithmetic logic unit
JP2009533470A JP2010507175A (en) 2006-10-17 2007-10-15 Graphics processing unit that uses a shared arithmetic processing unit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/550,344 2006-10-17
US11/550,344 US8009172B2 (en) 2006-08-03 2006-10-17 Graphics processing unit with shared arithmetic logic unit

Publications (2)

Publication Number Publication Date
WO2008048940A2 WO2008048940A2 (en) 2008-04-24
WO2008048940A3 true WO2008048940A3 (en) 2009-04-30

Family

ID=39314778

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/081428 WO2008048940A2 (en) 2006-10-17 2007-10-15 Graphics processing unit with shared arithmetic logic unit

Country Status (8)

Country Link
US (1) US8009172B2 (en)
EP (1) EP2084670A2 (en)
JP (1) JP2010507175A (en)
KR (1) KR20090079241A (en)
CN (1) CN101523442A (en)
CA (1) CA2666064A1 (en)
TW (1) TW200830220A (en)
WO (1) WO2008048940A2 (en)

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US20130271465A1 (en) * 2011-12-30 2013-10-17 Franz P. Clarberg Sort-Based Tiled Deferred Shading Architecture for Decoupled Sampling
KR102001222B1 (en) 2015-07-07 2019-07-17 삼성전자주식회사 Signal processing apparatus and method
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Also Published As

Publication number Publication date
CN101523442A (en) 2009-09-02
JP2010507175A (en) 2010-03-04
KR20090079241A (en) 2009-07-21
TW200830220A (en) 2008-07-16
US20080030512A1 (en) 2008-02-07
WO2008048940A2 (en) 2008-04-24
EP2084670A2 (en) 2009-08-05
US8009172B2 (en) 2011-08-30
CA2666064A1 (en) 2008-04-24

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