WO2008051503A2 - Light-emitter-based devices with lattice-mismatched semiconductor structures - Google Patents

Light-emitter-based devices with lattice-mismatched semiconductor structures Download PDF

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Publication number
WO2008051503A2
WO2008051503A2 PCT/US2007/022392 US2007022392W WO2008051503A2 WO 2008051503 A2 WO2008051503 A2 WO 2008051503A2 US 2007022392 W US2007022392 W US 2007022392W WO 2008051503 A2 WO2008051503 A2 WO 2008051503A2
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Prior art keywords
semiconductor material
light
crystalline semiconductor
trench
emitting device
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PCT/US2007/022392
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French (fr)
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WO2008051503A3 (en
Inventor
Jizhong Li
Anthony J. Lochtefeld
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Amberwave Systems Corporation
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Publication of WO2008051503A2 publication Critical patent/WO2008051503A2/en
Publication of WO2008051503A3 publication Critical patent/WO2008051503A3/en

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    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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Definitions

  • This invention relates generally to semiconductor processing, and particularly to formation of light-emitting devices based on lattice-mismatched semiconductor structures.
  • Particularly desirable is an epitaxial solution that can (a) achieve substantial elimination of defects arising from lattice mismatch with no more than about 1 ⁇ m of growth, and (b) manage large degrees of thermal mismatch (i.e., mismatch between the thermal expansion coefficients of the substrate and the epitaxial layers).
  • ART Aspect ratio trapping
  • Embodiments of the invention include the formation of a GaAs-based edge emission laser on a silicon substrate.
  • An aspect of the invention features a structure having, in various embodiments, a trench defined in a dielectric layer disposed over a substrate comprising a first crystalline semiconductor material.
  • a second crystalline semiconductor material is disposed in the trench, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material.
  • a light-emitting device is disposed over and in contact with at least a portion of the second crystalline semiconductor material.
  • the trench may have a height h and a width w, and a ratio of h/w >1.
  • the light- emitting device may be a laser or a light-emitting diode, either of which may include GaAs, AlAs, and/or AlGaAs layers.
  • the laser or light-emitting diode may include InP, GaP, AlP, InAs, AlAs, GaAs, InSb, AlSb, GaSb, InN, and/or their ternary or quaternary compounds.
  • the first crystalline semiconductor material may include or consist essentially of at least one of a group IV element or compound, a II- VI compound, or a III- V compound.
  • the second crystalline material may include a II-VI compound and/or a IH-V compound.
  • a top contact may be disposed over at least a portion of the light-emitting device and a second contact may be disposed over and in contact with a portion of the substrate.
  • a plurality of trenches may be formed in the dielectric layer, with the second crystalline semiconductor material disposed in each trench. The distance between two adjacent trenches may be at least equal to an average width of the adjacent trenches.
  • the light-emitting device may include a laser or a light-emitting diode (LED) epitaxial structure disposed in the trench.
  • the second crystalline semiconductor material may extend above the dielectric layer, and the light-emitting device may comprise a laser or an LED epitaxial structure disposed above a top surface of the dielectric layer.
  • the invention features a method for forming a structure. Embodiments of the method include forming a trench having a dielectric sidewall and a bottom surface adjacent a substrate comprising a first crystalline semiconductor material. At least a portion of the trench may be filled with a second crystalline semiconductor material lattice- mismatched to the first crystalline semiconductor material.
  • a light-emitting device may be defined over and in contact with at least a portion of the second crystalline semiconductor material.
  • the trench may have a height h and a width w, and a ratio of h/w >1.
  • the light- emitting device may be a laser or a light-emitting diode.
  • the trench may be filled by selective epitaxy.
  • the step for forming a trench further includes defining additional trenches
  • the step for filling the trench further includes forming a coalesced layer of the second crystalline semiconductor above the trenches, and the step of defining a light-emitting device forms the device over the trenches.
  • the active region of the light- emitting device may be formed within the trench.
  • the invention features a structure having a dielectric sidewall disposed proximate a top surface of a substrate comprising a first crystalline material.
  • a second crystalline semiconductor material is disposed proximate the dielectric sidewall, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material.
  • a cascade superlattice may be disposed over and in contact with at least a portion of the second crystalline semiconductor material.
  • the invention features a method for forming a trench-based light- emitting device.
  • Embodiments of the method include forming a trench adjacent a substrate, the trench (i) having a non-crystalline sidewall, (ii) having a width w, (iii) having a height h above a bottom surface of the trench, and (iv) having a ratio of h/w >1, the bottom surface of the trench including an exposed surface of the substrate.
  • a crystalline semiconductor material may be epitaxially grown in at least a portion of the trench, the crystalline semiconductor material being lattice-mismatched to the substrate.
  • a light-emitting device may be formed over the crystalline semiconductor material, an active region of the light-emitting device being at least partially disposed within the trench.
  • the invention features a method for forming a light-emitting device using lattice-mismatched materials and planarization. Embodiments of the method include forming an opening having a non-crystalline sidewall disposed above a surface of a substrate, the substrate comprising a first crystalline semiconductor material. A second crystalline semiconductor material may be formed in the opening, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material. A surface of the second crystalline semiconductor material may be planarized. A light-emitting device may be formed at least partially above the planarized surface of the second crystalline semiconductor material.
  • Figures 1-5 are schematic cross-sectional views illustrating a method for formation of a device on a semiconductor substrate in accordance with an aspect of the invention
  • Figure 6 is a simplified schematic perspective view of a device formed in accordance with the method illustrated in Figures 1-5;
  • Figures 7a-7d are schematic cross-sectional views illustrating alternative structures formed in accordance with aspects of the invention.
  • Figures 8a-8c are schematic cross-sectional views illustrating a method for formation of a V-groove laser diode in accordance with an aspect of the invention.
  • Figures 9a-9b are schematic cross-sectional views illustrating a method for formation of III- V cascade lasers in accordance with an aspect of the invention.
  • Figure 10 is a plan view illustrating examples of photonic patterning.
  • Figures 11 a-b are plan views illustrating one-dimensional laser diode and light- emitting diode arrays. Detailed Description
  • a substrate 100 includes a first crystalline semiconductor material Sl.
  • the substrate 100 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate.
  • the substrate 100 may include or consist essentially of the first semiconductor material Sl, such as a group IV element, e.g., germanium or silicon.
  • substrate 100 includes or consists essentially of n-type (100) silicon.
  • a dielectric layer 110 is formed over the semiconductor substrate 100.
  • the dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride or silicon dioxide.
  • the dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). As discussed below, the dielectric layer may have a thickness t) corresponding to a desired height h of crystalline material to be deposited in a trench formed through the dielectric layer. In some embodiments, the thickness ti of the dielectric layer 110 is in the range of 25-1000 nm. In a preferred embodiment, the thickness ti is 500 nm.
  • PECVD plasma-enhanced chemical vapor deposition
  • a mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110.
  • the mask is patterned to expose at least a portion of the dielectric layer 110.
  • the exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define a trench 120.
  • Trench 120 may be defined by at least one sidewall 130, and may extend to a top surface 135 of the substrate 100.
  • the height h of the sidewall 130 corresponds to the thickness ti of the dielectric layer 110, and may be at least equal to a predetermined distance H from a top surface 135 of the substrate.
  • the predetermined vertical distance H is a minimum distance at which a majority of defects in a lattice-mismatched material formed in the trench terminate at the sidewall 130.
  • the trench may be substantially rectangular in terms of cross-sectional profile, a plan view, or both, and have a width w that is smaller than a length L (not shown) of the trench.
  • the width w of the trench may be less than about 500 nm, e.g., about 10 - 100 nm, and the length L of the trench may exceed each of w and H.
  • a ratio of the height h of the trench to the width w of the trench 120 may be > 0.5, e.g., > 1.
  • the crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II- VI compound.
  • suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide.
  • suitable III- V compounds include gallium antimonide, gallium arsenide, gallium nitride, gallium phosphide, aluminum antimonide, aluminum arsenide, aluminum nitride, aluminum phosphide, indium antimonide, indium arsenide, indium nitride, indium phosphide, and their ternary or quaternary compounds.
  • suitable H-VI compounds include zinc selenide, zinc sulfide, cadmium selenide, cadmium sulfide, and their ternary or quaternary compounds.
  • the crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD).
  • MOCVD metal-organic chemical vapor deposition
  • APCVD atmospheric-pressure CVD
  • LPCVD low- (or reduced-) pressure CVD
  • UHVCVD ultra-high-vacuum CVD
  • MBE molecular beam epitaxy
  • ALD atomic layer deposition
  • selective epitaxial growth typically includes introducing a source gas into the chamber.
  • the source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen.
  • the reactor chamber may be heated by, for example, RF-heating.
  • the growth temperature in the chamber may range from about 300 °C to about 900 °C, depending on the composition of the crystalline material.
  • the growth system may also utilize low-energy plasma to enhance the layer growth kinetics.
  • the epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, CA; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.
  • a two-step growth technique is used to form high-quality crystalline material 140, consisting essentially of GaAs, in the trench 120.
  • the substrate 100 and dielectric layer 1 10 are thermally annealed with hydrogen at approximately 800°C for approximately 15 minutes to desorb a thin volatile oxide from the substrate surface 135 that may be produced during pre-epitaxy wafer preparation.
  • Chamber pressure during annealing may be in the range of approximately 50-100 torr, for example 75 torr.
  • the chamber temperature is cooled down with hydrogen flow.
  • APBs anti-phase boundaries
  • This step helps ensure uniform coverage of the trench surface with an As-As monolayer.
  • This pre-exposure is achieved by flowing AsH 3 gas through the reactor at a temperature of approximately 460°C.
  • the precursor triethylgallium (TEG) or trimethylgallium (TMG) is introduced into the chamber together with AsH 3 gas at a higher growth temperature, e.g., approximately 500°C to 550°C promote the initial GaAs nucleation process on the As pre-layer surface.
  • This high-temperature process helps ensure that the Ga atoms are sufficiently mobile to avoid GaAs cluster formation.
  • a slow growth rate of about 2 to 4 run per minute with V/III ratio of about 50 may be used to obtain this initial GaAs layer, with a thickness in the range of about 50 to 100 nm.
  • a layer of n-type GaAs having a thickness of 1 to 2 ⁇ m is grown at a constant growth temperature of approximately 68O 0 C and a V/III ratio of approximately 80 to obtain defect-free GaAs material inside the trench 120.
  • the GaAs epitaxial layer thickness t 2 may be greater than the dielectric mask thickness tj.
  • the GaAs material may have a mushroom-type cross-sectional profile with lateral over growth over the dielectric layer 110; the top portion of the GaAs material may coalesce with GaAs formed in neighboring trenches (not shown) to form an epitaxial layer.
  • the width W 2 of the crystalline material 140 extending over a top surface 160 of the dielectric layer 110 may be greater than the width w of the trench 120. In this case, a small void may be formed between the laterally grown GaAs layer and the top surface 160 of the dielectric layer 110.
  • the overall layer thickness t 2 of the crystalline material 140 may be monitored by using pre-calibrated growth rates and in situ monitoring equipment, according to methods routinely employed in the art.
  • dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the trench 120 in the dielectric material 110 at or below the predetermined vertical distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the trench 140. Accordingly, the upper portion of the crystalline material is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be substantially eliminated from the upper portion of the crystalline material.
  • the crystalline material 140 may be considered to have two portions: a lower portion for trapping dislocation defects and an upper portion which either (a) incorporates the laser or LED epitaxial layers or (b) serves as a template for the subsequent epitaxial growth of the laser or LED epitaxial layers.
  • the height h of the crystalline material thus has two components: the height h trapp i n g of the lower portion (where defects are concentrated) and the height h up per of the upper portion (which is largely free of defects).
  • the height h tra p P i n g of the trapping portion may be selected from a range of about 1 A w ⁇ hipping ⁇ 2w, to ensure effective trapping of dislocation defects.
  • hipping required may depend upon the type of dislocation defects encountered, which may depend on the materials used, and also upon the orientation of the trench sidewalls.
  • the height hippi n g can be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the upper portion, so that deleterious effects of dislocation defects upon device performance are not experienced.
  • h t rapping may be, e.g., 10 - 100 nm greater than required for effective trapping of defects.
  • the height h upper may be selected from the range of approximately 1 A w ⁇ h up p er ⁇ 10w.
  • the predetermined distance H necessary to trap defects is, typically, approximately equal to a width between 1 A w and 2 w, where w is the width of the trench. This range is based on the range of intersection angles of approximately 30 degrees through 60 degrees; then, tan(30°)w ⁇ H ⁇ tan(60°)w, which roughly corresponds to 1 A w ⁇ H ⁇ 2w.
  • a planarization step such as, e.g., chemical-mechanical polishing (CMP) may be used to planarize a top surface 170 of the crystalline material 140 within a roughness level preferably no greater than 20 nm, to allow the formation of good quality films thereon.
  • CMP chemical-mechanical polishing
  • the thickness t 3 of the portion of the crystalline material 140 disposed within the trench 120 is 1 ⁇ m and the thickness t 4 of the portion of the crystalline material 140 disposed above the top surface 160 of the dielectric layer 110 is about 0.5 ⁇ m.
  • a planarization step such as, e.g., CMP is used to planarize a top surface of the crystalline material 140 within a roughness level preferably no greater than 20 nm, to ensure that the top surface of the crystalline material 140 is substantially co-planar with the top surface 160 of the dielectric material 110.
  • a laser epitaxial structure 300 may be formed over the crystalline material 140.
  • the laser epitaxial structure 300 may be a GaAs-based laser structure including layers of GaAs/InGaAs/ AlGaAs, formed according to methods known in the art.
  • the laser structure may include, e.g., a -1.5 ⁇ m thick n-GaAs base layer 310, a -0.30 ⁇ m W-Al 0-04 GaAs graded lower cladding layer 312, a ⁇ 1.3 ⁇ m thick «- Al 04 GaAs cladding layer 314, an undoped -0.3 ⁇ m Al 04- C 2 GaAs graded lower confining layer 316, an undoped -7 nm In 02 GaAs single quantum well layer 318, an undoped -0.3 ⁇ m Al 02-O 4 GaAs graded upper confining layer 320, a -1.3 ⁇ m thick p-Al o.4 GaAs cladding layer 322, a -0.30 ⁇ m thick p-Al o.4-o GaAs graded upper cladding 324, and a -0.1 ⁇ m thick p + - GaAs contact layer 326.
  • These layers may be formed by epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, MOCVD, APCVD, LPCVD, UHVCVD, MBE, or ALD.
  • a growth temperature may be approximately 550 - 680 °C for the GaAs layer and approximately 650 - 800 0 C for the AlGaAs layers.
  • GaAs- based laser epitaxial structures are grown on offcut Si substrates oriented about 2° off (100) towards the ⁇ 011 > direction in an AIXTRON 2600 MOCVD reactor at about 75 torr.
  • TMG and trimethylaluminum may be used as group-Ill sources, and arsine (AsH 3 ) may be used as the group-V source.
  • Silane (SiH 4 ) and carbon tetrachloride (CCl 4 ) may be used as n- and p-dopant sources, respectively.
  • Hydrogen may be used as a carrier gas.
  • an LED epitaxial structure 300' may be formed over the crystalline material 140.
  • the surface-emitting epitaxial LED structure includes a base layer 310', a lower cladding layer 314', an undoped lower confining layer 316', an undoped single- or multiple-quantum- well active region 318', an undoped upper confining layer 320', an upper cladding layer 322', and a heavily doped p-type contact layer 326'.
  • Metal contacts may be formed over the p-type contact layer 326' using the process described below with reference to Figure 5. It is often desired that light emission for LEDs be through the top surface. For this reason, a transparent top-contact material such as indium tin oxide (ITO) may be used.
  • ITO indium tin oxide
  • a non-transparent contact may be used, preferably not covering an entire top surface of the LED epitaxial structure.
  • an RIE etch step may be performed to remove a portion of the laser epitaxial structure 300 that may extend laterally over the dielectric layer 110. This etch may remove defects that may arise from coalescence between neighboring selective epitaxial regions. Referring also to Figure 6, at the same time, this etch may define the front and back facets 600, 610 of an edge-emission laser structure 620. The etch may be performed with, for example, argon and chlorine plasmas.
  • a metal layer is deposited over the dielectric layer, for example via evaporation, and patterned to define a top contact 520.
  • the metal layer may have a thickness of, e.g., approximately 150 run.
  • the top contact 520 is a p-type contact and includes or consists essentially of Ti/Pt/Au. Following contact deposition, an anneal of approximately 350-450°C for approximately 10 minutes may be performed to ensure good electrical contact with the laser epitaxial structure 300.
  • a second metal contact 530 e.g., a bottom metal contact, is defined adjacent the substrate 100.
  • a backside of the substrate 100 may be thinned before the second metal contact is defined. In an embodiment, the second metal contact is formed on the backside of the substrate.
  • the second metal contact contacts the topside of the substrate through a window defined in the overlying dielectric layer(s) 110 (see Figures 7a-7d ).
  • the second metal contact may have a thickness of, e.g., approximately 500 nm.
  • the second metal contact is an n-type contact and includes or consists essentially of Al formed by evaporation on an n-type Si substrate.
  • a standard laser facet coating process is used, according to methods known in the art, to obtain reflectivity of approximately 3% and approximately 95% for front and back facets, respectively.
  • the resulting structure is a completed laser device that can be integrated into circuits formed on a semiconductor die.
  • the laser device is a light-emitting device 620 including laser epitaxial structure 300.
  • FIG. 1-6 A GaAs-based laser structure growth and device preparation process are illustrated in Figures 1-6.
  • the figures are not to scale, and a thick laser structure is illustrated to demonstrate the general process sequence.
  • This laser structure includes a single InGaAs quantum well centered in a waveguide, graded-index separate confinement heterostructure (GRJNSCH) with 1.3- ⁇ m-thick Al 04 Ga 06 As cladding layers.
  • GRJNSCH graded-index separate confinement heterostructure
  • the illustrated device is designed for operation at a wavelength of 980 nm.
  • the process may be utilized to form other structures based on ART technology. For instance, for small dimensional devices such as nano-scale light emitters, the full epitaxial structure for the laser may be confined inside a single trench.
  • CMP process and laser mesa contact process may be eliminated or simplified. Also, as discussed below, this method may be used to fabricate broad-area light emitters or emitter arrays, with large device dimensions and covering a plurality of trenches.
  • this method may be used to fabricate broad-area light emitters or emitter arrays, with large device dimensions and covering a plurality of trenches.
  • laser or LED epitaxial structure 300 or 300' may be formed in trench 120.
  • Dislocation defects 150 may be trapped within the lower trench region 710.
  • a planarization process, for example, CMP, of the crystalline material 140 is not necessary, as growth of the crystalline material 140 is halted before the crystalline material completely fills the trench 120.
  • the crystalline material 140 defines a portion of the laser or LED epitaxial structure 300 or 300'. In other embodiments, the crystalline material 140 provides a template for the formation of the laser or LED epitaxial structure 300 or 300' in the trench 120.
  • Top contact 520 is formed over the laser or LED epitaxial structure 300 or 300'.
  • the second metal contact 530 contacts the topside of the substrate 100 through a window defined in the overlying dielectric layer(s) 110 (see Figures 7a-7d ).
  • laser or LED epitaxial structure 300 or 300' may be formed on a top portion of the crystalline material 140 extending above the top surface 160 of the dielectric layer 110.
  • a plurality of trenches i.e., two or more adjacent trenches may each include crystalline material 140 and a laser or LED epitaxial structure 300 or 300' disposed over the crystalline material 140 in the trench, as discussed with reference to Figure 7a.
  • the distance d between two adjacent trenches may be at least equal to the average width of the adjacent trenches.
  • a patterned metal or a transparent top contact 520 may be formed over and in contact with each of the laser or LED epitaxial structures 300 or 300', thereby providing a broad-area laser or LED.
  • two or more adjacent trenches may each include crystalline semiconductor 140 extending above the top surface 160 of the dielectric layer 110, as described above with reference to Figures 1-6 and Figure 7b. Lateral growth of the crystalline material 140 between the adjacent trenches 120 results in the coalescence of the top portions of the crystalline material into a single epitaxial film 700 of crystalline material 140.
  • a planarization process for example, CMP, may be performed on a top surface of the epitaxial film 700.
  • crystalline semiconductor material 140 is formed in a trench 120, and extends beyond the top surface 160 of dielectric 110.
  • an electrically insulating diode (EID) (not shown) is added. The EID may be formed from two layers of semiconductor material, and the crystalline semiconductor material 140 may be the first of those layers.
  • the EID may be positioned between the crystalline material 140 formed in trench 120 and the light-emitting device 300 or 300'.
  • An n-contact 530 may be used to make an electrical connection to the crystalline material 140 above the trench 120, for example, near the top surface 160 of the dielectric layer 120; an EID may preferably then be used to prevent leakage current from the substrate 100 into the trench 120.
  • the crystalline material 140 is preferably planarized by, for example, CMP to within a roughness level preferably no greater than 20 nm.
  • the top surface of the crystalline semiconductor material 140 may then be modified with a selective etching process to create a V groove 800 in the surface of the crystalline material 140.
  • the V groove may be formed as follows.
  • An upper dielectric layer 810 including a dielectric material, e.g., Si 3 N 4 , may be formed on the crystalline semiconductor material 140 using a deposition process, e.g., PECVD, and patterned by photolithography and etching.
  • the pattern in the upper dielectric layer 910 may include stripes oriented along the trench 120 and may have dimensions similar to those of the lower dielectric layer 110. In an embodiment, the stripes defined by the upper dielectric layer have dimensions greater than those of the lower dielectric layer 110, so that the upper dielectric layer 140 covers some trenches 120 but not other trenches 120.
  • the pattern in the upper dielectric layer may be defined by a wet etch, e.g., a buffer oxide etchant.
  • the appropriate wet etch etches the crystalline semiconductor material 140 selectively with respect to the upper dielectric layer and dielectric layer 110.
  • the wet-etch composition is selected to define facets in the crystalline semiconductor material 140 to form the V-groove.
  • the patterned upper dielectric layer may be removed.
  • a diode structure 300 is grown on top of the V-shaped layer to create a V-groove laser diode. This design may be applied to the fabrication of single or trenched array laser diodes.
  • a multiple stage cascade structure 900 may be formed with a preferred structure design and controlled layer thicknesses, and may include, for example, InP/GalnAs/AlInAs, GaAs/AlGaAs or Si/SiGe/Si superlattice layers.
  • the cascade structure 900 may be formed within trench 120 above dislocation defects 150.
  • Each layer forming the cascade structure 900 may range in thickness from, for example, 1 nm to 5 ran, and may be formed with an epitaxial process, for example, MBE or MOCVD.
  • the layers of the superlattice 900 may be formed in groups of, for example, 5-10 layers, where the composition and number of the layers within a group defines the output characteristics of the laser. Furthermore, the group of layers may be repeated, for example, 10-30 times, to increase the output power of the laser. The number of layers within a group and number of groups may be repeated as many times as the height of the crystalline semiconductor material 140 allows. Growth of the cascade structure 900 may terminated before coalesced growth occurs, to produce a near- or middle-infrared laser with peak emission at a wavelength between 3 ⁇ m and 17 ⁇ m. In some embodiments, the crystalline material 140 itself provides a template for the formation of the cascade superlattice structure 900 above the trench 120.
  • the top contact 520 is formed over the cascade superlattice structure 900.
  • the second metal contact 530 contacts the bottom side of the thinned substrate 100.
  • multiple-wavelength cascade lasers may be formed on a surface that is preferably planarized, e.g., by CMP to within a roughness level preferably no greater than 20 nm. Different wavelength emissions may be accomplished by multiple sectional etching processes. The emission wavelength is tuned over a wide range by applying a voltage using multiple-section contacts. In an embodiment, one or all of the multiple wavelength sections of the cascade superlattice structure 900 has its own n-contact 530.
  • the process described above with respect to Figures 1-7 may be modified to create photonic crystals.
  • the dielectric layer 110 may be first deposited, and then etched to produce trenches and shapes other than trenches, e.g., circular holes. These shapes correspond to features in crystalline material 140 that may be formed to direct emissions from a laser.
  • a photonic mask layer (not shown) may be created to define these shapes and the dielectric layer 110 is selectively removed, e.g., etched, to form the desired shapes.
  • openings in the patterned dielectric layer 110 are filled with the crystalline semiconductor material 140.
  • an EID as described above is formed.
  • the dielectric layer may then be wholly or partially removed to form an air-spaced photonic crystal array, i.e., having features separated by air.
  • part of the dielectric layer is left in place to change the refraction index of the boundary between the crystalline semiconductor material 140 and the dielectric layer 110 in the photonic crystal array.
  • this crystal array is used with a laser 1010 as an optical DBR reflector 1020, beam divider 1030, or waveguide 1040, as illustrated in Figure 10.
  • the method described in Figures 1-7 may be modified to form a number of light-emitting devices arranged in a one-dimensional array.
  • each trench may contain a light-emitting device, such as a laser diode or a light-emitting diode.
  • a light-emitting device such as a laser diode or a light-emitting diode.
  • FIG 1 Ia a plan view of a one-dimensional array of light-emitting diodes is shown.
  • the p- contact 520 may cover only part of the top surface of the diode structure 300' to permit the diode to emit light perpendicular to the page from the portion of the top surface of the diode structure 300' not covered by p-contact 520.
  • Each diode in the array may be electrically connected by forming a layer of metal 1110 at one end of the trenches 120 that is electrically connected to each diode's p-contact 520.
  • Neighboring diodes may be electrically isolated with a dielectric isolator structure 1130.
  • Figure 1 Ib a plan view of a one-dimensional array of laser diodes is shown.
  • the p-contact 520 may cover the entire top surface of the laser structure 300, and the laser may output light in a direction 1120, within the plane of the page.
  • Each laser in the one-dimensional array may be electrically connected by forming a layer of metal 1110 at one end of the trenches 120 that is electrically connected to each laser's p-contact 520.
  • Neighboring lasers may be electrically isolated with a dielectric isolator structure 1130.
  • Each light-emitting device in a one-dimensional array may be formed inside its own trench 120, as shown in Figure 7a. In this case, each trench-defined device may be electrically isolated from a neighboring device or devices by portions of the dielectric layer 110.
  • the light-emitting devices in the one-dimensional array are formed above the trench 120, as shown in Figure 7b, in the single epitaxial layer resulting from the crystalline semiconductor material 140 coalescing above and between neighboring trenches. In this case, an etch step may be performed to electrically isolate the devices.
  • This process may include the steps of (i) forming a masking layer over the light-emitting devices, (ii) removing material from the masking layer to expose portions of the crystalline semiconductor material 140 where electrical continuity is to be broken, for example, the midpoint between two trench- based light-emitting devices, and (iii) removing the exposed crystalline semiconductor material 140 with an etching process.
  • the gaps formed when the exposed crystalline semiconductor material 140 is removed may be filled with, for example, a dielectric material 1130.

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Abstract

Some aspects for the invention. include a method and a structure including a light -emitting device (300, 300') disposed over a second crystalline semiconductor material (140) formed over a semiconductor substrate (100) comprising a first crystalline material. In some embodiments, the second crystalline semiconductor material (140) is proved in a trench (120) defined in a dielectric layer (110) which is disposed over said substrate (100). In some embodiments, the second crystalline semiconductor material is a lattice-mismatched to the first crystalline semiconductor material.

Description

LIGHT-EMITTER-BASED DEVICES WITH LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES
Related Application
[0001] This application claims priority to and the benefits of U.S. Provisional Patent Application Serial No. 60/852,781, filed on October 19, 2006, the entire disclosure of which is hereby incorporated by reference.
Field of the Invention [0002] This invention relates generally to semiconductor processing, and particularly to formation of light-emitting devices based on lattice-mismatched semiconductor structures.
Background
[0003] Achieving epitaxial growth and fabrication of high-performance optoelectronic devices (i.e., HI-V devices) on silicon substrates has been a goal of the semiconductor industry for decades. A major challenge has been to overcome the large lattice-mismatch and thermal- expansion differences between these two fundamentally different material systems. Various methods have been used in the past to demonstrate III-V-based lasers on Si substrates, for example utilizing very thick (-10 micrometer (μm)) epitaxial buffer layers (see "Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers," Michael E. Groenert, Christopher W. Leitz, Arthur J. Pitera, and Vicky Yang, Journal of Applied Physics 93 362 (2003) ) or utilizing wafer bonding between a Si wafer and epitaxial layers grown on a III-V substrate (see "Electrically pumped hybrid AlGalnAs-silicon evanescent laser," Alexander W. Fang, Hyundai Park, Oded Cohen, Richard Jones, Mario J. Paniccia, and John E. Bowers, Optics Express, Vol. 14, Issue 20, pp. 9203-9210 (2006) ). However, these methods may have disadvantages from either an economic or a technical standpoint. It may be desirable to avoid both (a) thick epitaxial layers that may be time-consuming to grow, and may suffer from thermal mismatch problems, and (b) bonding between Si and III-V wafers that can suffer from poor yield, thermal mismatch problems, and a lack of commercially available III-V substrates compatible with the Si substrates used today in leading-edge manufacturing. Particularly desirable is an epitaxial solution that can (a) achieve substantial elimination of defects arising from lattice mismatch with no more than about 1 μm of growth, and (b) manage large degrees of thermal mismatch (i.e., mismatch between the thermal expansion coefficients of the substrate and the epitaxial layers).
Summary
[0004] Aspect ratio trapping (ART) technology enables the formation of high-quality semiconductor materials on lattice-mismatched substrates. By properly choosing mask configurations, crystal orientations, and epitaxial growth conditions, various material defects may be trapped in a small localized area within a relatively thin epitaxial layer. Furthermore, because the ART regions are relatively small in area, thermal mismatch problems are substantially reduced, because ART islands can expand and contract elastically (producing no defects) with changes in processing temperature, instead of plastically (producing defects). ART technology greatly increases the quality of lattice-mismatched materials that may be achieved, e.g., with the growth of III- V materials on Si substrates. The straightforward process enables reliable and reproducible results. [0005] Embodiments of the invention include the formation of a GaAs-based edge emission laser on a silicon substrate.
[0006] An aspect of the invention features a structure having, in various embodiments, a trench defined in a dielectric layer disposed over a substrate comprising a first crystalline semiconductor material. A second crystalline semiconductor material is disposed in the trench, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material. A light-emitting device is disposed over and in contact with at least a portion of the second crystalline semiconductor material.
[0007] The trench may have a height h and a width w, and a ratio of h/w >1. The light- emitting device may be a laser or a light-emitting diode, either of which may include GaAs, AlAs, and/or AlGaAs layers. In some embodiments, the laser or light-emitting diode may include InP, GaP, AlP, InAs, AlAs, GaAs, InSb, AlSb, GaSb, InN, and/or their ternary or quaternary compounds.
[0008] The first crystalline semiconductor material may include or consist essentially of at least one of a group IV element or compound, a II- VI compound, or a III- V compound. The second crystalline material may include a II-VI compound and/or a IH-V compound. [0009] A top contact may be disposed over at least a portion of the light-emitting device and a second contact may be disposed over and in contact with a portion of the substrate. A plurality of trenches may be formed in the dielectric layer, with the second crystalline semiconductor material disposed in each trench. The distance between two adjacent trenches may be at least equal to an average width of the adjacent trenches. [0010] The light-emitting device may include a laser or a light-emitting diode (LED) epitaxial structure disposed in the trench. The second crystalline semiconductor material may extend above the dielectric layer, and the light-emitting device may comprise a laser or an LED epitaxial structure disposed above a top surface of the dielectric layer. [0011] In another aspect, the invention features a method for forming a structure. Embodiments of the method include forming a trench having a dielectric sidewall and a bottom surface adjacent a substrate comprising a first crystalline semiconductor material. At least a portion of the trench may be filled with a second crystalline semiconductor material lattice- mismatched to the first crystalline semiconductor material. A light-emitting device may be defined over and in contact with at least a portion of the second crystalline semiconductor material. [0012] The trench may have a height h and a width w, and a ratio of h/w >1. The light- emitting device may be a laser or a light-emitting diode. The trench may be filled by selective epitaxy. In an embodiment, the step for forming a trench further includes defining additional trenches, the step for filling the trench further includes forming a coalesced layer of the second crystalline semiconductor above the trenches, and the step of defining a light-emitting device forms the device over the trenches. In another embodiment, the active region of the light- emitting device may be formed within the trench.
[0013] In another aspect, the invention features a structure having a dielectric sidewall disposed proximate a top surface of a substrate comprising a first crystalline material. A second crystalline semiconductor material is disposed proximate the dielectric sidewall, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material. A cascade superlattice may be disposed over and in contact with at least a portion of the second crystalline semiconductor material.
[0014] In another aspect, the invention features a method for forming a trench-based light- emitting device. Embodiments of the method include forming a trench adjacent a substrate, the trench (i) having a non-crystalline sidewall, (ii) having a width w, (iii) having a height h above a bottom surface of the trench, and (iv) having a ratio of h/w >1, the bottom surface of the trench including an exposed surface of the substrate. A crystalline semiconductor material may be epitaxially grown in at least a portion of the trench, the crystalline semiconductor material being lattice-mismatched to the substrate. A light-emitting device may be formed over the crystalline semiconductor material, an active region of the light-emitting device being at least partially disposed within the trench. [0015] In another aspect, the invention features a method for forming a light-emitting device using lattice-mismatched materials and planarization. Embodiments of the method include forming an opening having a non-crystalline sidewall disposed above a surface of a substrate, the substrate comprising a first crystalline semiconductor material. A second crystalline semiconductor material may be formed in the opening, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material. A surface of the second crystalline semiconductor material may be planarized. A light-emitting device may be formed at least partially above the planarized surface of the second crystalline semiconductor material.
Brief Description of Figures [0016] In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
[0017] Figures 1-5 are schematic cross-sectional views illustrating a method for formation of a device on a semiconductor substrate in accordance with an aspect of the invention; [0018] Figure 6 is a simplified schematic perspective view of a device formed in accordance with the method illustrated in Figures 1-5;
[0019] Figures 7a-7d are schematic cross-sectional views illustrating alternative structures formed in accordance with aspects of the invention;
[0020] Figures 8a-8c are schematic cross-sectional views illustrating a method for formation of a V-groove laser diode in accordance with an aspect of the invention; and
[0021] Figures 9a-9b are schematic cross-sectional views illustrating a method for formation of III- V cascade lasers in accordance with an aspect of the invention.
[0022] Figure 10 is a plan view illustrating examples of photonic patterning.
[0023] Figures 11 a-b are plan views illustrating one-dimensional laser diode and light- emitting diode arrays. Detailed Description
[0024] Referring to Figure 1, a substrate 100 includes a first crystalline semiconductor material Sl. The substrate 100 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of the first semiconductor material Sl, such as a group IV element, e.g., germanium or silicon. In an embodiment, substrate 100 includes or consists essentially of n-type (100) silicon. [0025] A dielectric layer 110 is formed over the semiconductor substrate 100. The dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride or silicon dioxide. The dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). As discussed below, the dielectric layer may have a thickness t) corresponding to a desired height h of crystalline material to be deposited in a trench formed through the dielectric layer. In some embodiments, the thickness ti of the dielectric layer 110 is in the range of 25-1000 nm. In a preferred embodiment, the thickness ti is 500 nm.
[0026] A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110. The mask is patterned to expose at least a portion of the dielectric layer 110. The exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define a trench 120. Trench 120 may be defined by at least one sidewall 130, and may extend to a top surface 135 of the substrate 100. The height h of the sidewall 130 corresponds to the thickness ti of the dielectric layer 110, and may be at least equal to a predetermined distance H from a top surface 135 of the substrate. The predetermined vertical distance H is a minimum distance at which a majority of defects in a lattice-mismatched material formed in the trench terminate at the sidewall 130. [0027] The trench may be substantially rectangular in terms of cross-sectional profile, a plan view, or both, and have a width w that is smaller than a length L (not shown) of the trench. For example, the width w of the trench may be less than about 500 nm, e.g., about 10 - 100 nm, and the length L of the trench may exceed each of w and H. A ratio of the height h of the trench to the width w of the trench 120 may be > 0.5, e.g., > 1. [0028] A second crystalline semiconductor material S2, i.e., crystalline material 140, is formed in the trench 120. The crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II- VI compound. Examples of suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide. Examples of suitable III- V compounds include gallium antimonide, gallium arsenide, gallium nitride, gallium phosphide, aluminum antimonide, aluminum arsenide, aluminum nitride, aluminum phosphide, indium antimonide, indium arsenide, indium nitride, indium phosphide, and their ternary or quaternary compounds. Examples of suitable H-VI compounds include zinc selenide, zinc sulfide, cadmium selenide, cadmium sulfide, and their ternary or quaternary compounds.
[0029] The crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300 °C to about 900 °C, depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics. [0030] The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, CA; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands. [0031] In an exemplary process, a two-step growth technique is used to form high-quality crystalline material 140, consisting essentially of GaAs, in the trench 120. First, the substrate 100 and dielectric layer 1 10 are thermally annealed with hydrogen at approximately 800°C for approximately 15 minutes to desorb a thin volatile oxide from the substrate surface 135 that may be produced during pre-epitaxy wafer preparation. Chamber pressure during annealing may be in the range of approximately 50-100 torr, for example 75 torr. After annealing, the chamber temperature is cooled down with hydrogen flow. In order to suppress anti-phase boundaries (APBs) on substrate surface 135, a pre-exposure to As for about 1 to 2 minutes is performed. This step helps ensure uniform coverage of the trench surface with an As-As monolayer. This pre-exposure is achieved by flowing AsH3 gas through the reactor at a temperature of approximately 460°C. Then, the precursor triethylgallium (TEG) or trimethylgallium (TMG) is introduced into the chamber together with AsH3 gas at a higher growth temperature, e.g., approximately 500°C to 550°C promote the initial GaAs nucleation process on the As pre-layer surface. This high-temperature process helps ensure that the Ga atoms are sufficiently mobile to avoid GaAs cluster formation. A slow growth rate of about 2 to 4 run per minute with V/III ratio of about 50 may be used to obtain this initial GaAs layer, with a thickness in the range of about 50 to 100 nm. [0032] Then a layer of n-type GaAs having a thickness of 1 to 2 μm is grown at a constant growth temperature of approximately 68O0C and a V/III ratio of approximately 80 to obtain defect-free GaAs material inside the trench 120. During this step, the GaAs epitaxial layer thickness t2 may be greater than the dielectric mask thickness tj. The GaAs material may have a mushroom-type cross-sectional profile with lateral over growth over the dielectric layer 110; the top portion of the GaAs material may coalesce with GaAs formed in neighboring trenches (not shown) to form an epitaxial layer. The width W2 of the crystalline material 140 extending over a top surface 160 of the dielectric layer 110 may be greater than the width w of the trench 120. In this case, a small void may be formed between the laterally grown GaAs layer and the top surface 160 of the dielectric layer 110. The overall layer thickness t2 of the crystalline material 140 may be monitored by using pre-calibrated growth rates and in situ monitoring equipment, according to methods routinely employed in the art.
[0033] Most, if not all, dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the trench 120 in the dielectric material 110 at or below the predetermined vertical distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the trench 140. Accordingly, the upper portion of the crystalline material is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be substantially eliminated from the upper portion of the crystalline material. [0034] The crystalline material 140 may be considered to have two portions: a lower portion for trapping dislocation defects and an upper portion which either (a) incorporates the laser or LED epitaxial layers or (b) serves as a template for the subsequent epitaxial growth of the laser or LED epitaxial layers. The height h of the crystalline material thus has two components: the height htrapping of the lower portion (where defects are concentrated) and the height hupper of the upper portion (which is largely free of defects). The height htrapPing of the trapping portion may be selected from a range of about 1A w < hipping ≤ 2w, to ensure effective trapping of dislocation defects. The actual value of hipping required may depend upon the type of dislocation defects encountered, which may depend on the materials used, and also upon the orientation of the trench sidewalls. In some instances, the height hipping can be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the upper portion, so that deleterious effects of dislocation defects upon device performance are not experienced. For example, htrapping may be, e.g., 10 - 100 nm greater than required for effective trapping of defects. For the upper portion, the height hupper may be selected from the range of approximately 1A w < hupper ≤ 10w. [0035] It has been observed experimentally that dislocations in a mismatched cubic semiconductor grown on a Si (100) surface in the near vicinity (e.g., within approximately 500 nm or less) of a vertical dielectric sidewall surface bend toward that surface at approximately 30 degrees through 60 degrees. For example, the dislocations may bend toward that surface at approximately a 45-degree angle to that surface. Based on this relationship, the predetermined distance H necessary to trap defects is, typically, approximately equal to a width between 1A w and 2 w, where w is the width of the trench. This range is based on the range of intersection angles of approximately 30 degrees through 60 degrees; then, tan(30°)w < H < tan(60°)w, which roughly corresponds to 1A w < H < 2w.
[0036] Referring to Figure 2, a planarization step such as, e.g., chemical-mechanical polishing (CMP) may be used to planarize a top surface 170 of the crystalline material 140 within a roughness level preferably no greater than 20 nm, to allow the formation of good quality films thereon. In an embodiment, the thickness t3 of the portion of the crystalline material 140 disposed within the trench 120 is 1 μm and the thickness t4 of the portion of the crystalline material 140 disposed above the top surface 160 of the dielectric layer 110 is about 0.5 μm. In another embodiment, a planarization step such as, e.g., CMP is used to planarize a top surface of the crystalline material 140 within a roughness level preferably no greater than 20 nm, to ensure that the top surface of the crystalline material 140 is substantially co-planar with the top surface 160 of the dielectric material 110. [0037] Referring to Figure 3, a laser epitaxial structure 300 may be formed over the crystalline material 140. For example, the laser epitaxial structure 300 may be a GaAs-based laser structure including layers of GaAs/InGaAs/ AlGaAs, formed according to methods known in the art. The laser structure, described from the bottom up, may include, e.g., a -1.5 μm thick n-GaAs base layer 310, a -0.30 μm W-Al0-04GaAs graded lower cladding layer 312, a ~1.3 μm thick «- Al04GaAs cladding layer 314, an undoped -0.3 μm Al04-C2GaAs graded lower confining layer 316, an undoped -7 nm In02GaAs single quantum well layer 318, an undoped -0.3 μm Al02-O 4GaAs graded upper confining layer 320, a -1.3 μm thick p-Alo.4GaAs cladding layer 322, a -0.30 μm thick p-Alo.4-oGaAs graded upper cladding 324, and a -0.1 μm thick p+- GaAs contact layer 326. These layers may be formed by epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, MOCVD, APCVD, LPCVD, UHVCVD, MBE, or ALD. A growth temperature may be approximately 550 - 680 °C for the GaAs layer and approximately 650 - 8000C for the AlGaAs layers. In an embodiment, GaAs- based laser epitaxial structures are grown on offcut Si substrates oriented about 2° off (100) towards the <011 > direction in an AIXTRON 2600 MOCVD reactor at about 75 torr. TMG and trimethylaluminum (TMA) may be used as group-Ill sources, and arsine (AsH3) may be used as the group-V source. Silane (SiH4) and carbon tetrachloride (CCl4) may be used as n- and p-dopant sources, respectively. Hydrogen may be used as a carrier gas. [0038] Referring to Figure 4, instead of a laser epitaxial structure 300, an LED epitaxial structure 300' may be formed over the crystalline material 140. The surface-emitting epitaxial LED structure includes a base layer 310', a lower cladding layer 314', an undoped lower confining layer 316', an undoped single- or multiple-quantum- well active region 318', an undoped upper confining layer 320', an upper cladding layer 322', and a heavily doped p-type contact layer 326'. Metal contacts may be formed over the p-type contact layer 326' using the process described below with reference to Figure 5. It is often desired that light emission for LEDs be through the top surface. For this reason, a transparent top-contact material such as indium tin oxide (ITO) may be used. Alternatively, a non-transparent contact may be used, preferably not covering an entire top surface of the LED epitaxial structure. [0039] Referring to Figure 5, an RIE etch step may be performed to remove a portion of the laser epitaxial structure 300 that may extend laterally over the dielectric layer 110. This etch may remove defects that may arise from coalescence between neighboring selective epitaxial regions. Referring also to Figure 6, at the same time, this etch may define the front and back facets 600, 610 of an edge-emission laser structure 620. The etch may be performed with, for example, argon and chlorine plasmas. A metal layer is deposited over the dielectric layer, for example via evaporation, and patterned to define a top contact 520. The metal layer may have a thickness of, e.g., approximately 150 run. In an embodiment, the top contact 520 is a p-type contact and includes or consists essentially of Ti/Pt/Au. Following contact deposition, an anneal of approximately 350-450°C for approximately 10 minutes may be performed to ensure good electrical contact with the laser epitaxial structure 300. A second metal contact 530, e.g., a bottom metal contact, is defined adjacent the substrate 100. A backside of the substrate 100 may be thinned before the second metal contact is defined. In an embodiment, the second metal contact is formed on the backside of the substrate. In an alternative embodiment, the second metal contact contacts the topside of the substrate through a window defined in the overlying dielectric layer(s) 110 (see Figures 7a-7d ). The second metal contact may have a thickness of, e.g., approximately 500 nm. In some embodiments, the second metal contact is an n-type contact and includes or consists essentially of Al formed by evaporation on an n-type Si substrate. A standard laser facet coating process is used, according to methods known in the art, to obtain reflectivity of approximately 3% and approximately 95% for front and back facets, respectively. The resulting structure is a completed laser device that can be integrated into circuits formed on a semiconductor die. The laser device is a light-emitting device 620 including laser epitaxial structure 300. [0040] A GaAs-based laser structure growth and device preparation process are illustrated in Figures 1-6. The figures are not to scale, and a thick laser structure is illustrated to demonstrate the general process sequence. This laser structure includes a single InGaAs quantum well centered in a waveguide, graded-index separate confinement heterostructure (GRJNSCH) with 1.3-μm-thick Al04Ga06As cladding layers. The illustrated device is designed for operation at a wavelength of 980 nm. However, the process may be utilized to form other structures based on ART technology. For instance, for small dimensional devices such as nano-scale light emitters, the full epitaxial structure for the laser may be confined inside a single trench. In this case, CMP process and laser mesa contact process may be eliminated or simplified. Also, as discussed below, this method may be used to fabricate broad-area light emitters or emitter arrays, with large device dimensions and covering a plurality of trenches. [0041] Referring to Figures 7a-7d, the process described above with respect to Figures 1-6 may be used to form light-emitting structures having various configurations. Referring to Figure 7a, laser or LED epitaxial structure 300 or 300' may be formed in trench 120. Dislocation defects 150 may be trapped within the lower trench region 710. In an embodiment, a planarization process, for example, CMP, of the crystalline material 140 is not necessary, as growth of the crystalline material 140 is halted before the crystalline material completely fills the trench 120. In this way, sufficient room (e.g., approximately 1-3 μm) is provided in an upper portion of the trench 120 for the formation of the laser or LED epitaxial structure. In some embodiments, the crystalline material 140 defines a portion of the laser or LED epitaxial structure 300 or 300'. In other embodiments, the crystalline material 140 provides a template for the formation of the laser or LED epitaxial structure 300 or 300' in the trench 120. Top contact 520 is formed over the laser or LED epitaxial structure 300 or 300'. The second metal contact 530 contacts the topside of the substrate 100 through a window defined in the overlying dielectric layer(s) 110 (see Figures 7a-7d ). [0042] Referring to Figure 7b, as discussed in detail with respect to Figures 1-6, laser or LED epitaxial structure 300 or 300' may be formed on a top portion of the crystalline material 140 extending above the top surface 160 of the dielectric layer 110. [0043] Referring to Figure 7c, a plurality of trenches, i.e., two or more adjacent trenches may each include crystalline material 140 and a laser or LED epitaxial structure 300 or 300' disposed over the crystalline material 140 in the trench, as discussed with reference to Figure 7a. The distance d between two adjacent trenches may be at least equal to the average width of the adjacent trenches. A patterned metal or a transparent top contact 520 may be formed over and in contact with each of the laser or LED epitaxial structures 300 or 300', thereby providing a broad-area laser or LED. [0044] Referring to Figure 7d, two or more adjacent trenches may each include crystalline semiconductor 140 extending above the top surface 160 of the dielectric layer 110, as described above with reference to Figures 1-6 and Figure 7b. Lateral growth of the crystalline material 140 between the adjacent trenches 120 results in the coalescence of the top portions of the crystalline material into a single epitaxial film 700 of crystalline material 140. A planarization process, for example, CMP, may be performed on a top surface of the epitaxial film 700. Thereafter, a broad area laser or LED epitaxial structure 300 or 300', containing an optical active region, is formed over the epitaxial film 700. [0045] Referring to Figures 8a-8c, the process described above with reference to Figures 1- 6 may be combined with selective etching to form a V-groove laser diode. Referring to Figure 8a, in an exemplary embodiment, crystalline semiconductor material 140 is formed in a trench 120, and extends beyond the top surface 160 of dielectric 110. In an embodiment, an electrically insulating diode (EID) (not shown) is added. The EID may be formed from two layers of semiconductor material, and the crystalline semiconductor material 140 may be the first of those layers. The EID may be positioned between the crystalline material 140 formed in trench 120 and the light-emitting device 300 or 300'. An n-contact 530 may be used to make an electrical connection to the crystalline material 140 above the trench 120, for example, near the top surface 160 of the dielectric layer 120; an EID may preferably then be used to prevent leakage current from the substrate 100 into the trench 120. The crystalline material 140 is preferably planarized by, for example, CMP to within a roughness level preferably no greater than 20 nm. [0046] Referring to Figure 8b, the top surface of the crystalline semiconductor material 140 may then be modified with a selective etching process to create a V groove 800 in the surface of the crystalline material 140. In particular, the V groove may be formed as follows. An upper dielectric layer 810 including a dielectric material, e.g., Si3N4, may be formed on the crystalline semiconductor material 140 using a deposition process, e.g., PECVD, and patterned by photolithography and etching. The pattern in the upper dielectric layer 910 may include stripes oriented along the trench 120 and may have dimensions similar to those of the lower dielectric layer 110. In an embodiment, the stripes defined by the upper dielectric layer have dimensions greater than those of the lower dielectric layer 110, so that the upper dielectric layer 140 covers some trenches 120 but not other trenches 120. The pattern in the upper dielectric layer may be defined by a wet etch, e.g., a buffer oxide etchant. [0047] An appropriate wet etch, e.g., H2SO4:H2O2:H2O = 1 :8:4, may then be used to create a V-groove in the crystalline semiconductor material 140 exposed by the openings formed in the upper dielectric layer. The appropriate wet etch etches the crystalline semiconductor material 140 selectively with respect to the upper dielectric layer and dielectric layer 110. Moreover, the wet-etch composition is selected to define facets in the crystalline semiconductor material 140 to form the V-groove. Subsequently, the patterned upper dielectric layer may be removed. [0048] Referring to Figure 8c, a diode structure 300 is grown on top of the V-shaped layer to create a V-groove laser diode. This design may be applied to the fabrication of single or trenched array laser diodes.
[0049] Referring to Figures 9a-9b, the process described above with reference to Figures 1- 6 may be combined with the formation of cascade superlattice structures to create cascade lasers. Referring to Figure 9a, a multiple stage cascade structure 900 may be formed with a preferred structure design and controlled layer thicknesses, and may include, for example, InP/GalnAs/AlInAs, GaAs/AlGaAs or Si/SiGe/Si superlattice layers. The cascade structure 900 may be formed within trench 120 above dislocation defects 150. Each layer forming the cascade structure 900 may range in thickness from, for example, 1 nm to 5 ran, and may be formed with an epitaxial process, for example, MBE or MOCVD. The layers of the superlattice 900 may be formed in groups of, for example, 5-10 layers, where the composition and number of the layers within a group defines the output characteristics of the laser. Furthermore, the group of layers may be repeated, for example, 10-30 times, to increase the output power of the laser. The number of layers within a group and number of groups may be repeated as many times as the height of the crystalline semiconductor material 140 allows. Growth of the cascade structure 900 may terminated before coalesced growth occurs, to produce a near- or middle-infrared laser with peak emission at a wavelength between 3 μm and 17 μm. In some embodiments, the crystalline material 140 itself provides a template for the formation of the cascade superlattice structure 900 above the trench 120.
[0050] In the illustrated embodiment, the top contact 520 is formed over the cascade superlattice structure 900. The second metal contact 530 contacts the bottom side of the thinned substrate 100. [0051] Referring to Figure 9b, multiple-wavelength cascade lasers may be formed on a surface that is preferably planarized, e.g., by CMP to within a roughness level preferably no greater than 20 nm. Different wavelength emissions may be accomplished by multiple sectional etching processes. The emission wavelength is tuned over a wide range by applying a voltage using multiple-section contacts. In an embodiment, one or all of the multiple wavelength sections of the cascade superlattice structure 900 has its own n-contact 530. [0052] Referring to Figure 10, the process described above with respect to Figures 1-7 may be modified to create photonic crystals. The dielectric layer 110 may be first deposited, and then etched to produce trenches and shapes other than trenches, e.g., circular holes. These shapes correspond to features in crystalline material 140 that may be formed to direct emissions from a laser. A photonic mask layer (not shown) may be created to define these shapes and the dielectric layer 110 is selectively removed, e.g., etched, to form the desired shapes. After the dielectric layer 110 has been patterned, openings in the patterned dielectric layer 110 are filled with the crystalline semiconductor material 140. In an embodiment, an EID as described above is formed. The dielectric layer may then be wholly or partially removed to form an air-spaced photonic crystal array, i.e., having features separated by air. In an embodiment, part of the dielectric layer is left in place to change the refraction index of the boundary between the crystalline semiconductor material 140 and the dielectric layer 110 in the photonic crystal array. In various embodiments, this crystal array is used with a laser 1010 as an optical DBR reflector 1020, beam divider 1030, or waveguide 1040, as illustrated in Figure 10. [0053] Referring to Figures 1 la-b, the method described in Figures 1-7 may be modified to form a number of light-emitting devices arranged in a one-dimensional array. A number of trenches of arbitrary length may be placed in close proximity to each other, and each trench may contain a light-emitting device, such as a laser diode or a light-emitting diode. Referring to Figure 1 Ia, a plan view of a one-dimensional array of light-emitting diodes is shown. The p- contact 520 may cover only part of the top surface of the diode structure 300' to permit the diode to emit light perpendicular to the page from the portion of the top surface of the diode structure 300' not covered by p-contact 520. Each diode in the array may be electrically connected by forming a layer of metal 1110 at one end of the trenches 120 that is electrically connected to each diode's p-contact 520. Neighboring diodes may be electrically isolated with a dielectric isolator structure 1130. Referring to Figure 1 Ib, a plan view of a one-dimensional array of laser diodes is shown. The p-contact 520 may cover the entire top surface of the laser structure 300, and the laser may output light in a direction 1120, within the plane of the page. Each laser in the one-dimensional array may be electrically connected by forming a layer of metal 1110 at one end of the trenches 120 that is electrically connected to each laser's p-contact 520. Neighboring lasers may be electrically isolated with a dielectric isolator structure 1130. [0054] Each light-emitting device in a one-dimensional array may be formed inside its own trench 120, as shown in Figure 7a. In this case, each trench-defined device may be electrically isolated from a neighboring device or devices by portions of the dielectric layer 110. [0055] In another embodiment, the light-emitting devices in the one-dimensional array are formed above the trench 120, as shown in Figure 7b, in the single epitaxial layer resulting from the crystalline semiconductor material 140 coalescing above and between neighboring trenches. In this case, an etch step may be performed to electrically isolate the devices. This process may include the steps of (i) forming a masking layer over the light-emitting devices, (ii) removing material from the masking layer to expose portions of the crystalline semiconductor material 140 where electrical continuity is to be broken, for example, the midpoint between two trench- based light-emitting devices, and (iii) removing the exposed crystalline semiconductor material 140 with an etching process. The gaps formed when the exposed crystalline semiconductor material 140 is removed may be filled with, for example, a dielectric material 1130.
[0056] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. [0057] What is claimed is:

Claims

1. A structure comprising: a trench defined in a dielectric layer disposed over a substrate comprising a first crystalline semiconductor material; a second crystalline semiconductor material disposed in the trench, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material; and a light-emitting device disposed over and in contact with at least a portion of the second crystalline semiconductor material.
2. The structure of claim 1 , wherein the trench has a height h and a width w, and a ratio of h/w ≥l.
3. The structure of claim 1, wherein the light-emitting device is a laser or a light-emitting diode.
4. The structure of claim 3, wherein the light-emitting device is a laser and comprises at least one of a GaAs, an AlAs, or an AlGaAs layer.
5. The structure of claim 3, wherein the light-emitting device is a laser and comprises at least one of InP, GaP, AlP, InAs, AlAs, GaAs, InSb, AlSb, GaSb, InN, or their ternary or quaternary compounds.
6. The structure of claim 3, wherein the light-emitting device is a light-emitting diode and comprises a GaAs, an AlAs, or an AlGaAs layer.
7. The structure of claim 3, wherein light-emitting device is a light-emitting diode and comprises InP, InAs, AlAs, GaAs, AlSb, GaSb, or their ternary or quaternary compounds.
8. The structure of claim 1, wherein the first crystalline semiconductor material comprises at least one of a group IV element or compound, a II-VI compound, or a IH-V compound.
9. The structure of claim 1, wherein the second crystalline material comprises at least one of a II-VI compound or a HI-V compound.
10. The structure of claim 1 , further comprising a top contact disposed over at least a portion of the light-emitting device and a second contact disposed over and in contact with a portion of the substrate.
1 1. The structure of claim 1 , wherein a plurality of trenches are formed in the dielectric layer, the second crystalline semiconductor material being disposed in each trench.
12. The structure of claim 11 , wherein a distance between two adjacent trenches is at least equal to an average width of the adjacent trenches.
13. The structure of claim 1 , wherein the light-emitting device comprises a laser epitaxial structure disposed in the trench.
14. The structure of claim 1, wherein the light-emitting device comprises an LED epitaxial structure disposed in the trench.
15. The structure of claim 1, wherein the second crystalline semiconductor material extends above the dielectric layer, and the light-emitting device comprises a laser epitaxial structure disposed above a top surface of the dielectric layer.
16. The structure of claim 1, wherein the second crystalline semiconductor material extends above the dielectric layer, and the light-emitting device comprises an LED epitaxial structure disposed above a top surface of the dielectric layer.
17. A method for forming a structure, the method comprising: forming a trench having a dielectric sidewall and a bottom surface adjacent a substrate comprising a first crystalline semiconductor material; filling at least a portion of the trench with a second crystalline semiconductor material lattice-mismatched to the first crystalline semiconductor material; and defining a light-emitting device over and in contact with at least a portion of the second crystalline semiconductor material.
18. The method of claim 17, wherein the trench has a height h and a width w, and a ratio of h/w ≥l.
19. The method of claim 17, wherein the light-emitting device is selected from the group consisting of a laser and a light-emitting diode.
20. The method of claim 17, wherein the trench is filled by selective epitaxy.
21. The method of claim 17, further comprising the step of defining additional trenches, wherein the step of filling comprises forming a coalesced layer of second crystalline semiconductor material above the trenches, and the step of defining a light-emitting device comprises defining a light-emitting device over the trenches.
22. The method of claim 17, wherein an active region of the light-emitting device is formed within the trench.
23. A structure comprising: a dielectric sidewall disposed proximate a top surface of a substrate comprising a first crystalline material; a second crystalline semiconductor material disposed proximate the dielectric sidewall, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material; and a cascade superlattice disposed over and in contact with at least a portion of the second crystalline semiconductor material.
24. A method for forming a trench-based light-emitting device, the method comprising: forming a trench adjacent a substrate, the trench (i) having a non-crystalline sidewall, (ii) having a width w, (iii) having a height h above a bottom surface of the trench, and (iv) having a ratio of h/w >1, the bottom surface of the trench including an exposed surface of the substrate. epitaxially growing a crystalline semiconductor material in at least a portion of the trench, the crystalline semiconductor material being lattice-mismatched to the substrate; and forming a light-emitting device over the crystalline semiconductor material, an active region of the light-emitting device being at least partially disposed within the trench.
25. A method for forming a light-emitting device using lattice-mismatched materials and planarization, the method comprising: forming an opening having a non-crystalline sidewall disposed above a surface of a substrate, the substrate comprising a first crystalline semiconductor material; forming a second crystalline semiconductor material in the opening, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material; planarizing a surface of the second crystalline semiconductor material; and forming a light-emitting device at least partially above the planarized surface of the second crystalline semiconductor material.
PCT/US2007/022392 2006-10-19 2007-10-19 Light-emitter-based devices with lattice-mismatched semiconductor structures WO2008051503A2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2343742A3 (en) * 2010-01-08 2014-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
EP2849208A1 (en) * 2013-09-13 2015-03-18 Commissariat A L'energie Atomique Et Aux Energies Alternatives Optimised method for manufacturing patterns of III-V semiconductor material on a semiconductor substrate
EP2869331A1 (en) * 2013-10-29 2015-05-06 IMEC vzw Episubstrates for selective area growth of group iii-v material and a method for fabricating a group iii-v material on a silicon substrate
US10014374B2 (en) 2013-12-18 2018-07-03 Intel Corporation Planar heterogeneous device

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006125040A2 (en) * 2005-05-17 2006-11-23 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
WO2007014294A2 (en) * 2005-07-26 2007-02-01 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US20090311483A1 (en) * 2006-04-04 2009-12-17 Technion Research & Development Foundation Ltd. Articles with Two Crystalline Materials and Method of Making Same
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8237151B2 (en) * 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR101374090B1 (en) * 2007-07-26 2014-03-17 아리조나 보드 오브 리젠츠 퍼 앤 온 비하프 오브 아리조나 스테이트 유니버시티 Epitaxial methods and templates grown by the methods
DE112008002387B4 (en) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a multijunction solar cell, method of forming a photonic device, photovoltaic multijunction cell and photovoltaic multijunction cell device,
US20090085055A1 (en) * 2007-09-27 2009-04-02 Hui Peng Method for Growing an Epitaxial Layer
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
WO2010110888A1 (en) * 2009-03-23 2010-09-30 The Board Of Trustees Of The Leland Stanford Junior University Quantum confinement solar cell fabriacated by atomic layer deposition
CN102379046B (en) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 Devices formed from a non-polar plane of a crystalline material and method of making the same
US20110062492A1 (en) * 2009-09-15 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology
CN102714144A (en) * 2010-01-15 2012-10-03 住友化学株式会社 Semiconductor substrate, electronic device, and method for producing semiconductor substrate
US8242510B2 (en) * 2010-01-28 2012-08-14 Intersil Americas Inc. Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
JP5757195B2 (en) * 2011-08-23 2015-07-29 セイコーエプソン株式会社 Semiconductor device, electro-optical device, power conversion device, and electronic apparatus
KR101805634B1 (en) * 2011-11-15 2017-12-08 삼성전자 주식회사 Semiconductor device comprising III-V group barrier and method of manufacturing the same
US9476143B2 (en) * 2012-02-15 2016-10-25 Imec Methods using mask structures for substantially defect-free epitaxial growth
WO2013158210A2 (en) 2012-02-17 2013-10-24 Yale University Heterogeneous material integration through guided lateral growth
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US9159677B2 (en) * 2012-08-21 2015-10-13 Micron Technology, Inc. Methods of forming semiconductor device structures
US8841188B2 (en) * 2012-09-06 2014-09-23 International Business Machines Corporation Bulk finFET with controlled fin height and high-K liner
US8765563B2 (en) 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
FR2997558B1 (en) 2012-10-26 2015-12-18 Aledia OPTOELECTRIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
US9859429B2 (en) 2013-01-14 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of fabricating same
US9106048B2 (en) * 2013-02-11 2015-08-11 Oracle International Corporation Waveguide-coupled vertical cavity laser
WO2014144698A2 (en) * 2013-03-15 2014-09-18 Yale University Large-area, laterally-grown epitaxial semiconductor layers
US8753953B1 (en) * 2013-03-15 2014-06-17 International Business Machines Corporation Self aligned capacitor fabrication
US9064699B2 (en) 2013-09-30 2015-06-23 Samsung Electronics Co., Ltd. Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
KR20160089519A (en) * 2013-12-20 2016-07-27 후아웨이 테크놀러지 컴퍼니 리미티드 Semiconductor device and method for manufacturing same
US9177967B2 (en) 2013-12-24 2015-11-03 Intel Corporation Heterogeneous semiconductor material integration techniques
CN106062963B (en) 2014-03-28 2019-08-13 英特尔公司 Strain compensation in transistor
CN106233471A (en) 2014-04-16 2016-12-14 耶鲁大学 The semi-polarity GaN layer of the nitrogen polarity in Sapphire Substrate and device
WO2015160909A1 (en) 2014-04-16 2015-10-22 Yale University Method of obtaining planar semipolar gallium nitride surfaces
US9391140B2 (en) * 2014-06-20 2016-07-12 Globalfoundries Inc. Raised fin structures and methods of fabrication
US9240447B1 (en) 2014-08-21 2016-01-19 International Business Machines Corporation finFETs containing improved strain benefit and self aligned trench isolation structures
JP2017533574A (en) * 2014-09-18 2017-11-09 インテル・コーポレーション Wurtzite heteroepitaxial structure with inclined sidewall cut surface for defect propagation control in silicon CMOS compatible semiconductor devices
KR102203497B1 (en) 2014-09-25 2021-01-15 인텔 코포레이션 Iii-n epitaxial device structures on free standing silicon mesas
EP3221886A4 (en) 2014-11-18 2018-07-11 Intel Corporation Cmos circuits using n-channel and p-channel gallium nitride transistors
US10056456B2 (en) 2014-12-18 2018-08-21 Intel Corporation N-channel gallium nitride transistors
US9401583B1 (en) * 2015-03-30 2016-07-26 International Business Machines Corporation Laser structure on silicon using aspect ratio trapping growth
CN107949914B (en) 2015-05-19 2022-01-18 英特尔公司 Semiconductor device with raised doped crystal structure
KR102349040B1 (en) 2015-06-26 2022-01-10 인텔 코포레이션 Hetero-epitaxial structures with high temperature stable substrate interface material
US9917414B2 (en) * 2015-07-15 2018-03-13 International Business Machines Corporation Monolithic nanophotonic device on a semiconductor substrate
WO2017023535A1 (en) 2015-07-31 2017-02-09 Sxaymiq Technologies Llc Light emitting diode with displaced p-type doping
US9870940B2 (en) 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
US9570297B1 (en) * 2015-12-09 2017-02-14 International Business Machines Corporation Elimination of defects in long aspect ratio trapping trench structures
WO2017111869A1 (en) 2015-12-24 2017-06-29 Intel Corporation Transition metal dichalcogenides (tmdcs) over iii-nitride heteroepitaxial layers
US9437427B1 (en) * 2015-12-30 2016-09-06 International Business Machines Corporation Controlled confined lateral III-V epitaxy
FR3053538B1 (en) * 2016-06-30 2018-08-17 Commissariat Energie Atomique LASER SOURCE WITH SEMICONDUCTOR
WO2018031876A1 (en) 2016-08-12 2018-02-15 Yale University Stacking fault-free semipolar and nonpolar gan grown on foreign substrates by eliminating the nitrogen polar facets during the growth
WO2018063372A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Supperlatice channel included in a trench
EP3340403B1 (en) * 2016-12-23 2023-06-28 IMEC vzw Improvements in or relating to laser devices
US10163628B1 (en) * 2017-05-31 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Lattice-mismatched semiconductor substrates with defect reduction
WO2019066953A1 (en) 2017-09-29 2019-04-04 Intel Corporation Group iii-nitride (iii-n) devices with reduced contact resistance and their methods of fabrication
US10546928B2 (en) * 2017-12-07 2020-01-28 International Business Machines Corporation Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques
FR3075461B1 (en) 2017-12-20 2020-02-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING A HETEROSTRUCTURE COMPRISING ELEMENTARY PHOTONIC STRUCTURES OF III-V MATERIAL ON THE SURFACE OF A SILICON-BASED SUBSTRATE
US20190198709A1 (en) 2017-12-22 2019-06-27 Lumileds Llc Iii-nitride multi-color on wafer micro-led enabled by tunnel junctions
EP3506000B1 (en) * 2017-12-29 2020-10-07 IMEC vzw Iii-v semiconductor waveguide nanoridge structure
US10593672B2 (en) 2018-01-08 2020-03-17 International Business Machines Corporation Method and structure of forming strained channels for CMOS device fabrication
DE102018106967B3 (en) * 2018-03-23 2019-05-23 Infineon Technologies Ag SILICON CARBIDE SEMICONDUCTOR ELEMENT and semiconductor diode
FR3080487B1 (en) * 2018-04-20 2020-06-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE WITH A DIODES ARRAY
EP3565068B1 (en) * 2018-04-30 2021-02-24 FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V. Thermally tunable laser and method for fabricating such laser
CN110649132B (en) * 2018-06-26 2022-09-13 晶元光电股份有限公司 Semiconductor substrate, semiconductor element and manufacturing method of semiconductor element
US10879420B2 (en) * 2018-07-09 2020-12-29 University Of Iowa Research Foundation Cascaded superlattice LED system
EP3621101B1 (en) 2018-09-04 2022-11-23 IMEC vzw Integrated circuit including at least one nano-ridge transistor
US11145507B2 (en) * 2019-12-16 2021-10-12 Wafer Works Corporation Method of forming gallium nitride film over SOI substrate
US11211527B2 (en) 2019-12-19 2021-12-28 Lumileds Llc Light emitting diode (LED) devices with high density textures
US11264530B2 (en) * 2019-12-19 2022-03-01 Lumileds Llc Light emitting diode (LED) devices with nucleation layer
US11437781B2 (en) * 2020-02-27 2022-09-06 Qualcomm Incorporated Distributed feedback (DFB) laser on silicon and integrated device comprising a DFB laser on silicon
CN116491036A (en) * 2020-11-06 2023-07-25 三菱电机株式会社 Optical semiconductor device and method for manufacturing the same
US11536902B1 (en) * 2021-07-07 2022-12-27 Globalfoundries U.S. Inc. Edge couplers with metamaterial rib features

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0262090A (en) * 1988-08-29 1990-03-01 Matsushita Electric Ind Co Ltd Manufacture of optical semiconductor device
US6015979A (en) * 1997-08-29 2000-01-18 Kabushiki Kaisha Toshiba Nitride-based semiconductor element and method for manufacturing the same
US6100106A (en) * 1997-11-17 2000-08-08 Nec Corporation Fabrication of nitride semiconductor light-emitting device
JP2000286449A (en) * 1999-03-31 2000-10-13 Toyoda Gosei Co Ltd Iii nitride compound semiconductor device and its manufacture
US6342404B1 (en) * 1999-03-31 2002-01-29 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing
US20030087462A1 (en) * 2001-11-02 2003-05-08 Norikatsu Koide Semiconductor light emitting device and method for producing the same
JP2004200375A (en) * 2002-12-18 2004-07-15 Matsushita Electric Ind Co Ltd Semiconductor laser device and method of manufacturing the same
EP1551063A1 (en) * 2002-06-04 2005-07-06 Nitride Semiconductors Co., Ltd. Gallium nitride compound semiconductor device and manufacturing method
WO2006125040A2 (en) * 2005-05-17 2006-11-23 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication

Family Cites Families (396)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2426529C3 (en) 1974-05-31 1980-08-28 Deutsche Itt Industries Gmbh, 7800 Freiburg Planar diffusion process for manufacturing a transistor in a monolithically integrated I2 L circuit
US4307510A (en) 1980-03-12 1981-12-29 The United States Of America As Represented By The Administrator Of The National Aeronautics & Space Administration Computer circuit card puller
WO1981002948A1 (en) * 1980-04-10 1981-10-15 Massachusetts Inst Technology Methods of producing sheets of crystalline material and devices made therefrom
US4322253A (en) * 1980-04-30 1982-03-30 Rca Corporation Method of making selective crystalline silicon regions containing entrapped hydrogen by laser treatment
US4370510A (en) * 1980-09-26 1983-01-25 California Institute Of Technology Gallium arsenide single crystal solar cell structure and method of making
US4482422A (en) * 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
US4545109A (en) 1983-01-21 1985-10-08 Rca Corporation Method of making a gallium arsenide field effect transistor
US4651179A (en) * 1983-01-21 1987-03-17 Rca Corporation Low resistance gallium arsenide field effect transistor
US5091333A (en) 1983-09-12 1992-02-25 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US4557794A (en) * 1984-05-07 1985-12-10 Rca Corporation Method for forming a void-free monocrystalline epitaxial layer on a mask
US4860081A (en) 1984-06-28 1989-08-22 Gte Laboratories Incorporated Semiconductor integrated circuit structure with insulative partitions
US4551394A (en) 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs
EP0214610B1 (en) 1985-09-03 1990-12-05 Daido Tokushuko Kabushiki Kaisha Epitaxial gallium arsenide semiconductor wafer and method of producing the same
US4774205A (en) 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
JPS6381855A (en) 1986-09-25 1988-04-12 Mitsubishi Electric Corp Manufacture of hetero junction bipolar transistor
US5236546A (en) 1987-01-26 1993-08-17 Canon Kabushiki Kaisha Process for producing crystal article
US5269876A (en) 1987-01-26 1993-12-14 Canon Kabushiki Kaisha Process for producing crystal article
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
US5166767A (en) 1987-04-14 1992-11-24 National Semiconductor Corporation Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer
US4876210A (en) 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
US4826784A (en) * 1987-11-13 1989-05-02 Kopin Corporation Selective OMCVD growth of compound semiconductor materials on silicon substrates
US5272105A (en) 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
US5079616A (en) * 1988-02-11 1992-01-07 Gte Laboratories Incorporated Semiconductor structure
GB2215514A (en) 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5156995A (en) 1988-04-01 1992-10-20 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers
US5032893A (en) * 1988-04-01 1991-07-16 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers
EP0352472A3 (en) 1988-07-25 1991-02-06 Texas Instruments Incorporated Heteroepitaxy of lattice-mismatched semiconductor materials
US5238869A (en) 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
US5061644A (en) 1988-12-22 1991-10-29 Honeywell Inc. Method for fabricating self-aligned semiconductor devices
EP0380815B1 (en) 1989-01-31 1994-05-25 Agfa-Gevaert N.V. Integration of GaAs on Si substrate
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
US4948456A (en) 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
US5256594A (en) 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
US5098850A (en) * 1989-06-16 1992-03-24 Canon Kabushiki Kaisha Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them
US5170404A (en) * 1989-09-04 1992-12-08 Hitachi, Ltd. Semiconductor laser device suitable for optical communications systems drive
US5093699A (en) * 1990-03-12 1992-03-03 Texas A & M University System Gate adjusted resonant tunnel diode device and method of manufacture
US5164359A (en) 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
US5105247A (en) 1990-08-03 1992-04-14 Cavanaugh Marion E Quantum field effect device with source extension region formed under a gate and between the source and drain regions
JP3202223B2 (en) 1990-11-27 2001-08-27 日本電気株式会社 Method for manufacturing transistor
US5403751A (en) 1990-11-29 1995-04-04 Canon Kabushiki Kaisha Process for producing a thin silicon solar cell
US5223043A (en) 1991-02-11 1993-06-29 The United States Of America As Represented By The United States Department Of Energy Current-matched high-efficiency, multijunction monolithic solar cells
US5091767A (en) * 1991-03-18 1992-02-25 At&T Bell Laboratories Article comprising a lattice-mismatched semiconductor heterostructure
JPH04299569A (en) 1991-03-27 1992-10-22 Nec Corp Manufacture of sois and transistor and its manufacture
US5269852A (en) 1991-05-27 1993-12-14 Canon Kabushiki Kaisha Crystalline solar cell and method for producing the same
JP3058954B2 (en) 1991-09-24 2000-07-04 ローム株式会社 Method of manufacturing semiconductor device having growth layer on insulating layer
JP2773487B2 (en) 1991-10-15 1998-07-09 日本電気株式会社 Tunnel transistor
US5406574A (en) * 1991-10-23 1995-04-11 Kabushiki Kaisha Toshiba Semiconductor laser device
JPH05121317A (en) * 1991-10-24 1993-05-18 Rohm Co Ltd Method for forming soi structure
JP3286920B2 (en) 1992-07-10 2002-05-27 富士通株式会社 Method for manufacturing semiconductor device
EP0600276B1 (en) 1992-12-04 1998-08-05 Siemens Aktiengesellschaft Process for production of a laterally limited monocrystal area by selective epitaxy and its application for production of a bipolar transistor as well as well as a MOS-transistor
JP3319472B2 (en) 1992-12-07 2002-09-03 富士通株式会社 Semiconductor device and manufacturing method thereof
US5295150A (en) * 1992-12-11 1994-03-15 Eastman Kodak Company Distributed feedback-channeled substrate planar semiconductor laser
US5407491A (en) 1993-04-08 1995-04-18 University Of Houston Tandem solar cell with improved tunnel junction
EP0627799B1 (en) * 1993-06-04 1997-10-08 Sharp Kabushiki Kaisha Semiconductor light-emitting device with third cladding layer
JP3748905B2 (en) 1993-08-27 2006-02-22 三洋電機株式会社 Quantum effect device
US5792679A (en) 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5405453A (en) 1993-11-08 1995-04-11 Applied Solar Energy Corporation High efficiency multi-junction solar cell
US5489539A (en) 1994-01-10 1996-02-06 Hughes Aircraft Company Method of making quantum well structure with self-aligned gate
JPH0851109A (en) 1994-04-11 1996-02-20 Texas Instr Inc <Ti> Epitaxial silicon growth inside window of wafer patterned byoxide
US6011271A (en) 1994-04-28 2000-01-04 Fujitsu Limited Semiconductor device and method of fabricating the same
US5710436A (en) * 1994-09-27 1998-01-20 Kabushiki Kaisha Toshiba Quantum effect device
US5825240A (en) 1994-11-30 1998-10-20 Massachusetts Institute Of Technology Resonant-tunneling transmission line technology
JP3835225B2 (en) 1995-02-23 2006-10-18 日亜化学工業株式会社 Nitride semiconductor light emitting device
JPH08306700A (en) 1995-04-27 1996-11-22 Nec Corp Semiconductor device and its manufacture
US5528209A (en) 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
TW304310B (en) 1995-05-31 1997-05-01 Siemens Ag
US5621227A (en) 1995-07-18 1997-04-15 Discovery Semiconductors, Inc. Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy
JPH0930952A (en) 1995-07-21 1997-02-04 Shiseido Co Ltd Dermal preparation for external use
KR100473901B1 (en) 1995-12-15 2005-08-29 코닌클리케 필립스 일렉트로닉스 엔.브이. Semiconductor Field Effect Device Including SiGe Layer
TW314621B (en) 1995-12-20 1997-09-01 Toshiba Co Ltd
US5987590A (en) 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods
ZA974261B (en) 1996-05-17 1997-11-17 Canon Kk Photovoltaic device and process for the production thereof.
JP3719618B2 (en) 1996-06-17 2005-11-24 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
US6229153B1 (en) 1996-06-21 2001-05-08 Wisconsin Alumni Research Corporation High peak current density resonant tunneling diode
JP3260660B2 (en) * 1996-08-22 2002-02-25 株式会社東芝 Semiconductor device and manufacturing method thereof
JP3449516B2 (en) 1996-08-30 2003-09-22 株式会社リコー Semiconductor multilayer mirror, semiconductor multilayer antireflection film, surface emitting semiconductor laser, and light receiving element
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
US5825049A (en) 1996-10-09 1998-10-20 Sandia Corporation Resonant tunneling device with two-dimensional quantum well emitter and base layers
JPH10126010A (en) 1996-10-23 1998-05-15 Ricoh Co Ltd Manufacturing method of semiconductor laser device
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US5853497A (en) 1996-12-12 1998-12-29 Hughes Electronics Corporation High efficiency multi-junction solar cells
US6348096B1 (en) * 1997-03-13 2002-02-19 Nec Corporation Method for manufacturing group III-V compound semiconductors
JP3853905B2 (en) 1997-03-18 2006-12-06 株式会社東芝 Quantum effect device and device using BL tunnel element
EP0874405A3 (en) 1997-03-25 2004-09-15 Mitsubishi Cable Industries, Ltd. GaN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof
CN1131548C (en) 1997-04-04 2003-12-17 松下电器产业株式会社 Ohmic electrode forming method and semiconductor device
JP3184115B2 (en) 1997-04-11 2001-07-09 松下電器産業株式会社 Ohmic electrode formation method
JP3047852B2 (en) 1997-04-04 2000-06-05 松下電器産業株式会社 Semiconductor device
ATE550461T1 (en) 1997-04-11 2012-04-15 Nichia Corp GROWTH METHOD FOR A NITRIDE SEMICONDUCTOR
DE19715572A1 (en) * 1997-04-15 1998-10-22 Telefunken Microelectron Selective epitaxy of III-V nitride semiconductor layers
US5998781A (en) 1997-04-30 1999-12-07 Sandia Corporation Apparatus for millimeter-wave signal generation
US5903170A (en) 1997-06-03 1999-05-11 The Regents Of The University Of Michigan Digital logic design using negative differential resistance diodes and field-effect transistors
US5883549A (en) * 1997-06-20 1999-03-16 Hughes Electronics Corporation Bipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and method
KR100400808B1 (en) 1997-06-24 2003-10-08 매사츄세츠 인스티튜트 오브 테크놀러지 CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION
US5869845A (en) * 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
JP3930161B2 (en) 1997-08-29 2007-06-13 株式会社東芝 Nitride-based semiconductor device, light-emitting device, and manufacturing method thereof
US20010006249A1 (en) 1997-09-16 2001-07-05 Eugene A Fitzgerald Co-planar si and ge composite substrate and method of producing same
TW393785B (en) * 1997-09-19 2000-06-11 Siemens Ag Method to produce many semiconductor-bodies
FR2769924B1 (en) 1997-10-20 2000-03-10 Centre Nat Rech Scient PROCESS FOR MAKING AN EPITAXIAL LAYER OF GALLIUM NITRIDE, EPITAXIAL LAYER OF GALLIUM NITRIDE AND OPTOELECTRONIC COMPONENT PROVIDED WITH SUCH A LAYER
DE69842052D1 (en) 1997-10-30 2011-01-27 Sumitomo Electric Industries GAN CRYSTAL SUBSTRATE AND MANUFACTURING METHOD
JP3036495B2 (en) * 1997-11-07 2000-04-24 豊田合成株式会社 Method for manufacturing gallium nitride-based compound semiconductor
JP3468082B2 (en) 1998-02-26 2003-11-17 日亜化学工業株式会社 Nitride semiconductor device
US6150242A (en) 1998-03-25 2000-11-21 Texas Instruments Incorporated Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode
JPH11274467A (en) 1998-03-26 1999-10-08 Murata Mfg Co Ltd Photo-electronic integrated-circuit device
US6500257B1 (en) 1998-04-17 2002-12-31 Agilent Technologies, Inc. Epitaxial material grown laterally within a trench and method for producing same
JP3338778B2 (en) 1998-04-24 2002-10-28 日本電気株式会社 Nitride compound semiconductor laser device
JP4083866B2 (en) * 1998-04-28 2008-04-30 シャープ株式会社 Semiconductor laser element
US6248948B1 (en) * 1998-05-15 2001-06-19 Canon Kabushiki Kaisha Solar cell module and method of producing the same
US6265289B1 (en) * 1998-06-10 2001-07-24 North Carolina State University Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby
JP4005701B2 (en) 1998-06-24 2007-11-14 シャープ株式会社 Method of forming nitrogen compound semiconductor film and nitrogen compound semiconductor element
KR100580307B1 (en) 1998-07-14 2006-05-16 후지쯔 가부시끼가이샤 Semiconductor laser and semiconductor apparatus
EP1115163A4 (en) 1998-09-10 2001-12-05 Rohm Co Ltd Semiconductor light-emitting device and method for manufacturing the same
US6252261B1 (en) 1998-09-30 2001-06-26 Nec Corporation GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor
JP3868136B2 (en) 1999-01-20 2007-01-17 日亜化学工業株式会社 Gallium nitride compound semiconductor light emitting device
JP3372226B2 (en) 1999-02-10 2003-01-27 日亜化学工業株式会社 Nitride semiconductor laser device
US7145167B1 (en) 2000-03-11 2006-12-05 International Business Machines Corporation High speed Ge channel heterostructures for field effect devices
DE10017137A1 (en) 1999-04-14 2000-10-26 Siemens Ag Novel silicon structure, used for solar cells or LCD TFTs, comprises a crystalline textured silicon thin film over a biaxially textured lattice-matched diffusion barrier buffer layer on a thermal expansion-matched inert substrate
US6803598B1 (en) 1999-05-07 2004-10-12 University Of Delaware Si-based resonant interband tunneling diodes and method of making interband tunneling diodes
JP3587081B2 (en) 1999-05-10 2004-11-10 豊田合成株式会社 Method of manufacturing group III nitride semiconductor and group III nitride semiconductor light emitting device
WO2000070683A1 (en) * 1999-05-13 2000-11-23 Hitachi, Ltd. Semiconductor memory
US6252287B1 (en) 1999-05-19 2001-06-26 Sandia Corporation InGaAsN/GaAs heterojunction for multi-junction solar cells
JP3555500B2 (en) 1999-05-21 2004-08-18 豊田合成株式会社 Group III nitride semiconductor and method of manufacturing the same
GB9912178D0 (en) 1999-05-25 1999-07-28 Univ Court Of The University O Improved optical modulator
US6214653B1 (en) 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
JP2001007447A (en) 1999-06-18 2001-01-12 Nichia Chem Ind Ltd Nitride semiconductor laser element
US6635110B1 (en) 1999-06-25 2003-10-21 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
US6228691B1 (en) 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same
GB9919479D0 (en) 1999-08-17 1999-10-20 Imperial College Island arrays
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
JP2001102678A (en) 1999-09-29 2001-04-13 Toshiba Corp Gallium nitride compound semiconductor element
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6812053B1 (en) 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
JP2001189483A (en) 1999-10-18 2001-07-10 Sharp Corp Solar battery cell with bypass function, multi-junction laminating type solar battery cell with bypass function, and their manufacturing method
DE60036594T2 (en) 1999-11-15 2008-01-31 Matsushita Electric Industrial Co., Ltd., Kadoma Field effect semiconductor device
US6521514B1 (en) * 1999-11-17 2003-02-18 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
JP2001176805A (en) * 1999-12-16 2001-06-29 Sony Corp Method for manufacturing crystal of nitride-based iii-v- group compound. nitride-based iii-v-group crystal substrate, nitride-based iii-v-group compound crystal film, and method for manufacturing device
US6403451B1 (en) 2000-02-09 2002-06-11 Noerh Carolina State University Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
AU2001233526A1 (en) * 2000-02-11 2001-08-20 Novo Rps Ulc Stent delivery system and method of use
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP3512701B2 (en) 2000-03-10 2004-03-31 株式会社東芝 Semiconductor device and manufacturing method thereof
TW504754B (en) * 2000-03-24 2002-10-01 Sumitomo Chemical Co Group III-V compound semiconductor and method of producing the same
US20050184302A1 (en) 2000-04-04 2005-08-25 Toshimasa Kobayashi Nitride semiconductor device and method of manufacturing the same
US6362071B1 (en) * 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
JP2001338988A (en) 2000-05-25 2001-12-07 Hitachi Ltd Semiconductor device and its manufacturing method
US6699419B1 (en) * 2000-06-05 2004-03-02 General Motors Corporation Method of forming a composite article with a textured surface and mold therefor
US6352071B1 (en) * 2000-06-20 2002-03-05 Seh America, Inc. Apparatus and method for reducing bow and warp in silicon wafers sliced by a wire saw
US6841808B2 (en) * 2000-06-23 2005-01-11 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing the same
US20020030246A1 (en) * 2000-06-28 2002-03-14 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
US20020008234A1 (en) 2000-06-28 2002-01-24 Motorola, Inc. Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure
JP3882539B2 (en) * 2000-07-18 2007-02-21 ソニー株式会社 Semiconductor light emitting device, method for manufacturing the same, and image display device
AU2001277001A1 (en) 2000-07-24 2002-02-05 Motorola, Inc. Heterojunction tunneling diodes and process for fabricating same
JP2002118255A (en) 2000-07-31 2002-04-19 Toshiba Corp Semiconductor device and manufacturing method thereof
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP4269541B2 (en) * 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ Semiconductor substrate, field effect transistor, method of forming SiGe layer, method of forming strained Si layer using the same, and method of manufacturing field effect transistor
US6579463B1 (en) * 2000-08-18 2003-06-17 The Regents Of The University Of Colorado Tunable nanomasks for pattern transfer and nanocluster array formation
US7301199B2 (en) * 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US20060175601A1 (en) 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
US6407425B1 (en) 2000-09-21 2002-06-18 Texas Instruments Incorporated Programmable neuron MOSFET on SOI
US6456214B1 (en) 2000-09-27 2002-09-24 Raytheon Company High-speed comparator utilizing resonant tunneling diodes and associated method
JP4044276B2 (en) * 2000-09-28 2008-02-06 株式会社東芝 Semiconductor device and manufacturing method thereof
US6555891B1 (en) * 2000-10-17 2003-04-29 International Business Machines Corporation SOI hybrid structure with selective epitaxial growth of silicon
US7163864B1 (en) * 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
JP2002198560A (en) * 2000-12-26 2002-07-12 Sharp Corp Semiconductor light emitting element and its manufacturing method
US6720090B2 (en) 2001-01-02 2004-04-13 Eastman Kodak Company Organic light emitting diode devices with improved luminance efficiency
JP4084541B2 (en) 2001-02-14 2008-04-30 豊田合成株式会社 Manufacturing method of semiconductor crystal and semiconductor light emitting device
DE60233386D1 (en) 2001-02-14 2009-10-01 Toyoda Gosei Kk METHOD FOR PRODUCING SEMICONDUCTOR CRYSTALS AND SEMICONDUCTOR LIGHT ELEMENTS
JP4084544B2 (en) 2001-03-30 2008-04-30 豊田合成株式会社 Semiconductor substrate and semiconductor device manufacturing method
US6380590B1 (en) 2001-02-22 2002-04-30 Advanced Micro Devices, Inc. SOI chip having multiple threshold voltage MOSFETs by using multiple channel materials and method of fabricating same
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP3679720B2 (en) * 2001-02-27 2005-08-03 三洋電機株式会社 Nitride semiconductor device and method for forming nitride semiconductor
JP2002270516A (en) * 2001-03-07 2002-09-20 Nec Corp Growing method of iii group nitride semiconductor, film thereof and semiconductor element using the same
US7205604B2 (en) 2001-03-13 2007-04-17 International Business Machines Corporation Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
JP3705142B2 (en) 2001-03-27 2005-10-12 ソニー株式会社 Nitride semiconductor device and manufacturing method thereof
TW554388B (en) 2001-03-30 2003-09-21 Univ California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
JP3956637B2 (en) 2001-04-12 2007-08-08 ソニー株式会社 Nitride semiconductor crystal growth method and semiconductor element formation method
GB0110112D0 (en) 2001-04-25 2001-06-20 Univ Glasgow Improved optoelectronic device
GB0111207D0 (en) 2001-05-08 2001-06-27 Btg Int Ltd A method to produce germanium layers
US6784074B2 (en) 2001-05-09 2004-08-31 Nsc-Nanosemiconductor Gmbh Defect-free semiconductor templates for epitaxial growth and method of making same
JP3819730B2 (en) 2001-05-11 2006-09-13 三洋電機株式会社 Nitride-based semiconductor device and method for forming nitride semiconductor
US20020168802A1 (en) 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US7358578B2 (en) 2001-05-22 2008-04-15 Renesas Technology Corporation Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring
TW544956B (en) 2001-06-13 2003-08-01 Matsushita Electric Ind Co Ltd Nitride semiconductor, production method therefor and nitride semiconductor element
JP3515974B2 (en) 2001-06-13 2004-04-05 松下電器産業株式会社 Nitride semiconductor, manufacturing method thereof and nitride semiconductor device
US6566284B2 (en) 2001-08-07 2003-05-20 Hrl Laboratories, Llc Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom
JP3785970B2 (en) * 2001-09-03 2006-06-14 日本電気株式会社 Method for manufacturing group III nitride semiconductor device
JP2003077847A (en) * 2001-09-06 2003-03-14 Sumitomo Chem Co Ltd Manufacturing method of 3-5 compound semiconductor
JP2003163370A (en) 2001-09-11 2003-06-06 Toyoda Gosei Co Ltd Method of manufacturing semiconductor crystal
TW544930B (en) 2001-09-11 2003-08-01 Toyoda Gosei Kk Method for producing semiconductor crystal
US7105865B2 (en) * 2001-09-19 2006-09-12 Sumitomo Electric Industries, Ltd. AlxInyGa1−x−yN mixture crystal substrate
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US6710368B2 (en) * 2001-10-01 2004-03-23 Ken Scott Fisher Quantum tunneling transistor
US20030070707A1 (en) 2001-10-12 2003-04-17 King Richard Roland Wide-bandgap, lattice-mismatched window layer for a solar energy conversion device
JP2003152220A (en) * 2001-11-15 2003-05-23 Sharp Corp Manufacturing method for semiconductor light emitting element and the semiconductor light emitting element
US6835246B2 (en) 2001-11-16 2004-12-28 Saleem H. Zaidi Nanostructures for hetero-expitaxial growth on silicon substrates
US6576532B1 (en) 2001-11-30 2003-06-10 Motorola Inc. Semiconductor device and method therefor
AU2002354254A1 (en) 2001-12-20 2003-07-09 Matsushita Electric Industrial Co., Ltd. Method for making nitride semiconductor substrate and method for making nitride semiconductor device
JP4207781B2 (en) 2002-01-28 2009-01-14 日亜化学工業株式会社 Nitride semiconductor device having supporting substrate and method for manufacturing the same
KR100458288B1 (en) 2002-01-30 2004-11-26 한국과학기술원 Double-Gate FinFET
US7411233B2 (en) * 2002-08-27 2008-08-12 E-Phocus, Inc Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US6492216B1 (en) 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel
JP3782021B2 (en) 2002-02-22 2006-06-07 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate manufacturing method
AU2002252110A1 (en) 2002-02-27 2003-09-09 Midwest Research Institute Monolithic photovoltaic energy conversion device
JP4092927B2 (en) * 2002-02-28 2008-05-28 豊田合成株式会社 Group III nitride compound semiconductor, group III nitride compound semiconductor element, and method for manufacturing group III nitride compound semiconductor substrate
JP4307113B2 (en) * 2002-03-19 2009-08-05 宣彦 澤木 Semiconductor light emitting device and manufacturing method thereof
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US7208393B2 (en) 2002-04-15 2007-04-24 The Regents Of The University Of California Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy
WO2003089696A1 (en) * 2002-04-15 2003-10-30 The Regents Of The University Of California Dislocation reduction in non-polar gallium nitride thin films
US20060162768A1 (en) 2002-05-21 2006-07-27 Wanlass Mark W Low bandgap, monolithic, multi-bandgap, optoelectronic devices
US8067687B2 (en) 2002-05-21 2011-11-29 Alliance For Sustainable Energy, Llc High-efficiency, monolithic, multi-bandgap, tandem photovoltaic energy converters
US7217882B2 (en) 2002-05-24 2007-05-15 Cornell Research Foundation, Inc. Broad spectrum solar cell
CN2550906Y (en) 2002-05-27 2003-05-14 李映华 Stereo light double side junction light battery
FR2840452B1 (en) 2002-05-28 2005-10-14 Lumilog PROCESS FOR THE EPITAXIC PRODUCTION OF A GALLIUM NITRIDE FILM SEPARATED FROM ITS SUBSTRATE
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
JP2004014856A (en) 2002-06-07 2004-01-15 Sharp Corp Method for manufacturing semiconductor substrate and semiconductor device
KR20050032527A (en) 2002-06-19 2005-04-07 메사추세츠 인스티튜트 오브 테크놀로지 Ge photodetectors
US6887773B2 (en) 2002-06-19 2005-05-03 Luxtera, Inc. Methods of incorporating germanium within CMOS process
US7012298B1 (en) 2002-06-21 2006-03-14 Advanced Micro Devices, Inc. Non-volatile memory device
US6617643B1 (en) 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
US7335908B2 (en) 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
US6982204B2 (en) * 2002-07-16 2006-01-03 Cree, Inc. Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
EP1530800B1 (en) 2002-08-23 2016-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US7015497B1 (en) 2002-08-27 2006-03-21 The Ohio State University Self-aligned and self-limited quantum dot nanoswitches and methods for making same
US20040043584A1 (en) * 2002-08-27 2004-03-04 Thomas Shawn G. Semiconductor device and method of making same
GB0220438D0 (en) 2002-09-03 2002-10-09 Univ Warwick Formation of lattice-turning semiconductor substrates
US7122733B2 (en) 2002-09-06 2006-10-17 The Boeing Company Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds
US6830953B1 (en) 2002-09-17 2004-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Suppression of MOSFET gate leakage current
US6815241B2 (en) 2002-09-25 2004-11-09 Cao Group, Inc. GaN structures having low dislocation density and methods of manufacture
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6787864B2 (en) 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
JP4546021B2 (en) 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 Insulated gate field effect transistor and semiconductor device
US6902991B2 (en) 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6920159B2 (en) 2002-11-29 2005-07-19 Optitune Plc Tunable optical source
AU2003297649A1 (en) 2002-12-05 2004-06-30 Blue Photonics, Inc. High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
EP1576671A4 (en) * 2002-12-16 2006-10-25 Univ California Growth of planar, non-polar a-plane gallium nitride by hydride vapor phase epitaxy
US7453129B2 (en) 2002-12-18 2008-11-18 Noble Peak Vision Corp. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US7589380B2 (en) * 2002-12-18 2009-09-15 Noble Peak Vision Corp. Method for forming integrated circuit utilizing dual semiconductors
US7012314B2 (en) * 2002-12-18 2006-03-14 Agere Systems Inc. Semiconductor devices with reduced active region defects and unique contacting schemes
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US6686245B1 (en) * 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US7098487B2 (en) 2002-12-27 2006-08-29 General Electric Company Gallium nitride crystal and method of making same
KR100513316B1 (en) * 2003-01-21 2005-09-09 삼성전기주식회사 Manufacturing method of semiconductor device having high efficiency
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
JP2004235190A (en) * 2003-01-28 2004-08-19 Sony Corp Optical semiconductor device
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
DE10320160A1 (en) 2003-02-14 2004-08-26 Osram Opto Semiconductors Gmbh Production of semiconductor bodies for e.g. optoelectronic components comprises forming a mask layer on the substrate or on an initial layer having windows to the substrate, back-etching, and further processing
US6815738B2 (en) 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
CN100437970C (en) 2003-03-07 2008-11-26 琥珀波系统公司 Shallow trench isolation process
JP4695824B2 (en) 2003-03-07 2011-06-08 富士電機ホールディングス株式会社 Manufacturing method of semiconductor wafer
EP1609177A2 (en) * 2003-03-21 2005-12-28 North Carolina State University Methods for nanoscale structures from optical lithography and subsequent lateral growth
US6936851B2 (en) 2003-03-21 2005-08-30 Tien Yang Wang Semiconductor light-emitting device and method for manufacturing the same
US7061065B2 (en) 2003-03-31 2006-06-13 National Chung-Hsing University Light emitting diode and method for producing the same
US6900502B2 (en) 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US20050212051A1 (en) 2003-04-16 2005-09-29 Sarnoff Corporation Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies
JP2004336040A (en) * 2003-04-30 2004-11-25 Osram Opto Semiconductors Gmbh Method of fabricating plurality of semiconductor chips and electronic semiconductor baseboard
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6909186B2 (en) 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US7088143B2 (en) 2003-05-22 2006-08-08 The Regents Of The University Of Michigan Dynamic circuits having improved noise tolerance and method for designing same
US6849487B2 (en) * 2003-05-27 2005-02-01 Motorola, Inc. Method for forming an electronic structure using etch
TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
US7262117B1 (en) 2003-06-10 2007-08-28 Luxtera, Inc. Germanium integrated CMOS wafer and method for manufacturing the same
JP4105044B2 (en) 2003-06-13 2008-06-18 株式会社東芝 Field effect transistor
US6974733B2 (en) 2003-06-16 2005-12-13 Intel Corporation Double-gate transistor with enhanced carrier mobility
US6943407B2 (en) 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
JP2005011915A (en) 2003-06-18 2005-01-13 Hitachi Ltd Semiconductor device, semiconductor circuit module and its manufacturing method
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
KR100631832B1 (en) 2003-06-24 2006-10-09 삼성전기주식회사 White light emitting device and its manufacturing method
US7122392B2 (en) 2003-06-30 2006-10-17 Intel Corporation Methods of forming a high germanium concentration silicon germanium alloy by epitaxial lateral overgrowth and structures formed thereby
US20050017351A1 (en) * 2003-06-30 2005-01-27 Ravi Kramadhati V. Silicon on diamond wafers and devices
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
JP2005051022A (en) * 2003-07-28 2005-02-24 Seiko Epson Corp Semiconductor device and its manufacturing method
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6855583B1 (en) * 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation
JP4322255B2 (en) 2003-08-05 2009-08-26 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7101742B2 (en) 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050035410A1 (en) * 2003-08-15 2005-02-17 Yee-Chia Yeo Semiconductor diode with reduced leakage
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6815278B1 (en) 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US7078299B2 (en) 2003-09-03 2006-07-18 Advanced Micro Devices, Inc. Formation of finFET using a sidewall epitaxial layer
US6955969B2 (en) 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance
JP4439358B2 (en) 2003-09-05 2010-03-24 株式会社東芝 Field effect transistor and manufacturing method thereof
US20050054164A1 (en) * 2003-09-09 2005-03-10 Advanced Micro Devices, Inc. Strained silicon MOSFETs having reduced diffusion of n-type dopants
US7579263B2 (en) * 2003-09-09 2009-08-25 Stc.Unm Threading-dislocation-free nanoheteroepitaxy of Ge on Si using self-directed touch-down of Ge through a thin SiO2 layer
US7138292B2 (en) 2003-09-10 2006-11-21 Lsi Logic Corporation Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide
US7211864B2 (en) * 2003-09-15 2007-05-01 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US20050056827A1 (en) * 2003-09-15 2005-03-17 Agency For Science, Technology And Research CMOS compatible low band offset double barrier resonant tunneling diode
WO2005029583A2 (en) 2003-09-19 2005-03-31 Spinnaker Semiconductor, Inc. Schottky barrier integrated circuit
US6831350B1 (en) 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
US6919258B2 (en) 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
JP2007507905A (en) 2003-10-03 2007-03-29 スピンネイカー セミコンダクター インコーポレイテッド Schottky barrier MOSFET manufacturing method using isotropic etching process
US6900491B2 (en) 2003-10-06 2005-05-31 Hewlett-Packard Development Company, L.P. Magnetic memory
EP1683193A1 (en) 2003-10-22 2006-07-26 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US7009215B2 (en) * 2003-10-24 2006-03-07 General Electric Company Group III-nitride based resonant cavity light emitting devices fabricated on single crystal gallium nitride substrates
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US7057216B2 (en) 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US6902965B2 (en) 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
GB0326321D0 (en) 2003-11-12 2003-12-17 Univ Warwick Formation of lattice-tuning semiconductor substrates
US20050104156A1 (en) * 2003-11-13 2005-05-19 Texas Instruments Incorporated Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
JP2005191530A (en) 2003-12-03 2005-07-14 Sumitomo Electric Ind Ltd Light emitting device
JP4473710B2 (en) 2003-12-05 2010-06-02 株式会社東芝 Semiconductor device
US7198995B2 (en) 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US6958286B2 (en) 2004-01-02 2005-10-25 International Business Machines Corporation Method of preventing surface roughening during hydrogen prebake of SiGe substrates
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7705345B2 (en) 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7138302B2 (en) 2004-01-12 2006-11-21 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit channel region
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7198970B2 (en) 2004-01-23 2007-04-03 The United States Of America As Represented By The Secretary Of The Navy Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
US7118987B2 (en) 2004-01-29 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of achieving improved STI gap fill with reduced stress
DE102004005506B4 (en) * 2004-01-30 2009-11-19 Atmel Automotive Gmbh Method of producing semiconductor active layers of different thickness in an SOI wafer
US7180134B2 (en) * 2004-01-30 2007-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for planar and multiple-gate transistors formed on SOI
US6855982B1 (en) * 2004-02-02 2005-02-15 Advanced Micro Devices, Inc. Self aligned double gate transistor having a strained channel region and process therefor
US7205210B2 (en) 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
US7492022B2 (en) 2004-02-27 2009-02-17 University Of Iowa Research Foundation Non-magnetic semiconductor spin transistor
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
US6888181B1 (en) 2004-03-18 2005-05-03 United Microelectronics Corp. Triple gate device having strained-silicon channel
US20050211291A1 (en) 2004-03-23 2005-09-29 The Boeing Company Solar cell assembly
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
US7087965B2 (en) 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US7445673B2 (en) 2004-05-18 2008-11-04 Lumilog Manufacturing gallium nitride substrates by lateral overgrowth through masks and devices fabricated thereof
US7084441B2 (en) 2004-05-20 2006-08-01 Cree, Inc. Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
JP5461773B2 (en) 2004-06-03 2014-04-02 独立行政法人科学技術振興機構 Growth of flat and low dislocation density m-plane gallium nitride by hydride vapor deposition
US7994527B2 (en) 2005-11-04 2011-08-09 The Regents Of The University Of California High light extraction efficiency light emitting diode (LED)
US7125785B2 (en) 2004-06-14 2006-10-24 International Business Machines Corporation Mixed orientation and mixed material semiconductor-on-insulator wafer
US7807921B2 (en) 2004-06-15 2010-10-05 The Boeing Company Multijunction solar cell having a lattice mismatched GrIII-GrV-X layer and a composition-graded buffer layer
US7244958B2 (en) 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) * 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
US20060211210A1 (en) 2004-08-27 2006-09-21 Rensselaer Polytechnic Institute Material for selective deposition and etching
TWI500072B (en) 2004-08-31 2015-09-11 Sophia School Corp Manufacturing method for light emitting element
US20060073681A1 (en) 2004-09-08 2006-04-06 Han Sang M Nanoheteroepitaxy of Ge on Si as a foundation for group III-V and II-VI integration
US7002175B1 (en) * 2004-10-08 2006-02-21 Agency For Science, Technology And Research Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration
US7846759B2 (en) 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
US20060105533A1 (en) 2004-11-16 2006-05-18 Chong Yung F Method for engineering hybrid orientation/material semiconductor substrate
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US20060131606A1 (en) * 2004-12-18 2006-06-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods
US7405436B2 (en) * 2005-01-05 2008-07-29 International Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
JP2006196631A (en) 2005-01-13 2006-07-27 Hitachi Ltd Semiconductor device and its manufacturing method
US7138309B2 (en) * 2005-01-19 2006-11-21 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer
US7344942B2 (en) 2005-01-26 2008-03-18 Micron Technology, Inc. Isolation regions for semiconductor devices and their formation
US7224033B2 (en) 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
JP2006253181A (en) 2005-03-08 2006-09-21 Seiko Epson Corp Semiconductor device and its manufacturing method
KR100712753B1 (en) 2005-03-09 2007-04-30 주식회사 실트론 Compound semiconductor device and method for manufacturing the same
TWI246210B (en) * 2005-04-28 2005-12-21 Epitech Corp Ltd Lateral current blocking light emitting diode and method for manufacturing the same
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) * 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20070267722A1 (en) 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2006332295A (en) 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd Hetero-junction bipolar transistor and manufacturing method thereof
TW200703463A (en) 2005-05-31 2007-01-16 Univ California Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO)
WO2007014294A2 (en) 2005-07-26 2007-02-01 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US7801406B2 (en) * 2005-08-01 2010-09-21 Massachusetts Institute Of Technology Method of fabricating Ge or SiGe/Si waveguide or photonic crystal structures by selective growth
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US7358107B2 (en) 2005-10-27 2008-04-15 Sharp Laboratories Of America, Inc. Method of fabricating a germanium photo detector on a high quality germanium epitaxial overgrowth layer
US8120060B2 (en) 2005-11-01 2012-02-21 Massachusetts Institute Of Technology Monolithically integrated silicon and III-V electronics
US7629661B2 (en) 2006-02-10 2009-12-08 Noble Peak Vision Corp. Semiconductor devices with photoresponsive components and metal silicide light blocking structures
KR100790869B1 (en) 2006-02-16 2008-01-03 삼성전자주식회사 Single crystal substrate and fabrication method thereof
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US20080154197A1 (en) 2006-12-20 2008-06-26 Joel Brian Derrico System and method for regulating the temperature of a fluid injected into a patient
JP2008198656A (en) 2007-02-08 2008-08-28 Shin Etsu Chem Co Ltd Method of manufacturing semiconductor substrate
US7825328B2 (en) * 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
KR20080102065A (en) 2007-05-18 2008-11-24 삼성전자주식회사 Method of forming a epitaxial silicon structure and method of forming a semiconductor device using the same
US8329541B2 (en) * 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR20090010284A (en) 2007-07-23 2009-01-30 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
DE112008002387B4 (en) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a multijunction solar cell, method of forming a photonic device, photovoltaic multijunction cell and photovoltaic multijunction cell device,
US7883990B2 (en) 2007-10-31 2011-02-08 International Business Machines Corporation High resistivity SOI base wafer using thermally annealed substrate
WO2009084238A1 (en) 2007-12-28 2009-07-09 Sumitomo Chemical Company, Limited Semiconductor substrate, method for manufacturing semiconductor substrate, and electronic device
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) * 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) * 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
CN102379046B (en) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 Devices formed from a non-polar plane of a crystalline material and method of making the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0262090A (en) * 1988-08-29 1990-03-01 Matsushita Electric Ind Co Ltd Manufacture of optical semiconductor device
US6015979A (en) * 1997-08-29 2000-01-18 Kabushiki Kaisha Toshiba Nitride-based semiconductor element and method for manufacturing the same
US6100106A (en) * 1997-11-17 2000-08-08 Nec Corporation Fabrication of nitride semiconductor light-emitting device
JP2000286449A (en) * 1999-03-31 2000-10-13 Toyoda Gosei Co Ltd Iii nitride compound semiconductor device and its manufacture
US6342404B1 (en) * 1999-03-31 2002-01-29 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing
US20030087462A1 (en) * 2001-11-02 2003-05-08 Norikatsu Koide Semiconductor light emitting device and method for producing the same
EP1551063A1 (en) * 2002-06-04 2005-07-06 Nitride Semiconductors Co., Ltd. Gallium nitride compound semiconductor device and manufacturing method
JP2004200375A (en) * 2002-12-18 2004-07-15 Matsushita Electric Ind Co Ltd Semiconductor laser device and method of manufacturing the same
WO2006125040A2 (en) * 2005-05-17 2006-11-23 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2343742A3 (en) * 2010-01-08 2014-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
EP2849208A1 (en) * 2013-09-13 2015-03-18 Commissariat A L'energie Atomique Et Aux Energies Alternatives Optimised method for manufacturing patterns of III-V semiconductor material on a semiconductor substrate
FR3010828A1 (en) * 2013-09-13 2015-03-20 Commissariat Energie Atomique OPTIMIZED METHOD OF MANUFACTURING III-V SEMICONDUCTOR MATERIAL PATTERNS ON A SEMICONDUCTOR SUBSTRATE
US9293322B2 (en) 2013-09-13 2016-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Optimized method for fabricating patterns of III-V semiconductor material on a semiconductor substrate
EP2869331A1 (en) * 2013-10-29 2015-05-06 IMEC vzw Episubstrates for selective area growth of group iii-v material and a method for fabricating a group iii-v material on a silicon substrate
US10014374B2 (en) 2013-12-18 2018-07-03 Intel Corporation Planar heterogeneous device

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