WO2008062164A3 - Hardware architecure for video conferencing - Google Patents

Hardware architecure for video conferencing Download PDF

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Publication number
WO2008062164A3
WO2008062164A3 PCT/GB2007/004404 GB2007004404W WO2008062164A3 WO 2008062164 A3 WO2008062164 A3 WO 2008062164A3 GB 2007004404 W GB2007004404 W GB 2007004404W WO 2008062164 A3 WO2008062164 A3 WO 2008062164A3
Authority
WO
WIPO (PCT)
Prior art keywords
daughterboard
switch
daughterboards
motherboard
video processing
Prior art date
Application number
PCT/GB2007/004404
Other languages
French (fr)
Other versions
WO2008062164A2 (en
Inventor
Simon James Winn Evans
Original Assignee
Codian Ltd
Simon James Winn Evans
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0623096A external-priority patent/GB0623096D0/en
Priority claimed from GB0623097A external-priority patent/GB0623097D0/en
Priority claimed from GB0623098A external-priority patent/GB0623098D0/en
Priority claimed from GB0623100A external-priority patent/GB0623100D0/en
Application filed by Codian Ltd, Simon James Winn Evans filed Critical Codian Ltd
Priority to CN2007800492644A priority Critical patent/CN101573974B/en
Priority to JP2009536799A priority patent/JP5200029B2/en
Priority to EP07824621.2A priority patent/EP2105015B1/en
Publication of WO2008062164A2 publication Critical patent/WO2008062164A2/en
Publication of WO2008062164A3 publication Critical patent/WO2008062164A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/14—Systems for two-way working
    • H04N7/15—Conference systems
    • H04N7/152—Multipoint control units therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks

Abstract

Video processing architectures, systems, and methods for a multipoint control unit are provided. In one example, a video processing system includes a motherboard and at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, where the daughterboard switch is configured to switch data between the plurality of processors and between the motherboard and daughterboard. The video processing system may further include a plurality of daughterboards each having an identical hardware and/or mechanical configuration. The plurality of daughterboards may be configured to be mechanically and electrically couplable together in any order, and may be stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along said series chain.
PCT/GB2007/004404 2006-11-20 2007-11-19 Hardware architecure for video conferencing WO2008062164A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800492644A CN101573974B (en) 2006-11-20 2007-11-19 Hardware architecure for video conferencing
JP2009536799A JP5200029B2 (en) 2006-11-20 2007-11-19 Video conferencing hardware architecture
EP07824621.2A EP2105015B1 (en) 2006-11-20 2007-11-19 Hardware architecture for video conferencing

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
GB0623096A GB0623096D0 (en) 2006-11-20 2006-11-20 Hardware architecture for video conferencing
GB0623097A GB0623097D0 (en) 2006-11-20 2006-11-20 Hardware architecture for video conferencing
GB0623100.5 2006-11-20
GB0623098A GB0623098D0 (en) 2006-11-20 2006-11-20 Hardware architecture for video conferencing
GB0623098.1 2006-11-20
GB0623100A GB0623100D0 (en) 2006-11-20 2006-11-20 Hardware architecture for video conferencing
GB0623097.3 2006-11-20
GB0623096.5 2006-11-20

Publications (2)

Publication Number Publication Date
WO2008062164A2 WO2008062164A2 (en) 2008-05-29
WO2008062164A3 true WO2008062164A3 (en) 2009-02-19

Family

ID=39430101

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2007/004404 WO2008062164A2 (en) 2006-11-20 2007-11-19 Hardware architecure for video conferencing

Country Status (5)

Country Link
US (2) US7889226B2 (en)
EP (1) EP2105015B1 (en)
JP (1) JP5200029B2 (en)
CN (1) CN102065270B (en)
WO (1) WO2008062164A2 (en)

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US9218316B2 (en) 2011-01-05 2015-12-22 Sphero, Inc. Remotely controlling a self-propelled device in a virtualized environment
US10281915B2 (en) 2011-01-05 2019-05-07 Sphero, Inc. Multi-purposed self-propelled device
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Also Published As

Publication number Publication date
EP2105015B1 (en) 2020-04-22
US7889226B2 (en) 2011-02-15
US8169464B2 (en) 2012-05-01
CN102065270B (en) 2013-09-25
US20090213126A1 (en) 2009-08-27
US20080158338A1 (en) 2008-07-03
JP2010510705A (en) 2010-04-02
JP5200029B2 (en) 2013-05-15
CN102065270A (en) 2011-05-18
EP2105015A2 (en) 2009-09-30
WO2008062164A2 (en) 2008-05-29

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