WO2008066351A1

WO2008066351A1 - Multiple transmitting and receiving system for space-time encoding using orthogonal sequence

Info

Publication number: WO2008066351A1
Application number: PCT/KR2007/006152
Authority: WO
Inventors: Seog-Ill Song; Young-Il Kim; Jee-Hwan Ahn
Original assignee: Electronics And Telecommunications Research Institute; Samsung Electronics Co., Ltd.
Priority date: 2006-12-01
Filing date: 2007-11-30
Publication date: 2008-06-05

Abstract

The present invention relates to a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence and a method of transmitting data in a multiple transmitting and receiving system. A transmitting apparatus of a multiple transmitting and receiving system includes a plurality of transmission processing units that are provided to correspond to a plurality of transmitting antennas, and a serial-to-parallel converting unit that performs space-time encoding on input data and generates parallel data to correspond to the plurality of transmission processing units. Each of the transmission processing units includes a real component processor that performs orthogonal encoding on a real component of corresponding data among the parallel data generated by the serial-to-parallel converting unit, an imaginary component processor that performs orthogonal encoding on an imaginary component of corresponding data among the parallel data generated by the serial-to-parallel converting unit, and a synthesizer that synthesizes data output from the real component processor and the imaginary component processor to transmit the synthesized data through a corresponding transmitting antenna.

Description

MULTIPLE TRANSMITTING AND RECEIVING SYSTEM FOR SPACE-TIME ENCODING USING ORTHOGONAL SEQUENCE

Technical Field

[1] The present invention relates to a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence and a method of transmitting data in a multiple transmitting and receiving system. Background Art

[2] In modulation/demodulation schemes, a QAM scheme is used to support an increasing data transfer rate within a limited frequency bandwidth. However, a mobility problem occurs and performance during usage is deteriorated due to a distance greater than a predetermined value in 16 or more QAM.

[3] In recent years, the fact that channel capacity in the same bandwidth is proportional to the number of transmitting and receiving antennas when a multiple transmitting and receiving (multiple input multiple output (MIMO)) antenna is used in a channel having rich scattering characteristics has been disclosed. Since then, application of the MIMO technology has been studied using various methods of detecting received signals.

[4] According to the methods of detecting a received signal using the MIMO technology, since a channel status changes, improvement in the performance is possible by using a transmission speed that is adjusted according to the channel status. Further, by using a unique spreading code and orthogonal codes, a data transfer rate has been increased without increasing an entire bandwidth used by users.

[5] According to a space-time encoding technology, an encoding scheme is coupled to a space diversity scheme where data is transmitted through a plurality of transmitting antennas and excellent performance is achieved in a wireless mobile communication fading channel. The space-time encoding technology is advantageous for multimedia transmission when a large amount of information is transmitted with excellent quality but using a limited frequency resource.

[6] However, in the space-time encoding technology that maintains orthogonality, when the number of transmitting antennas is three or more, it is not possible to satisfy a maximum transfer rate 1 (symbol/channel use), and a decoding process is very complex.

[7] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Disclosure of Invention

Technical Problem

[8] The present invention has been made in an effort to provide a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence, having advantages of a high transfer rate and a simple decoding process. Technical Solution

[9] An exemplary embodiment of the present invention provides a transmitting apparatus of a multiple transmitting and receiving system. The transmitting apparatus includes a plurality of transmission processing units that are provided to correspond to a plurality of transmitting antennas, and a serial-to-parallel converting unit that performs space- time encoding on input data and generates parallel data to correspond to the plurality of transmission processing units. Each of the transmission processing units includes a real component processor that performs orthogonal encoding on a real component of corresponding data among the parallel data generated by the serial-to-parallel converting unit, an imaginary component processor that performs orthogonal encoding on an imaginary component of corresponding data among the parallel data generated by the serial-to-parallel converting unit, and a synthesizer that synthesizes data output from the real component processor and the imaginary component processor to transmit the synthesized data through a corresponding transmitting antenna.

[10] Another embodiment of the present invention provides a receiving apparatus of a multiple transmitting and receiving system. The receiving apparatus includes a plurality of reception processing units that are provided to correspond to a plurality of receiving antennas, and a parallel-to-serial converting unit that converts parallel data received from the plurality of reception processing units into serial data. Each of the reception processing units includes a real component processor that restores a real component of data received through a corresponding receiving antenna, and an imaginary component processor that restores an imaginary component of data received through a corresponding receiving antenna.

[11] Yet another embodiment of the present invention provides a method of transmitting data in a multiple transmitting and receiving system. The method includes performing space-time encoding on input data and generating parallel data to be processed in a plurality of transmission processing units, performing orthogonal encoding on a real component of corresponding data among the parallel data in the plurality of transmission processing units, performing orthogonal encoding on an imaginary component of corresponding data among the parallel data in the plurality of transmission processing units, and synthesizing the real component and the imaginary component on which the orthogonal encoding have been performed. Advantageous Effects

[12] According to the exemplary embodiment of the present invention, it is possible to achieve a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence in which a data rate is high and a decoding process is simple. Brief Description of the Drawings

[13] FIG. 1 is a block diagram illustrating a transmitter of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention.

[14] FIG. 2 is a block diagram illustrating an orthogonal encoding unit shown in FIG. 1.

[15] FIG. 3 is a flowchart illustrating the operation of a transmitter of a multiple transmitting and receiving system according to an exemplary embodiment of the present invention.

[16] FIG. 4 is a block diagram illustrating a receiver of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention.

[17] FIG. 5 is a block diagram illustrating an inverse orthogonal encoding unit shown in

FIG. 4.

[18] FIG. 6 is a flowchart illustrating a process of restoring received data in a reception processing unit. Mode for the Invention

[19] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

[20] It will be understood that the terms "comprises" and "comprising" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term "unit" used herein means one unit that processes a specific function or operation, and may be implemented by hardware, software, or a combination thereof.

[21] First, a transmitter of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention and the operation of the transmitter will be described in detail with reference to FIGS. 1 and 2.

[22] FIG. 1 is a block diagram illustrating a transmitter of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram illustrating an orthogonal encoding unit shown in FIG. 1.

[23] As shown in FIG. 1, a transmitter of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention includes a serial-to-parallel converting unit 101, a plurality of transmission processing units 102, and a plurality of antennas 103 that are provided to correspond to the plurality of transmission processing units 102. Each of the transmission processing units 102 includes a complex signal real component processor 110, a complex signal imaginary component processor 120, and a synthesizer 130. The complex signal real component processor 110 includes a mapper 111, an orthogonal encoding unit 112, a unique spreading code synthesizer 113, and a multiplier 114. The complex signal imaginary component processor 120 includes a mapper 121, an orthogonal encoding unit 122, a unique spreading code synthesizer 123, and a multiplier 124.

[24] The serial-to-parallel converting unit 101 performs space-time encoding on input serial data and generates parallel data to correspond to the plurality of antennas 103. The serial-to-parallel converting unit 101 transmits the generated parallel data to the transmission processing units 102.

[25] In each of the transmission processing units 102, the mappers 111 and 121 of the complex signal real component processor 110 and the complex signal imaginary component processor 120 generate a real component and an imaginary component of input data, which has been input through the serial-to-parallel converting unit 101, as non-binary signal values, and then output them. Each of the orthogonal encoding units 112 and 122 receives the non-binary signal value from each of the mappers 111 and 121 and multiplies the non-binary value by an orthogonal code.

[26] As shown in FIG. 2, each of the orthogonal encoding units 112 and 122 includes a serial-to-parallel converter 112a, orthogonal code converters 112b, and an adder 112c. The serial-to-parallel converter 112a converts the non-binary signals, which are output by the mappers 111 and 121, into parallel data. Each of the orthogonal code converters 112b multiplies the components of the non-binary signal, which has been converted into the parallel data, by corresponding orthogonal codes. The adder 112c outputs a value, which is obtained by adding values of the non-binary signals multiplied by the orthogonal codes, to the corresponding unique spreading code synthesizer 113 or 123.

[27] The unique spreading code synthesizers 113 and 123 multiply the signals, which have been output by the orthogonal encoding units 112 and 122, by corresponding unique spreading codes. The multipliers 114 and 124 multiply the signals, which are output by the unique spreading code synthesizers 113 and 123, by radio frequency signals received from the outside of the transmitter, and output modulated data to the synthesizer 130.

[28] The synthesizer 130 receives two modulated data from the multiplier 114 of the complex signal real component processor 110 and the multiplier 124 of the complex signal imaginary component processor 120 and synthesizes them. The synthesizer 130 transmits the synthesized data as a sky wave through the corresponding antenna 103.

[29] Hereinafter, the operation of the multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to the exemplary embodiment of the present invention will be described using non-binary signal values 16 QAM (Quadrature Amplitude Modulation). FIG. 3 is a flowchart illustrating the operation of a transmitter of a multiple transmitting and receiving system according to an exemplary embodiment of the present invention.

[30] The serial-to-parallel converting unit 101 performs space-time encoding on the input data, and generates parallel data to correspond to the plurality of transmission processing units (step S310).

[31] The real component of the parallel data is input to the mapper 111 of the complex signal real component processor 110, and the imaginary component of the parallel data is input to the mapper 121 of the complex signal imaginary component processor 120. Then, each of the mappers 111 and 121 generates the input data as gray-encoded non- binary signals and outputs them (step S320).

[32] At this time, the non-binary signal, which is output from the mapper 111 of the complex signal real component processor 110, corresponds to d(l) = (d, -d, 3d, d). The non-binary signal, which is output from the mapper 121 of the complex signal imaginary component processor 120, corresponds to d(2) = (-3d, 3d, d, -d). In this case, d denotes a minimum distance of a 16-QAM constellation.

[33] The non-binary signals d(l) and d(2) are respectively input to the orthogonal encoding units 112 and 122, and are then converted into parallel data by the serial- to-parallel converters 112a (step S330). The orthogonal code converters 112b multiply the components of the non-binary signals d(l) and d(2) by orthogonal codes Sub-w(l), Sub-w(2), Sub-w(3), and Sub-w(4) (step S340).

[34] First, if d in the non-binary signals is assumed as a constant and is removed, the conditions d(l) = (+1, -1, +3, +1) and d(2) = (-3, +3, +1, -1) are satisfied. In the orthogonal codes and the unique spreading code, 0 is expressed by - and 1 is expressed by + as follows.

[35] <Orthogonal Code>

[36] Sub-w(l) = (1 1 1 l)-> (+ + + +) [37] Sub-w(2) = (1 0 1 0)~> ( + - + -)

[38] Sub-w(3) = (1 1 0 0)-> ( + + - -)

[39] Sub-w(4) = (1 0 0 1)~> ( + - - + )

[40] <Unique Spreading Code>

[41] Wl = (0 1 0 1 0 1 0 l)->(- + - + - + - +)

[42] The orthogonal code converters 112b of the orthogonal encoding unit 112 of the complex signal real component processor 110 multiply the components of the non- binary signal d(l) by the orthogonal codes Sub-w(l), Sub-w(2), Sub-w(3), and Sub- w(4). If + 1 of d(l) is multiplied by Sub-w(l), the condition C(I l) = (+1 +1 +1 +1) is satisfied, and if -1 of d(l) is multiplied by Sub-w(2), the condition C(12) = (-1 +1 -1 + 1) is satisfied. Further, if +3 of d(l) is multiplied by Sub-w(3), the condition C(13) = (+3 +3 -3 -3) is satisfied, and if +1 of d(l) is multiplied by Sub-w(4), the condition C(14) = (+1 -1 -1 +1) is satisfied.

[43] The orthogonal code converter of the orthogonal encoding unit 122 of the complex signal imaginary component processor 120 multiplies the components of the non- binary signal d(2) by the orthogonal codes Sub-w(l), Sub-w(2), Sub-w(3), and Sub- w(4). If -3 of d(2) is multiplied by Sub-w(l), the condition C(21) = (-3 -3 -3 -3) is satisfied, and if +3 of d(2) is multiplied by Sub-w(2), the condition C(22) = (+3 -3 +3 - 3) is satisfied. Further, if + 1 of d(2) is multiplied by Sub-w(3), the condition C(23) = (+1 +1 -1 -1) is satisfied, and if -1 of d(2) is multiplied by Sub-w(4), the condition C(24) = (-1 +1 +1 -1) is satisfied.

[44] The adder 112c of each of the orthogonal encoding units 112 and 122 adds output values of the corresponding orthogonal code converters 112b (step S350).

[45] The adder 112c of the orthogonal encoding unit 112 of the complex signal real component processor 110 adds output values of the orthogonal code converters 112b of the orthogonal encoding unit 112 of the complex signal real component processor 110. That is, if C(11), C(12), C(13), and C(14) are added, the condition Bl = (+4 +4 -4 0) is satisfied.

[46] The adder of the orthogonal encoding unit 122 of the complex signal imaginary component processor 120 adds output values of the orthogonal code converters of the orthogonal encoding unit 122 of the complex signal imaginary component processor 120. That is, if C(21), C(22), C(23), and C(24) are added, the condition B2 = (0 -4 0 - 8) is satisfied.

[47] The unique spreading code synthesizers 113 and 123 multiply Bl and B2 by the unique spreading code Wl (step S360). If Bl is multiplied by Wl, the condition Dl = (-4+4 -4+4 +4-4 00) is satisfied, and if B2 is multiplied by Wl, the condition D2 = (00 +4-4 00 +8-8) is satisfied.

[48] The multipliers 114 and 124 multiply Dl and D2 by a radio frequency (RF) to perform modulation. Then, the multipliers 114 and 124 generate modulated data and output them (step S370).

[49] The adder 130 synthesizes two modulated data received from the two multipliers 114 and 124 (step S380) and transmits the synthesized data as a sky wave.

[50] The transmitter of the multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention simultaneously transmits the different data synthesized in the above- described method through the plurality of antennas.

[51] Now, a receiver of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention and operation of the receiver will be described.

[52] FIG. 4 is a block diagram illustrating a receiver of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention, and FIG. 5 is a block diagram illustrating an inverse orthogonal encoding unit shown in FIG. 4.

[53] As shown in FIG. 4, a receiver of a multiple transmitting and receiving system for space-time encoding using an orthogonal sequence according to an exemplary embodiment of the present invention includes a plurality of antennas 401, a plurality of reception processing units 402, and a parallel-to-serial converting unit 403. Each of the reception processing units 402 includes a complex signal real component processor 410 and a complex signal imaginary component processor 420. The complex signal real component processor 410 and the complex signal imaginary component processor 420 include multipliers 411 and 421, low pass filters 412 and 422, unique spreading code multipliers 413 and 423, inverse orthogonal encoding units 414 and 424, and inverse mappers 415 and 425, respectively.

[54] The receiver simultaneously receives different transmission data through the plurality of antennas. The receiver demodulates the different transmission data in a plurality of reception processing units, inversely maps the different transmission data, and restores original signals. The complex signal real component processor 410 restores a real component of the received data, and the complex signal imaginary component processor 420 restores an imaginary component of the received data.

[55] As shown in FIG. 5, each of the inverse orthogonal encoding units 414 and 424 includes orthogonal code converters 414a, integrators 414b, and a parallel-to-serial converter 414c. The orthogonal code converters 414a multiply output values of each of the unique spreading code multipliers 413 and 423 by the corresponding orthogonal codes. The integrators 414b integrate the output values of the orthogonal code converters 414a and restore the original signals.

[56] Hereinafter, a process of restoring received data in the plurality of reception processing units 402 will be described with reference to FIG. 6. FIG. 6 is a flowchart illustrating a process of restoring received data in a reception processing unit 402.

[57] First, the low pass filters 412 and 422 remove high frequency components of the received data that has been input through the multipliers 411 and 421 (step S610).

[58] The unique spreading code multipliers 413 and 423 multiply the received data, from which the high frequency components have been removed, by the unique spreading code Wl (step S620). If the real component of the received data, that is, Dl = (-4+4 - 4+4 +4-4 00) is multiplied by Wl, the condition Dl = (+4+4 +4+4 -4-4 00) is satisfied. If the imaginary component of the received data, that is, D2 = (00 +4-4 00 +8-8) is multiplied by Wl, the condition D2 = (00 -4-4 00 -8-8) is satisfied.

[59] The orthogonal code converters 414a of the inverse orthogonal encoding units 414 and 424 multiply output values of the unique spreading code multipliers 413 and 423 by the orthogonal codes Sub-w(l), Sub-w(2), Sub-w(3), and Sub-w(4) (step S630).

[60] The orthogonal code converters 414a of the inverse orthogonal encoding unit 414 of the complex signal real component processor 410 multiply output values of the unique spreading code multiplier 413 by the corresponding orthogonal codes. That is, if (+4+4 +4+4 -4-4 00) is multiplied by (+ + + +) corresponding to the orthogonal code Sub- w(l), it becomes (+4+4 +4+4 -4-4 00 ). If (+4+4 +4+4 -4-4 00) is multiplied by (+ - + - ) corresponding to the orthogonal code Sub-w(2), it becomes (+4+4 -4-4 -4-4 00). If (+4+4 +4+4 -4-4 00) is multiplied by (+ H — ) corresponding to the orthogonal code Sub-w(3), it becomes (+4+4 +4+4 +4+4 00). If (+4+4 +4+4 -4-4 00) is multiplied by (+ h) corresponding to Sub-w(4), it becomes (+4+4 -4-4 +4+4 00).

[61] The orthogonal code converters of the inverse orthogonal encoding unit 424 of the complex signal imaginary component processor 420 multiply output values of the unique spreading code multiplier 423 of the complex signal imaginary component processor 420 by the corresponding orthogonal codes. That is, if (00 -4-4 00 -8-8) is multiplied by (+ + + +) corresponding to the orthogonal code Sub-w(l), it becomes (00 -4-4 00 -8-8). If (00 -4-4 00 -8-8) is multiplied by (+ - + -) corresponding to the orthogonal code Sub-w(2), it becomes (00 +4+4 00 +8+8). If (00 -4-4 00 -8-8) is multiplied by (+ H — ) corresponding to the orthogonal code Sub-w3, it becomes (00 - 4-4 00 +8+8). If (00 -4-4 00 -8-8) is multiplied by (+ - - +) corresponding to the orthogonal code Sub-w(4), it becomes (00 +4+4 00 -8-8).

[62] The integrators 414b of the inverse orthogonal encoding units 414 and 424 add output values of the orthogonal code converters during one period. The integrators 414b multiply values, which are obtained by dividing the output values by values corresponding to one period, by d (minimum distance of a 16-QAM constellation) (step S640). In this case, one period of Wl is divided by 8 and integration is performed for every 1/8 period, such that one period becomes an entire integration interval. [63] If the integrator 414b of the inverse orthogonal encoding unit 414 of the complex signal real component processor 410 divides 8, which corresponds to a value obtained by adding values of (+4+4 +4+4 -4-4 00), by +8 as a value corresponding to one period, a value +1 is obtained. If the integrator 414b divides -8, which corresponds to a value obtained by adding values of (+4+4 -4-4 -4-4 00), by 8, a value -1 is obtained. If the integrator 414b divides +24, which corresponds to a value obtained by adding values of (+4+4 +4+4 +4+4 00), by 8, a value +3 is obtained. If the integrator 414b divides +8, which corresponds to a value obtained by adding values of (+4+4 -4-4 +4+4 00), by 8, a value +1 is obtained. Accordingly, if (+1, -1, +3, +1) is multiplied by d, (d, -d, 3d, d) is obtained.

[64] If the integrator of the inverse orthogonal encoding unit 424 of the complex signal imaginary component processor 420 divides -24, which corresponds to a value obtained by adding values of (00 -4-4 00 -8-8 ), by +8 as a value corresponding to one period, a value -3 is obtained. If the integrator divides +24, which corresponds to a value obtained by adding values of (00 +4+4 00 +8+8), by 8, a value +3 is obtained. If the integrator divides +8, which corresponds to a value obtained by adding values of (00 -4-4 00 +8+8), by 8, a value +1 is obtained. If the integrator divides 8, which corresponds to a value obtained by adding values of (00 +4+4 00 -8-8), by -8, a value -1 is obtained. Accordingly, if (-3, +3, +1, -1) is multiplied by d, (-3d, 3d, d, -d) is restored.

[65] The parallel-to-serial converting unit 403 converts parallel data received from the plurality of reception processing units 402 into serial data.

[66] The exemplary embodiment of the present invention that has been described above may be implemented by not only a method and an apparatus but also a program capable of realizing a function corresponding to the structure according to the exemplary embodiment of the present invention and a recording medium having the program recorded therein. It can be understood by those skilled in the art that the implementation can be easily made from the above-described exemplary embodiment of the present invention.

[67] While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[68]

Claims

[1] A transmitting apparatus of a multiple transmitting and receiving system, the transmitting apparatus comprising: a plurality of transmission processing units that are provided to correspond to a plurality of transmitting antennas; and a serial-to-parallel converting unit that performs space-time encoding on input data and generates parallel data to correspond to the plurality of transmission processing units, wherein each of the transmission processing units includes a real component processor that performs orthogonal encoding on a real component of corresponding data among the parallel data generated by the serial- to-parallel converting unit, an imaginary component processor that performs orthogonal encoding on an imaginary component of corresponding data among the parallel data generated by the serial-to-parallel converting unit, and a synthesizer that synthesizes data output from the real component processor and the imaginary component processor to transmit the synthesized data through a corresponding transmitting antenna.

[2] The transmitting apparatus of claim 1, wherein: the real component processor includes a first mapper that generates the real component as a non-binary signal value and outputs the non-binary signal value, a first orthogonal encoding unit that multiplies the non-binary signal value by an orthogonal code, and a first unique spreading code synthesizer that multiplies a signal output by the first orthogonal encoding unit by a unique spreading code; and the imaginary component processor includes a second mapper that generates the imaginary component as a non-binary signal value and outputs the non-binary signal value, a second orthogonal encoding unit that multiplies the non-binary signal value output from the second mapper by an orthogonal code, and a second unique spreading code synthesizer that multiplies a signal output by the second orthogonal encoding unit by a unique spreading code.

[3] The transmitting apparatus of claim 2, wherein: the real component processor further includes a first multiplier that multiplies a signal output by the first unique spreading code synthesizer by a high frequency received from the outside of the transmitting apparatus and modulates the signal; and the imaginary component processor further includes a second multiplier that multiplies a signal output from the second unique spreading code synthesizer by a high frequency received from the outside of the transmitting apparatus and modulates the signal.

[4] The transmitting apparatus of claim 2, wherein: the first orthogonal encoding unit includes a first serial-to-parallel converter that converts the non-binary signal output from the first mapper into a parallel signal, first orthogonal code converters that multiply components of the parallel signal output by the first serial-to-parallel converter by corresponding orthogonal codes, and a first adder that adds values output by the first orthogonal code converters; and the second orthogonal encoding unit includes a second serial-to-parallel converter that converts the non-binary signal output from the second mapper into a parallel signal, second orthogonal code converters that multiply components of the parallel signal output by the second serial-to-parallel converter by corresponding orthogonal codes, and a second adder that adds values output by the second orthogonal code converters.

[5] A receiving apparatus of a multiple transmitting and receiving system, the receiving apparatus comprising: a plurality of reception processing units that are provided to correspond to a plurality of receiving antennas; and a parallel-to-serial converting unit that converts parallel data received from the plurality of reception processing units into serial data, wherein each of the reception processing units includes a real component processor that restores a real component of data received through a corresponding receiving antenna, and an imaginary component processor that restores an imaginary component of data received through a corresponding receiving antenna.

[6] The receiving apparatus of claim 5, wherein: the real component processor includes a first low pass filter that removes a high frequency component from the real component of the received data, a first unique spreading code multiplier that multiplies signals output from the first low pass filter by a unique spreading code, a first inverse orthogonal encoding unit that multiplies values output by the first unique spreading code multiplier by corresponding orthogonal codes, integrates the values, and outputs the integrated values, and a first inverse mapper that divides the values integrated by the first inverse orthogonal encoding unit by using non-binary signals and restores original signals; and the imaginary component processor includes a second low pass filter that removes a high frequency component from the imaginary component of the received data, a second unique spreading code multiplier that multiplies signals output by the second low pass filter by a unique spreading code, a second inverse orthogonal encoding unit that multiplies values output by the second unique spreading code multiplier by corresponding orthogonal codes, integrates the values, and outputs the integrated values, and a second inverse mapper that divides the values integrated by the second inverse orthogonal encoding unit by using non-binary signals and restores original signals.

[7] The receiving apparatus of claim 6, wherein: the first inverse orthogonal encoding unit includes first orthogonal code converters, each of which multiplies the synthesized signal output by the first unique spreading code synthesizer by an orthogonal code, integrators, each of which integrates a value output by each of the first orthogonal code converters for every predetermined period on the basis of one period of the unique spreading code, and a first parallel-to-serial converter that converts output values of the integrators into serial data; and the second inverse orthogonal encoding unit includes second orthogonal code converters, each of which multiplies the synthesized signal output by the second unique spreading code synthesizer by an orthogonal code, integrators, each of which integrates a value output by each of the second orthogonal code converters for every predetermined period on the basis of one period of the unique spreading code, and a second parallel-to-serial converter that converts output values of the integrators into serial data.

[8] A method of transmitting data in a multiple transmitting and receiving system, the method comprising: performing space-time encoding on input data and generating parallel data to be processed in a plurality of transmission processing units; performing orthogonal encoding on a real component of corresponding data among the parallel data in the plurality of transmission processing units; performing orthogonal encoding on an imaginary component of corresponding data among the parallel data in the plurality of transmission processing units; and synthesizing the real component and the imaginary component on which the orthogonal encoding have been performed.

[9] The method of claim 8, wherein: the performing of the orthogonal encoding on the real component includes generating the real component as a first non-binary signal value, multiplying the first non-binary signal value by an orthogonal code, multiplying the first non-binary signal value, which has been multiplied by the orthogonal code, by a unique spreading code, and multiplying the first non-binary signal value, which has been multiplied by the unique spreading code, by a high frequency, and generating modulated data; and the performing of the orthogonal encoding on the imaginary component includes generating the imaginary component as a second non-binary signal value, multiplying the second non-binary signal value by an orthogonal code, multiplying the second non-binary signal value, which has been multiplied by the orthogonal code, by a unique spreading code, and multiplying the second non-binary signal value, which has been multiplied by the unique spreading code, by a high frequency, and generating modulated data.

[10] The method of claim 9, wherein: the multiplying of the first non-binary signal value by the orthogonal code includes converting the first non-binary signal value into parallel data, multiplying elements of the first non-binary signal value, which has been converted into the parallel data, by corresponding orthogonal codes, and adding the elements of the first non-binary signal value that have been multiplied by the orthogonal codes; and the multiplying of the second non-binary signal value by the orthogonal code includes converting the second non-binary signal value into parallel data, multiplying elements of the second non-binary signal value, which have been converted into the parallel data, by corresponding orthogonal codes, and adding the elements of the second non-binary signal value that have been multiplied by the orthogonal codes.