WO2008076896A3 - Configurable cache for a microprocessor - Google Patents

Configurable cache for a microprocessor Download PDF

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Publication number
WO2008076896A3
WO2008076896A3 PCT/US2007/087600 US2007087600W WO2008076896A3 WO 2008076896 A3 WO2008076896 A3 WO 2008076896A3 US 2007087600 W US2007087600 W US 2007087600W WO 2008076896 A3 WO2008076896 A3 WO 2008076896A3
Authority
WO
WIPO (PCT)
Prior art keywords
cache
memory
microprocessor
control unit
issued
Prior art date
Application number
PCT/US2007/087600
Other languages
French (fr)
Other versions
WO2008076896A2 (en
Inventor
Rodney J Pesavento
Gregg D Lahti
Joseph W Triece
Original Assignee
Microchip Tech Inc
Rodney J Pesavento
Gregg D Lahti
Joseph W Triece
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Tech Inc, Rodney J Pesavento, Gregg D Lahti, Joseph W Triece filed Critical Microchip Tech Inc
Priority to CN200780046003.7A priority Critical patent/CN101558393B/en
Priority to KR1020097014666A priority patent/KR101363585B1/en
Priority to EP07869282A priority patent/EP2095243B1/en
Publication of WO2008076896A2 publication Critical patent/WO2008076896A2/en
Publication of WO2008076896A3 publication Critical patent/WO2008076896A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Abstract

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.
PCT/US2007/087600 2006-12-15 2007-12-14 Configurable cache for a microprocessor WO2008076896A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200780046003.7A CN101558393B (en) 2006-12-15 2007-12-14 Configurable cache for a microprocessor
KR1020097014666A KR101363585B1 (en) 2006-12-15 2007-12-14 Configurable cache for a microprocessor
EP07869282A EP2095243B1 (en) 2006-12-15 2007-12-14 Configurable cache for a microprocessor

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US87018806P 2006-12-15 2006-12-15
US60/870,188 2006-12-15
US87062206P 2006-12-19 2006-12-19
US60/870,622 2006-12-19
US11/928,322 2007-10-30
US11/928,322 US7966457B2 (en) 2006-12-15 2007-10-30 Configurable cache for a microprocessor

Publications (2)

Publication Number Publication Date
WO2008076896A2 WO2008076896A2 (en) 2008-06-26
WO2008076896A3 true WO2008076896A3 (en) 2008-08-07

Family

ID=39345378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/087600 WO2008076896A2 (en) 2006-12-15 2007-12-14 Configurable cache for a microprocessor

Country Status (5)

Country Link
US (1) US7966457B2 (en)
EP (1) EP2095243B1 (en)
KR (1) KR101363585B1 (en)
TW (1) TWI456390B (en)
WO (1) WO2008076896A2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571287B2 (en) 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
US9208095B2 (en) 2006-12-15 2015-12-08 Microchip Technology Incorporated Configurable cache for a microprocessor
US7877537B2 (en) * 2006-12-15 2011-01-25 Microchip Technology Incorporated Configurable cache for a microprocessor
US8127104B1 (en) 2007-08-06 2012-02-28 Marvell International Ltd. Alignment matrix memory copy
US8688947B1 (en) 2007-11-21 2014-04-01 Marvell International Ltd. Aligned data access
US8131915B1 (en) 2008-04-11 2012-03-06 Marvell Intentional Ltd. Modifying or overwriting data stored in flash memory
US8683085B1 (en) 2008-05-06 2014-03-25 Marvell International Ltd. USB interface configurable for host or device mode
US8423710B1 (en) 2009-03-23 2013-04-16 Marvell International Ltd. Sequential writes to flash memory
US8213236B1 (en) 2009-04-21 2012-07-03 Marvell International Ltd. Flash memory
US8489814B2 (en) * 2009-06-23 2013-07-16 Mediatek, Inc. Cache controller, method for controlling the cache controller, and computing system comprising the same
US8412971B2 (en) 2010-05-11 2013-04-02 Advanced Micro Devices, Inc. Method and apparatus for cache control
US8756394B1 (en) 2010-07-07 2014-06-17 Marvell International Ltd. Multi-dimension memory timing tuner
CN103003805B (en) 2010-07-16 2016-01-20 株式会社东芝 The customization of bus adapter card
US20140181402A1 (en) * 2012-12-21 2014-06-26 Advanced Micro Devices, Inc. Selective cache memory write-back and replacement policies
WO2016012833A1 (en) * 2014-07-21 2016-01-28 Elliptic Technologies Inc. Pre-loading cache lines
US11200166B2 (en) 2019-07-31 2021-12-14 Micron Technology, Inc. Data defined caches for speculative and normal executions
US11194582B2 (en) 2019-07-31 2021-12-07 Micron Technology, Inc. Cache systems for main and speculative threads of processors
US11010288B2 (en) 2019-07-31 2021-05-18 Micron Technology, Inc. Spare cache set to accelerate speculative execution, wherein the spare cache set, allocated when transitioning from non-speculative execution to speculative execution, is reserved during previous transitioning from the non-speculative execution to the speculative execution
US11048636B2 (en) * 2019-07-31 2021-06-29 Micron Technology, Inc. Cache with set associativity having data defined cache sets
CN117076699B (en) * 2023-10-13 2023-12-12 南京奥看信息科技有限公司 Multi-picture acceleration processing method and device and electronic equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057675A1 (en) * 2000-02-02 2001-08-09 Sony Electronics Inc. System and method for effectively utilizing a cache memory in an electronic device
US20030070047A1 (en) * 2001-10-09 2003-04-10 Harry Dwyer Method and apparatus for adaptive cache frame locking and unlocking

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5197139A (en) 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5655096A (en) 1990-10-12 1997-08-05 Branigin; Michael H. Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution
US5353425A (en) 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
EP0795820B1 (en) 1993-01-21 2000-03-01 Advanced Micro Devices Inc. Combined prefetch buffer and instructions cache memory system and method for providing instructions to a central processing unit utilizing said system.
US5887152A (en) 1995-04-12 1999-03-23 Advanced Micro Devices, Inc. Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
US5848433A (en) 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5761712A (en) 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US6341347B1 (en) 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US6532520B1 (en) * 1999-09-10 2003-03-11 International Business Machines Corporation Method and apparatus for allocating data and instructions within a shared cache
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6480938B2 (en) * 2000-12-15 2002-11-12 Hewlett-Packard Company Efficient I-cache structure to support instructions crossing line boundaries
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US6931494B2 (en) * 2002-09-09 2005-08-16 Broadcom Corporation System and method for directional prefetching
KR20060130120A (en) 2004-03-24 2006-12-18 마쯔시다덴기산교 가부시키가이샤 Cache memory and control method thereof
US7386679B2 (en) * 2004-04-15 2008-06-10 International Business Machines Corporation System, method and storage medium for memory management
US20060179174A1 (en) 2005-02-02 2006-08-10 Bockhaus John W Method and system for preventing cache lines from being flushed until data stored therein is used
US8090934B2 (en) * 2006-07-11 2012-01-03 Cetin Kaya Koc Systems and methods for providing security for computer systems
US7877537B2 (en) 2006-12-15 2011-01-25 Microchip Technology Incorporated Configurable cache for a microprocessor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057675A1 (en) * 2000-02-02 2001-08-09 Sony Electronics Inc. System and method for effectively utilizing a cache memory in an electronic device
US20030070047A1 (en) * 2001-10-09 2003-04-10 Harry Dwyer Method and apparatus for adaptive cache frame locking and unlocking

Also Published As

Publication number Publication date
US7966457B2 (en) 2011-06-21
EP2095243A2 (en) 2009-09-02
TWI456390B (en) 2014-10-11
WO2008076896A2 (en) 2008-06-26
EP2095243B1 (en) 2012-11-14
KR101363585B1 (en) 2014-02-13
US20080147978A1 (en) 2008-06-19
KR20090105928A (en) 2009-10-07
TW200834309A (en) 2008-08-16

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