WO2008078146A1

WO2008078146A1 - Data transfer

Info

Publication number: WO2008078146A1
Application number: PCT/IB2006/004201
Authority: WO
Inventors: Anssi Haverinen; Ketil Julsgaard; Tea Seppa
Original assignee: Nokia Corporation
Priority date: 2006-12-27
Filing date: 2006-12-27
Publication date: 2008-07-03

Abstract

A method, comprising: initiating data transfer by applying, on a first bus, an indication of direction of data transfer; applying, on a second bus, a first data address; applying, on the second bus, first data associated with the first data address; continuing the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and applying, on the second bus, second data associated with the second data address.

Description

TITLE

Data Transfer

FIELD OF THE INVENTION

Embodiments of the present invention relate to data transfer. Some embodiments relate to a method and apparatus for data transfer using an Open Chip Protocol (OCP) compliant bus arrangement.

BACKGROUND TO THE INVENTION

The OCP is a socket interface specification that defines a protocol for integrated circuits (chips) to communicate with each other.

Using the definitions made in the OCP, an integrated circuit may read from or write to another integrated circuit. For example, a microprocessor chip may read from or write to a cellular modem chip.

A temporal schematic of write transactions using the OCP is illustrated in Fig. 1. A RequestCommandBus 100, a AddressDataBus 200 and a ResponseStatusBus 300 electrically connect a first integrated circuit to a second integrated circuit. In this implementation, the first integrated circuit is a master and the second integrated circuit is a slave. The slave and the master operate using a common clock source.

At rising clock edge 1 , the master begins a first write transaction by setting a first write command wn on the RequestCommandBus 100 and by setting a first absolute address Ai on the AddressDataBus 20.

At rising clock edge 2, the master changes the state of the RequestCommandBus 100 to Idle and sets data D₁ on the AddressDataBus 200 to be written to the first address A-|. Also, at rising clock edge 2, the slave accepts and acknowledges the first write command wn by setting a data valid indication Dvai on the ResponseStatusBus 300.

At rising clock edge 3, the master begins a second write transaction by setting a second write command wr₂ on the RequestCommandBus 100 and by setting a second address A₂ on the AddressDataBus 200. The second write command wr₂ has the same form as the first write command Wr₁. The second address A₂ is an absolute address having the same data word size as the first address A-i. The second write transaction then continues in the same manner as the first write transaction.

Fig. 2 illustrates a temporal schematic of read transactions using the OCP. As in Fig. 1 , a RequestCommandBus 100, a AddressDataBus 200 and a ResponseStatusBus 300 electrically connect a first integrated circuit to a second integrated circuit. The first integrated circuit is a master and the second integrated circuit is a slave. The slave and the master operate using a common clock source.

At rising clock edge 1 , the master begins a read transaction by setting a first read command rdi on the RequestCommandBus 100 and by setting a first address Ai on the AddressDataBus 200.

At rising clock edge 2, the master changes the state of the RequestCommandBus 100 to Idle and sets the AddressDataBus 200 to a high impedance state. The direction of the AddressDataBus 200 is turned from the master to slave direction to the slave to master direction.

At rising clock edge 3, the slave sets first data D₁ on the AddressDataBus 200 that corresponds to the first address A₁. The slave accepts and acknowledges the first read command Td₁ by setting a data valid indication Dva-i on the ResponseStatusBus 300. At rising clock edge 4, the slave sets the AddressDataBus 200 to a high- impedance state and sets the ResponseStatusBus 300 to Null. The AddressStatusBus 200 is turned around from the slave to master direction to the master to slave direction.

At rising clock edge 5, the master starts a second read transaction by setting a second read command rd₂ on the RequestCommandBus 100 and by setting a second address A₂ on the AddressDataBus 200. The second address A₂ is an absolute address having the same data word size as the first address Ai. The second read transaction then continues in the same manner as the first read transaction.

BRIEF DESCRIPTION OF THE INVENTION

According to one embodiment of the invention, there is provided a method, comprising: initiating data transfer by applying, on a first bus, an indication of direction of data transfer; applying, on a second bus, a first data address; applying, on the second bus, first data associated with the first data address; continuing the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and applying, on the second bus, second data associated with the second data address.

According to another embodiment of the invention, there is provided a method, comprising: initiating data transfer by applying, on a first bus, a indication of direction of data transfer; applying, on a second bus, a first data address; detecting, on the second bus, first data associated with the first data address; continuing the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and detecting, on the second bus, second data associated with the second data address. According to a further embodiment of the invention, there is provided a method, comprising: detecting, on a first bus, a indication of direction of data transfer to initiate data transfer; detecting, on a second bus, a first data address; detecting, on the second bus, first data associated with the first data address; continuing the data transfer by detecting, on the first bus, an indication of a second data address as a variation from the first data address; and detecting, on the second bus, second data associated with the second data address.

According to another embodiment of the invention there is provided, a method, comprising: detecting, on a first bus, a indication of direction of data transfer to initiate data transfer; detecting, on a second bus, a first data address; applying, on the second bus, first data associated with the first data address; continuing the data transfer by detecting, on the first bus, an indication of a second data address as a variation from the first data address; and applying, on the second bus, second data associated with the second data address.

According to a further embodiment of the invention, there is provided an apparatus, comprising: a data transfer controller operable to apply, on a first bus, an indication of direction of data transfer; an address controller operable to apply, on a second bus, a first data address; a data controller operable to apply, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to apply, on the second bus, second data associated with the second data address.

According to a further embodiment of the invention, there is provided an apparatus, comprising: a data transfer controller operable to apply, on a first bus, a indication of direction of data transfer; an address controller operable to apply, on a second bus, a first data address; a data controller operable to detect, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by applying, on the first bus, an indication of a second data address as a variation of the first data address; and the data controller is operable to detect, on the second bus, second data associated with the second data address.

According to another embodiment of the invention, there is provided an apparatus, comprising: a data transfer controller operable to detect, on a first bus, an indication of direction of data transfer; an address controller operable to detect, on a second bus, a first data address; a data controller operable to detect, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by detecting, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to detect, on the second bus, second data associated with the second data address.

According to a further embodiment of the invention, there is provided an apparatus, comprising: a data transfer controller operable to detect, on a first bus, an indication of direction of data transfer; an address controller operable to detect, on a second bus, a first data address; a data controller operable to apply, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by detecting, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to apply, on the second bus, second data associated with the second data address.

According to another embodiment of the invention, there is provided a method, comprising: initiating data transfer by applying, via a first bus, an indication of direction of data transfer; communicating, via a second bus having a data width larger than the first bus, a first data address; communicating, via the second bus, first data associated with first data address; continuing the data transfer by communicating, via the first bus, an indication of a second data address by indicating a variation from the first data address; and communicating, via the second bus, second data associated with the second data address.

According to a further embodiment of the invention, there is provided an apparatus, comprising: a data transfer controller operable to communicate, via a first bus, an indication of direction of data transfer; an address controller operable to communicate, via a second bus having a data width larger than the first data bus, a first data address; a data controller operable to communicate, via the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by communicating, via the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to communicate, via the second bus, second data associated with the second data address.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention reference will now be made by way of example only to the accompanying drawings in which:

Fig. 1 illustrates a temporal schematic of prior art write transactions according to the OCP;

Fig. 2 illustrates a temporal schematic of prior art read transactions according to the OCP;

Fig. 3 illustrates a schematic of an apparatus; Fig. 4 illustrates a schematic of the apparatus connected to a further apparatus via a RequestCommandBus, an AddressDataBus and a ResponseStatusBus;

Fig. 5 illustrates a temporal schematic of a write burst transaction;

Fig. 6 illustrates a temporal schematic of a first read burst transaction; and

Fig. 7 illustrates a temporal schematic of a second read burst transaction.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The Figures illustrate a method, comprising: initiating data transfer by applying, on a first bus 100, an indication wr/rd of direction of data transfer; applying, on a second bus 200, a first data address Ai; applying, on the second bus 200, first data Di associated with first data address A-i; continuing the data transfer by applying, on the first bus 100, an indication incri of a second data address A₂ by indicating a variation from the first data address A-i ; and applying, on the second bus 200, second data D₂ associated with the second data address A₂.

Fig. 3 illustrates a schematic of the functional modules of an apparatus 10. The apparatus 10 may be an integrated circuit, a portion of an integrated circuit or a plurality of integrated circuits (i.e. a chipset). For example, it may be a software programmable processor. Alternatively, it may be an application specific integrated circuit (ASIC), such as a cellular modem chip.

The apparatus 10 comprises the following functional modules: a data transfer controller 12, an address controller 14, a data controller 16, an acknowledgement controller 18 and a switching arrangement 20. The apparatus 10 has been illustrated as comprising these functional modules for ease of explanation only. It will be appreciated by the skilled person that the arrangement of functional modules illustrated in Fig. 3 represents only one way of implementing embodiments of the invention. The functional modules 12 to 20 are not necessarily different physical parts of the apparatus 10. For example, where the apparatus is a software programmable processor, the functions of each of modules may be carried out using software.

The data transfer controller 12 is connected to receive an input from and to provide an input to: the address controller 14, the data controller 16 and the acknowledgement controller 18. The data transfer controller 12 is also connected to provide an output to the switching arrangement 20.

Fig. 4 illustrates a system 1000 comprising an apparatus 10 electrically connected to a further apparatus 10'. The apparatus 10 is a master and the further apparatus 10' is a slave.

Operation of master 10

The data transfer controller 12 includes a latching circuit 11 for latching a voltage onto the RequestCommandBus 100. The address controller 14 includes a latching circuit 13 for latching a voltage onto the AddressDataBus 200 when the switching arrangement 20 is at position X. The data controller 16 includes a latching circuit 15 for latching a voltage onto the AddressDataBus 200 when the switching arrangement 20 is at position Y. The data controller 16 includes a detection circuit 17 for detecting a voltage on the AddressDataBus 200 when the switching arrangement 20 is at position Y. The acknowledgement controller 18 may include a detection circuit 19 for detecting a voltage on the ResponseStatusBus 300.

Operation of slave 10'

The data transfer controller 12 includes a detection circuit 111 for detecting a voltage on the RequestCommandBus 100. The Address Controller 14 includes a detection circuit 113 for detecting a voltage on the AddressDataBus 200 when the switching arrangement 20 is at position X. The data controller 16 includes a latching circuit 115 for latching a voltage onto the AddressDataBus 200 when the switching arrangement 20 is at position Y. The data controller 16 includes a detection circuit 117 for detecting a voltage on the AddressDataBus 200 when the switching arrangement 20 is at position Y. The acknowledgement controller 18 may include a latching circuit 119 for latching a voltage onto the ResponseStatusBus 300.

In the example illustrated in Fig. 4, the master data transfer controller 12 is connected to receive an input from and to provide an output to a central processor core 70. The central processor core 70 and the apparatus 10 may be different portions of the same integrated circuit or different integrated circuits. The central processor core 70 may, for example, handle most of the data processing tasks in an electronic device such as a mobile telephone.

The slave data transfer controller 12' is connected to receive an input from and to provide an output to chip core 80 which is, in this example, a cellular modem chip core. The cellular modem chip core 80 and the further apparatus 10' may be different portions of the same integrated circuit or different integrated circuits. A cellular modem chip core 80 may handle data processing tasks relating to a bi-directional connection to a cellular telephone network.

The master data transfer controller 12 is connected to the slave data transfer controller 12' via the RequestCommandBus 100. The RequestCommandBus 100 has a width of two bits (i.e. it may consist of two command lines) or more bits.

The master address controller 14 is connected to the slave address controller 14' via the AddressDataBus 200 when the master switching arrangement 20 and the slave switching arrangement 20' are both at position X. The master data controller 16 is connected to the slave data controller 16 via the AddressDataBus 200 when the master switching arrangement 20 and the slave switching arrangement 20' are both at position Y.

The width of the AddressDataBus 200 in bits may be a power of two and may be, for example, 4, 8, 16, 32 or 64 bits.

The master acknowledgement controller 18 is connected to the slave acknowledgement controller via the ResponseStatusBus 300. The ResponseStatusBus 300 may be, for example, a single command line.

The master 10 and the slave 10' communicate on the RequestCommandBus 100, the AddressDataBus 200 and the ResponseStatusBus 300 using a common clock source or synchronized clock sources.

It will be apparent to the skilled person that the terms "applying" and "setting" have been used interchangeably in the present specification in relation to the application of signals on the RequestCommandBus 100, the AddressDataBus 200 and the ResponseStatusBus 300.

Fig. 5 illustrates a temporal schematic of a write burst transaction according to embodiments of the invention. Initially, the master data transfer controller 12 receives first data Di and a first absolute address Ai from the central processor core 70. The first data Di is to be written to the first address A-i. The master data transfer controller 12 sets the master switching arrangement 20 to point X, so that the address controller 14 is connected to the AddressDataBus 200.

At rising clock edge 1 in Fig. 5, the master data transfer controller 12 initiates data transfer by setting a write command wr on the RequestCommandBus 100 and controls the master address controller 14 to set the first address Ai on the AddressDataBus 200.

In response to detecting the write command wr, the slave data transfer controller 12' sets the slave switching arrangement 20' to point X, enabling the slave address controller 14' to detect the first address A-i.

The slave address controller 14 detects the first address Ai and communicates it to the slave data transfer controller 12'. The slave data transfer controller 12 communicates the first address Ai to the cellular modem chip core 80. In response to detecting the first address A-i, the slave data transfer controller 12' sets the slave switching arrangement 20' to point Y so that the slave data controller 16' is connected to the AddressDataBus 200.

The master data transfer controller 12 then receives second data D₂ from the central processor core 70. At rising clock edge 2, the master data transfer controller 12 continues the data transfer by setting a first increment command incri on the RequestCommandBus 100.

The first increment command incri indicates to the slave data transfer controller 12' that second data D₂ is to be transferred from the master 10 to the slave 10' at a subsequent point in time. Thus, the first increment command incri indicates that the write burst transaction is to continue.

The first increment command incri also indicates to the slave data controller 12' a second address A₂ that the second data D₂ is to be written to. It indicates that the second address A₂ is equivalent to the first address Ai plus an increment. The increment may be, for example, one address unit.

The first increment command incn therefore provides the slave data transfer controller 12' with the second address A₂ as a variation from the first address Ai. In response to detecting the second address A₂, the slave data transfer controller 12' communicates an indication of the second address A₂ to the cellular modem chip core 80.

The master data transfer controller 12 sets the master switching arrangement 20 to point Y, to enable the master data controller 16 to set the first data Di onto the AddressDataBus 200. The master data transfer controller 12 controls the master data controller 16 to set the first data Di onto the AddressData Bus at rising clock edge 2.

The slave data controller 16' detects the first data D₁ and communicates it to the slave data transfer controller 12', which then communicates the first data Di to the cellular modem chip core 80.

The slave data transfer controller 12' may control the slave acknowledgement controller 18' to set a first data valid instruction Dvai on the ResponseStatusBus 300 at rising clock edge 2, in order to accept and acknowledge the write command wr of rising clock edge 1.

However, in the example illustrated in Fig. 5, the slave data transfer controller 12' is busy handling other information and is unable to control the slave acknowledgement controller 18' to set a data valid instruction Dva on the ResponseStatusBus 300. Consequently, the slave acknowledgement controller 18' holds the ResponseStatusBus 300 in Null at rising clock edge 2.

At rising clock edge 3, the master data transfer controller 12 sets a first continue command conti on the RequestCommandBus 100, which is detected by the slave data transfer controller 12'. The first continue command conti indicates to the slave that the write transaction is to continue.

The slave data transfer controller 12' controls the slave acknowledgement controller 18' to set a data valid instruction Dvai on the ResponseStatusBus 300 at rising clock edge 3. The first data valid instruction Dvai indicates to the master that the slave accepts the write command wr and acknowledges receipt of it. The master acknowledgement controller 18 detects the first data valid instruction Dvai and informs the master data transfer controller 12 that it has been detected.

The master data transfer controller 12 then receives third data D₃ from the central processor core 70. At rising clock edge 4, the master data transfer controller 12 sets a second increment command incr₂ on the RequestCommandBus 100. The second increment command incr₂ is associated with the transfer of the third data D₃. The second increment command incr₂ indicates to the slave data transfer controller 12' that third data D₃ is to be transferred to the slave 10' at a subsequent point in time. Thus, the second increment command incr₂ indicates that the write burst transaction is to continue.

The second increment command incr₂ indicates to the slave data transfer controller 12' a third address A₃ that the third data D3 is to be written to. The third address A₃ is indicated as a variation from the first address Ai or the second address A₂. For example, it may indicate that the third address A₃ is equivalent to the second address A₂ plus an increment. The increment may be, for example, one address unit. In response to detecting the second increment command incr₂, the slave data transfer controller 12' communicates an indication of the third address A₃ to the cellular modem chip core 80.

The master data transfer controller 12 also controls the master data controller 16 to set the second data D₂ on the AddressDataBus 200 at rising clock edge 4. The slave data controller 16' detects the second data D₂ and communicates it to the slave data transfer controller 12', which communicates the second data D₂ to the cellular modem chip core 80.

The slave data transfer controller 12 controls the slave acknowledgement controller 18 to set a second data valid instruction Dva₂ on the ResponseStatusBus 300 at rising clock edge 4 to accept and acknowledge receipt of the first increment command incr-i. The master acknowledgement 18 controller detects the second data valid instruction Dva₂ and informs the master data transfer controller 12 that it has been detected.

Given that the master has received a data valid instruction Dva (i.e. Dvai) relating to the first increment command incr-i, the master data transfer controller 12 may set a third increment command on the RequestCommandBus 100 at rising clock edge 5 if there is further data to transfer.

However, in the embodiment illustrated in Fig. 5, the master data transfer controller 12 has not yet received new data from the central processor core 70. The master data transfer controller 12 is informed by the central processor core 70 that, while there is no further data to transfer at rising clock edge 5, there may be new data to transfer at a later point in time.

The master data transfer controller 12 therefore sets a second continue command cont₂ on the RequestCommandBus 100, which indicates that the write burst transaction is to continue.

The master data controller 16 sets third data D₃ on the AddressDataBus 200 at rising clock edge 5. The third data D₃ is detected by the slave data controller 16' and communicated to the slave data transfer controller 12'. The slave data transfer controller 12' communicates the third data D₃ to the cellular modem chip core 80.

The slave data transfer controller 12' controls the slave acknowledgement controller 18' to set a third data valid instruction Dva₃ on the ResponseStatusBus 300 at rising clock edge 5, to accept and acknowledge receipt of the second increment command incr₂. The master acknowledgement controller 18 detects the second increment command incr₂ and informs the master data transfer controller 12.

The master data transfer controller 12 then receives fourth data D₄ from the central processor core 70. At rising clock edge 6, the master data transfer controller 12 sets a third increment command incr₃ on the

RequestCommandBus 100. The third increment command incr₃ is associated with the transfer of the fourth data D₄. The third increment command incr₃ indicates to the slave data transfer controller 12' that fourth data D₄ is to be transferred to the slave at a subsequent point in time. Thus, the third increment command incr₃ indicates that the write burst transaction is to continue.

The third increment command incr₃ indicates to the slave data transfer controller 12' the fourth address A₄ that the fourth data D₄ is to be written to.

The fourth address A₄ is indicated as a variation from the first, second or third addresses Ai, A₂ or A₃. For example, it may indicate that the fourth address

A₄ is equivalent to the third address A₃ plus an increment. The increment may be, for example, one address unit. In response to receiving the third increment command JnCr₃, the master data transfer controller 12 communicates an indication of the fourth address A₄ to the cellular modem chip core 80.

As a second continue command cont₂ was set on the RequestCommandBus 100 at rising clock edge 5, the master has no further data to transfer on AddressDataBus 200 at rising clock edge 6. In the illustrated embodiment, the master data controller 16 continues by holding the third data D₃ on the AddressDataBus 200 at rising clock edge 6. In another embodiment, the data controller 16 may cease to apply any voltage to the AddressDataBus 200 at clock edge 6. The slave acknowledgement controller 18 holds the ResponseStatusBus 300 in Null at rising clock edge 6. At this point in time, there are no commands that need to be acknowledged or accepted by the slave 10'.

At rising clock edge 7, the master data transfer controller 12 sets an idle instruction on the RequestCommandBus 100. The idle instruction indicates to the slave 10' that the write burst transaction is to end. The master data controller 16 sets the fourth data D₄ on the AddressDataBus 200 at rising clock edge 7. The fourth data D₄ is detected by the slave data controller 16' and communicated to the slave data transfer controller 12'. The slave data transfer controller 12' communicates the fourth data D₄ to the cellular modem chip core 80.

The slave data transfer controller 12 controls the slave acknowledgement controller 18' to set a fourth data valid instruction Dva₄ at rising clock edge 7, in order to accept and acknowledge receipt of the third increment command incr₃.The master acknowledgement controller 18 detects the fourth data valid instruction Dva₄ and informs the master data transfer controller 12 that it has been detected.

In the write burst transaction described above, once a first absolute address Ai is communicated by the master 10 to the slave 10' on the AddressDataBus 200, subsequent data address information is transmitted on the RequestCommandBus 100 as relative address information.

The subsequent communication of relative addresses on the RequestCommandBus 100 advantageously allows the AddressDataBus 200 to be used solely for the transfer of data, enabling embodiments of the invention to achieve a higher rate of data transfer from a master to a slave than in the prior art. Typically, the AddressDataBus 200 has a much larger width (usually 8, 16 or 32 bits) than the RequestCommandBus 100 (usually 2 bits). The use of the RequestCommandBus 100 to communicate address information means that bus resources are used more efficiently in embodiments of the invention that 5 in the prior art.

Fig. 6 illustrates a temporal schematic of a read burst transaction according to embodiments of the invention. The master data transfer controller 12 initiates data transfer by setting a read command rd on the RequestCommandBus 100 I O at rising clock edge 1. The master data transfer controller 12 also sets the master switching arrangement 20 to point X and controls the master address controller 14 to set a first address Ai on the AddressDataBus 200 at rising clock edge 1.

15 The slave data transfer controller 12' detects the read command rd and sets the slave switching arrangement 20' to point X. The slave address controller 14' detects the first address Ai and provides it to the slave data transfer controller 12'. The slave data transfer controller 12' communicates the first address Ai to the cellular modem chip core 80. The cellular modem chip core

20 80 then communicates first data D₁ corresponding to the first address Ai to the slave data transfer controller 12'.

At rising clock edge 2, the master data transfer controller 12 sets a first increment command incri on the RequestCommandBus 100. The first 25 increment command incri indicates to the slave data transfer controller 12' that second data D2 is to be transferred from the slave 10' to the master 10 at a subsequent point in time. Thus, the first increment command incri indicates that the read burst transaction is to continue.

30 The first increment command incri also indicates to the slave data transfer controller 12' a second address A2 that the second data D₂ is to be read from. It indicates that the second address A2 is equivalent to the first address Ai plus an increment. The increment may be, for example, one address unit. The first increment command incri therefore provides the slave data transfer controller 12' with the second address A₂ as a variation from the first address AL

The slave data transfer controller 12' communicates an indication of the second address A₂ to the cellular modem chip core 80. In response, the cellular modem chip core 80 provides the second data D₂ to the slave data transfer controller 12'.

The slave data transfer controller 12' sets the slave switching arrangement 20 to point Y and controls the slave data controller 16' to turn the direction of the AddressDataBus 200 around from the master to slave direction to the slave to the master direction.

At rising clock edge 3, the master data transfer controller 12 sets a second increment command incr₂ on the RequestCommandBus 100. The second increment command incr₂ is associated with the transfer of D₃. The second increment command incr₂ indicates to the slave data transfer controller 12' that third data D₃ is to be transferred to the slave 10' at a subsequent point in time. Thus, the second increment command incr₂ indicates that the read burst transaction is to continue.

The second increment command incr₃ also indicates to the slave data controller 12' a third address A₃ that the third data D₃ is to be read from. The third address A₃ is indicated as a variation from the first address Ai or the second address A₂. For example, the second increment command incr₂ may indicate that the third address A3 is equivalent to the second address A₂ plus an increment. The increment may be, for example, one address unit.

The slave data transfer controller 12' communicates an indication of the third address A₃ to the cellular modem chip core 80. In response, the cellular modem chip core 80 provides third data D₃ corresponding to the third address A₃ to the slave data transfer controller 12'.

At rising clock edge 3, the slave data transfer controller 12' also controls the slave data controller 16' to set the first data on the AddressDataBus 200. The master data controller 16 detects the second data D₂ and communicates it to the master data transfer controller 12. The master data controller 12 communicates the second data D₂ to the central processor core 70.

The slave data transfer controller 12' also controls the slave acknowledgement controller 18' at rising clock edge 3 to set a first data valid instruction Dvai on the ResponseStatusBus 300 to accept and acknowledge receipt of the read command rd. The master acknowledgement controller 18 detects the first data valid instruction Dvai and informs the master data transfer controller 12 that it has been detected.

At rising clock edge 4, the master data transfer controller 12 has not yet received any indication from the central processor core 70 that it wishes to read further data from the cellular modem chip core 80. Instead, the central processor core 70 may merely indicate to the master data transfer controller 12 that the read first transaction has not yet finished. In response, the master data transfer controller 12 sets a continue command cont on the RequestCommandBus 100, which indicates that the read first transaction is to continue.

At rising clock edge 4, the slave data transfer controller 12' controls the slave data controller 16' to set the second data D₂ on the DataAddressBus 200. The master data controller 16 detects the second data D₂ and provides it to the master data transfer controller 12. The master data transfer controller 12 provides the second data D₂ to the central processor core 70. The slave data transfer controller 12' also controls the slave acknowledgement controller 18' at rising clock edge 4 to set a second data valid instruction Dva₂ on the ResponseDataBus 200. The master acknowledgement controller 18 detects the second data valid instruction Dva₂ and informs the master data transfer controller 12 that it has been detected.

The central processor core 70 then indicates to the master data transfer controller 12 that it wishes to read fourth data D₄ from the cellular modem chip core 80.

At rising clock edge 5, the master data transfer controller 12 sets a third increment command incr₃ on the RequestCommandBus 100. The third increment command incr₃ indicates to the slave data transfer controller 12' a fourth address A₄ that the fourth data D₄ is to be written to. The fourth address A₄ is indicated as a variation from the first, second or third addresses A-i, A₂ or A₃. For example, it may indicate that the fourth address A₄ is equivalent to the third address A₃ plus an increment. The increment may be, for example, one address unit. The master data transfer controller 12 communicates an indication of the fourth address A₄ to the cellular modem chip core 80. In response, the cellular modem chip core 80 provides the fourth data D₄ to the slave data transfer controller 12'.

The slave data transfer controller 12' controls the slave data controller 16' to set the third data D₃ on the AddressDataBus 200 at rising clock edge 5. The master data controller 16 detects the third data D₃ and provides it to the master data transfer controller 12. The master data transfer controller 12 provides the third data D₃ to the central processor core 70.

The slave data transfer controller 12' also controls the slave acknowledgement controller 18' at rising clock edge 5 to set a third data valid instruction Dva₃ on the ResponseStatusBus 300. The master acknowledgement controller 18 detects the third data valid instruction Dva₃ and informs the master that it has received it.

The central processor core 70 then indicates to the master data transfer controller 12 that the read burst transaction is to end. The master data transfer controller 12 sets the RequestCommandBus 100 to idle to inform the slave that the read burst transaction is to end.

At rising clock edge 6, the slave data transfer controller 12, is busy processing information and is therefore unable to control the slave data controller 16' to set information on the AddressDataBus 200 or to control the slave acknowledgement 18' to set information on the ResponseStatusBus 300. The slave data controller 16' therefore continues to hold the third data on the AddressDataBus 200 at rising clock edge 6. In an alternative embodiment, the slave data controller 16' ceases to apply any voltage to the AddressDataBus 200 at rising clock edge 6. The slave acknowledgement controller 18' sets the ResponseStatusBus 300 to Null (i.e. it ceases to apply a voltage) at rising clock edge 6.

At rising clock edge 7, the slave data transfer controller 12' controls the slave data controller 16' to set fourth data D₄ on the AddressDataBus 200. The master data controller 16 detects the fourth data D₄ and provides it to the master data transfer controller 12. The master data transfer controller 12 provides the fourth data D₄ to the central processor core 70.

The slave data transfer controller 12' also controls the slave acknowledgement controller 18' at rising clock edge 7 to set a fourth data valid instruction Dva₄ on the ResponseStatusBus 300. The master acknowledgement controller 18 detects the data valid instruction Dva4 and informs the master data transfer controller 12 that it has been received. In the read burst transaction described above in relation to Fig. 6, once a first absolute address Ai is communicated by the master 10 to the slave 10' on the AddressDataBus 200, any subsequent data address information is transmitted on the RequestCommandBus 100 as relative address information.

The subsequent communication of relative addresses on the RequestCommandBus 100 advantageously allows the AddressDataBus 200 to be used solely for the transfer of data, enabling embodiments of the invention to achieve a higher rate of data transfer from a slave to a master than in the prior art.

Typically, the AddressDataBus 200 has a much larger width (usually 8, 16 or 32 bits) than the RequestCommandBus 100 (usually 2 bits). The use of the RequestCommandBus 100 to communicate address information means that bus resources are used more efficiently in embodiments of the invention that in the prior art.

Fig. 7 illustrates a temporal schematic of a second read burst transaction according to embodiments of the invention. The master initiates data transfer by setting a read command rd on the RequestCommandBus 100 at rising clock edge 1. The master data transfer controller 12 also sets the master switching arrangement 20 to point X and controls the master address controller 14 to set a first absolute address Ai on the AddressDataBus 200 at rising clock edge 1.

The slave data transfer controller 12' detects the read command rd and sets the slave switching arrangement 20' to position X. The slave address controller 14' detects the first address Ai and provides it to the slave data transfer controller 12'. The slave data transfer controller 12' communicates the first address Ai to the cellular chip core 80. The cellular modem chip core 80 then provides the first data Di corresponding to the first address Ai to the slave data transfer controller 12'. At rising clock edge 2, the master data transfer controller 12 continues to hold the read command rd on the RequestCommandBus 100. The master data transfer controller 12 also controls the master address controller 14 to set a header H on the AddressDataBus 200. The header H indicates the length of the read burst. The master data transfer controller 12 then sets the master switching arrangement 20 to point Y to connect the master data controller 16 to the AddressDataBus 200.

The slave address controller 14' detects the header H and communicates it to the slave data transfer controller 12'. The slave data transfer controller 12' then sets the slave switching arrangement 20' to position Y to connect the slave data controller 16 to the AddressDataBus 200. The read burst transaction then continues from rising clock edge 3 in the same manner as the read burst transaction described in relation to Fig. 6.

By identifying the length of the read burst in the header H, the master 10 enables the slave data transfer controller 12' to identify the addresses Ai to A_n that relate to the data Di to D_n to be transferred, before the slave data transfer controller 12' detects any increment commands incr.

For example, if the header H indicates that the read burst spans ten data units, Di to Dio, the slave data controller 12' can identify the addresses Ai to Aio that correspond to the data units Di to Dio . It may then request the data units D₁ to Di₀ to be communicated to it by the cellular modem chip core 80 at appropriate points in time.

In this embodiment, the increment commands incr are not the first indication that the slave 10' has of the addresses of the data to be transferred, because the addresses have already been implicitly communicated in the header H.

The subsequent communication of the increment commands serves as an indication to the slave 10' of when the master 10 wishes to detect the data units.

Although embodiments of the present invention have been described in the preceding paragraphs with reference to various examples, it should be appreciated that modifications to the examples given can be made without departing from the scope of the invention as claimed. For example, in the above examples events occur only at rising clock edges. However, events may occur at both rising and falling clock edges (double edge clocking).

The RequestCommandBus 100 is used to communicate m information items including some or all of rd, wr, incr, cont and idle. The data width of the RequestCommandBus 100 in bits may be n and, in some embodiments 2ⁿ > m. In other embodiments m > 2^π, and the information items are interpreted in context such as by using the status of a bus or buses at that time or at a preceding time.

Whilst endeavoring in the foregoing specification to draw attention to those features of the invention believed to be of particular importance it should be understood that the Applicant claims protection in respect of any patentable feature or combination of features hereinbefore referred to and/or shown in the drawings whether or not particular emphasis has been placed thereon.

I/we claim:

Claims

1. A method, comprising: initiating data transfer by applying, on a first bus, an indication of direction of data transfer; applying, on a second bus, a first data address; applying, on the second bus, first data associated with the first data address; continuing the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and applying, on the second bus, second data associated with the second data address.

2. A method as claimed in claim 1 , wherein the indication of direction of data transfer is a write command.

3. A method as claimed in claim 1 or 2, wherein the indication of direction is applied on the first bus at the same time that the first data address is applied on the second bus.

4. A method as claimed in claim 1, 2 or 3, wherein the first bus and the second bus operate using the same clock source.

5. A method as claimed in any of the preceding claims, wherein the first bus is an Open Chip Protocol (OCP) compliant RequestCommandBus and the second bus is an OCP compliant AddressDataBus.

6. A method as claimed in any of the preceding claims, further comprising detecting, on a third bus, acknowledgement data, indicating that the indication of direction of data transfer has been detected on the first bus.

7. A method as claimed in claim 6, wherein the third bus is an Open Chip Protocol (OCP) compliant ResponseStatusBus.

8. A method as claimed in claim 6 or 7, further comprising in response to detecting the acknowledgement data, applying, on the first bus, an indication of a third address by indicating a variation from the second address or the first address.

9. A method as claimed in claim 8, further comprising applying, on the second bus, third data associated with the third data address.

10. A method as claimed in claim 8 or 9, further comprising detecting, on the third bus, acknowledgement data, indicating that an indication of a variation from the first data address has been detected on the first bus.

11. A method as claimed in claim 10, further comprising in response to detecting the acknowledgement data, applying, on the first bus, an indication that the data transfer is to end.

12. A method, comprising: initiating data transfer by applying, on a first bus, a indication of direction of data transfer; applying, on a second bus, a first data address; detecting, on the second bus, first data associated with the first data address; continuing the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and detecting, on the second bus, second data associated with the second data address.

13. A method as claimed in claim 12, wherein the indication of direction of data transfer is a read command.

14. A method, comprising: detecting, on a first bus, a indication of direction of data transfer to initiate data transfer; detecting, on a second bus, a first data address; detecting, on the second bus, first data associated with the first data address; continuing the data transfer by detecting, on the first bus, an indication of a second data address as a variation from the first data address; and detecting, on the second bus, second data associated with the second data address.

15. A method as claimed in claim 14, wherein the indication of direction of data transfer is a write command.

16.A method, comprising: detecting, on a first bus, a indication of direction of data transfer to initiate data transfer; detecting, on a second bus, a first data address; applying, on the second bus, first data associated with the first data address; continuing the data transfer by detecting, on the first bus, an indication of a second data address as a variation from the first data address; and applying, on the second bus, second data associated with the second data address.

17. A method as claimed in claim 16, wherein the indication of direction of data transfer is a read command.

18.An apparatus, comprising: a data transfer controller operable to apply, on a first bus, an indication of direction of data transfer; an address controller operable to apply, on a second bus, a first data address; a data controller operable to apply, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by applying, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to apply, on the second bus, second data associated with the second data address.

19.An apparatus, comprising: a data transfer controller operable to apply, on a first bus, a indication of direction of data transfer; an address controller operable to apply, on a second bus, a first data address; a data controller operable to detect, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by applying, on the first bus, an indication of a second data address as a variation of the first data address; and the data controller is operable to detect, on the second bus, second data associated with the second data address.

20.An apparatus, comprising: a data transfer controller operable to detect, on a first bus, an indication of direction of data transfer; an address controller operable to detect, on a second bus, a first data address; a data controller operable to detect, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by detecting, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to detect, on the second bus, second data associated with the second data address.

21.An apparatus, comprising: a data transfer controller operable to detect, on a first bus, an indication of direction of data transfer; an address controller operable to detect, on a second bus, a first data address; a data controller operable to apply, on the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by detecting, on the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to apply, on the second bus, second data associated with the second data address.

22.A method, comprising: initiating data transfer by applying, via a first bus, an indication of direction of data transfer; communicating, via a second bus having a data width larger than the first bus, a first data address; communicating, via the second bus, first data associated with first data address; continuing the data transfer by communicating, via the first bus, an indication of a second data address by indicating a variation from the first data address; and communicating, via the second bus, second data associated with the second data address.

23.An apparatus, comprising: a data transfer controller operable to communicate, via a first bus, an indication of direction of data transfer; an address controller operable to communicate, via a second bus having a data width smaller than the first data bus, a first data address; a data controller operable to communicate, via the second bus, first data associated with first data address; wherein the data transfer controller is operable to continue the data transfer by communicating, via the first bus, an indication of a second data address by indicating a variation from the first data address; and the data controller is operable to communicate, via the second bus, second data associated with the second data address.

24.A method substantially as hereinbefore described with reference to and/or as shown in the accompanying drawings.

25.An apparatus substantially as hereinbefore described with reference to and/or as shown in the accompanying drawings.