WO2008088654A1

WO2008088654A1 - Nand memory with dual control gates having fixed charge layer below control gates

Info

Publication number: WO2008088654A1
Application number: PCT/US2007/088145
Authority: WO
Inventors: Henry Chien; George Matamis; Takashi Orimoto; James Kai
Original assignee: Sandisk Corporation
Priority date: 2007-01-12
Filing date: 2007-12-19
Publication date: 2008-07-24
Also published as: TW200845153A

Abstract

A string (200) of nonvolatile memory cells are connected together by source/drain regions (202-205)- that include an inversion layer created by fixed charge in an overlying layer (210-213). Control gates (220-223) extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation. Fixed charges may also be located between floating gates and the underlying substrate surface. Fixed charge over source/drain regions and under floating gates are formed together in a common deposition.

Description

NAND MEMORY WITH DUAL CONTROL GATES HAVING FIXED CHARGE LAYER BELOW CONTROL GATES

BACKGROUND OF THE INVENTION

This invention relates to nonvolatile memories and methods of forming nonvolatile memories. In particular, this application relates to nonvolatile memory arrays in which a series of floating gate memory cells are electrically connected in series.

Nonvolatile memory systems are used in various applications. Some nonvolatile memory systems are embedded in a larger system such as a personal computer. Other nonvolatile memory systems are removably connected to a host system and may be interchanged between different host systems. Examples of such removable memory systems include memory cards and USB flash drives. Electronic circuit cards, including non-volatile memory cards, have been commercially implemented according to a number of well-known standards. Memory cards are used with personal computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras, portable audio players and other host electronic devices for the storage of large amounts of data. Such cards usually contain a re-programmable non-volatile semiconductor memory cell array along with a controller that controls and supports operation of the memory cell array and interfaces with a host to which the card is connected. Several of the same type of card may be interchanged in a host card slot designed to accept that type of card. However, the development of the many electronic card standards has created different types of cards that are incompatible with each other in various degrees. A card made according to one standard is usually not useable with a host designed to operate with a card of another standard. Memory card standards include PC Card, CompactFlash™ card (CF™ card), SmartMedia™ card, MultiMediaCard (MMC™), Secure Digital (SD) card, a miniSD™ card, Subscriber Identity Module (SIM), Memory Stick™, Memory Stick Duo card and micro SD/TransFlash™ memory module standards. There are several USB flash drive products commercially available from SanDisk Corporation under its trademark "Cruzer®." USB flash drives are typically larger and shaped differently than the memory cards described above.

Different types of memory array architecture are used in nonvolatile memory systems. In one type of architecture, a NAND array, a series of strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be over driven so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.

SUMMARY OF THE INVENTION

A nonvolatile memory array according to an embodiment of the present invention comprises: a plurality of floating gate memory cells connected in series, the plurality of floating gate memory cells electrically connected by source/drain regions, a source/drain region including an inversion layer created by a fixed charge within a fixed charge layer portion that extends over the source/drain region, control gates extending between floating gates such that a control gate overlies the fixed charge layer portion.

An nonvolatile memory array according to another embodiment comprises: a plurality of memory cells connected in series to form a NAND string, each of the plurality of memory cells having a floating gate; a plurality of control gates, each of the plurality of control gates extending between adjacent floating gates; a plurality of source/drain regions that electrically connect the plurality of memory cells in series, each of the plurality of source/drain regions underlying one of the plurality of control gates; and a plurality of fixed charge layer portions, each of the plurality of fixed charge layer portions extending over one of the plurality of source/drain regions, each of the plurality of fixed charge layer portions holding a fixed electrical charge.

A method of forming a nonvolatile memory array according to an embodiment of the present invention comprises: forming a plurality of floating gates overlying a substrate surface; forming a plurality of fixed charge layer portions overlying the substrate surface, the plurality of fixed charge layer portions interspersed between the plurality of floating gates, each of the plurality of fixed charge layer portions formed having fixed electrical charge; and forming a plurality of control gates overlying the plurality of fixed charge layer portions.

A method of forming a nonvolatile memory array according to another embodiment comprises: forming a gate dielectric layer over a substrate surface; subsequently forming a plurality of floating gates overlying the gate dielectric layer; subsequently forming a plurality of fixed charge layer portions, individual fixed charge layer portions overlying the substrate surface between floating gates; forming an interlayer dielectric layer over the plurality of floating gates; and forming a plurality of control gates between floating gates.

A NAND flash memory array according to an embodiment of the present invention comprises: a plurality of floating gate memory cells connected in series by conductive source/drain regions, an individual floating gate memory cell including a floating gate and a fixed charge layer portion, the fixed charge layer portion located between the floating gate and an underlying substrate surface.

A NAND flash memory die according to an embodiment of the present invention comprises: a plurality of NAND strings formed on the die, an individual NAND string including floating gate memory cells connected together in series, an individual floating gate memory cell having a first fixed charge located between a floating gate and an underlying channel region, the first fixed charge affecting the threshold voltage of the floating gate memory cell, the floating gate memory cell having two control gates coupled to the floating gate.

A method of forming a NAND flash memory array according to an embodiment of the present invention comprises: forming a fixed charge layer that extends over a surface of a substrate; forming a plurality of floating gates overlying the fixed charge layer; and forming a plurality of conductive source/drain regions in areas of the substrate between floating gates, the source/drain regions connecting memory cells in series as a NAND string.

A method of forming a NAND flash memory according to an embodiment of the present invention comprises: forming a dielectric layer over a surface of a substrate; performing a plasma nitridation process on the dielectric layer; forming a plurality of floating gates over the nitrided dielectric layer; and forming a plurality of control gates that are individually interposed between neighboring floating gates of the plurality of floating gates.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a cross section of a NAND string having control gates located between floating gates so that two control gates couple to an individual floating gate. Figure 2 shows a cross section of a NAND string according to an embodiment of the present invention where source/drain regions include an inversion layer produced by a fixed charge in an overlying fixed charge layer.

Figure 3 shows a cross section of a NAND string according to an embodiment of the present invention at an intermediate stage of fabrication where floating gates are separated from a substrate by a tunnel oxide layer.

Figure 4 shows the NAND string of Figure 3 at a subsequent stage of fabrication after a nitridation process forms a fixed charge layer.

Figure 5 shows the NAND string of Figure 4 at a subsequent stage of fabrication after an interlayer dielectric (in this case an ONO stack) is deposited.

Figure 6 shows the NAND string of Figure 5 at a subsequent stage of fabrication after a conductive layer (in this case doped polysilicon) is deposited over the interlayer dielectric.

Figure 7 shows the NAND string of Figure 6 at a subsequent stage of fabrication after the conductive layer is etched back to remove excess conductive material, thus forming separate control gates between floating gates.

Figure 8 shows the NAND string of Figure 7 including the positive charge located in the fixed charge layer portions that lie between floating gates and the inversion layer portions formed under them.

Figure 9 shows a NAND string according to an alternative embodiment where floating gates have an inverted-T shape in cross section along the direction of the string and where source/drain regions include an inversion layer formed by charge in a fixed charge layer.

Figure 10 shows a cross section of a portion of a NAND string according to an embodiment of the present invention having a fixed charge layer extending over a substrate surface, the fixed charge layer causing an oppositely charged layer to be formed in the substrate under both floating gates and control gates.

Figure 11 shows an alternative embodiment of the present invention in which a NAND string has fixed charge under floating gates but does not have fixed charge under control gates. Figure 12 shows a cross section of a NAND string at an intermediate stage of fabrication according to an embodiment of the present invention, where a nitrided dielectric layer is formed over the surface of a substrate.

Figure 13 shows the NAND string of Figure 12 at a later stage of fabrication after conductive floating gate material is deposited and patterned using a hard mask.

Figure 14 shows the NAND string of Figure 13 at a later stage of fabrication after an interlayer dielectric layer is deposited.

Figure 15 shows the NAND string of Figure 14 at a later stage of fabrication after conductive control gate material is deposited to fill gaps between remaining floating gate material.

Figure 16 shows the NAND string of Figure 15 at a later stage of fabrication after the conductive control gate material is etched back to leave control gates in gaps between floating gates.

Figure 17 shows a cross section of a NAND string that includes floating gates having an inverted-T shape in cross section along the string direction.

Figure 18 shows a cross section of an alternative NAND string with control gates over floating gates.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

Figure 1 shows a cross section of a NAND flash memory string 100 that has control gates 81-84 extending on both sides of floating gates 33-35 (this type of array is sometimes referred to as ENAND). Examples of such strings and methods of forming them are described in U.S. Patent No. 6,888,755. In string 100 of Figure 1 a floating gate is coupled to two control gates, one on either side of the control gate (e.g. floating gate 34 is coupled to control gates 82 and 83). This is in contrast to a common memory design where a control gate overlies a floating gate so that each floating gate is coupled to only one control gate. A memory string such as that of Figure 1 may be formed as part of a memory array having many strings. Neighboring strings may be isolated from each other by Shallow Trench Isolation (STI) structures, or other means (not shown in Figure 1). In some cases, individual stings may have 8, 16, 32 or more memory cells connected together in series. Select gates 45, 51 are provided at either end of string 100 and are connected to select lines 80, 85 to allow string 100 to be connected to circuits used for accessing the memory cells of string 100. Floating gates 33-35 are separated from substrate 77 by a gate dielectric (tunnel oxide) layer 91 overlying substrate surface 79.

In string 100 of Figure 1, source/drain regions 57, 62, 67, 72, 105, 106 are provided in substrate 77 on either side of floating gates. Source/drain regions 57, 62, 67, 72, 105, 106 are shared by neighboring memory cells and provide an electrically conductive pathway between memory cells so that the memory cells in string 100 may be connected in series. Source/drain regions 57, 62, 67, 72, 105, 106 of Figure 1 are formed by implantation using floating gates 33-35 and select gates 45, 51 to provide a mask so that source/drain regions 57, 62, 67, 72, 105, 106 are self-aligned to floating gates 33-35 and select gates 45, 51. Control gates 81-84 are then formed by depositing a conductive layer (e.g. doped polysilicon) and removing the conductive material where it overlies floating gates 33-35 and select gates 45, 51 so that conductive material remains between floating gates 33-35. Thus, control gates 81-84 may be considered to be self-aligned to floating gates 33-35. Control gates 81-84 are separated from floating gates 33-35 by an interlayer dielectric layer 103. Control gates 81-84 extend in the direction perpendicular to the cross section shown and control gates of neighboring strings are connected together as word lines. Thus, a word line is a conductive element that extends through multiple strings and forms control gates where it couples to floating gates of individual strings. A control gate may couple to the underlying substrate to form a transistor where it overlies a source/drain region. By biasing a control gate a source/drain region may be made more conductive or less conductive. Thus, the source/drain region in a memory of this type (having a control gate close to the substrate, not just overlying the floating gate) may be considered as the channel of a transistor that has the control gate as its gate. In some cases, control gate bias may be sufficient to create an inversion layer that acts as a conductive source/drain region without requiring a source/drain implant.

When an architecture such as that of Figure 1 is scaled to small dimensions (e.g. gate length less than 45nanometers) certain device characteristics may be negatively impacted. Problems encountered as a result of diminished channel length may be referred to as "short channel effects." Short channel effects may be caused by implanted dopant in a source/drain region reducing the effective gate length and causing variation in effective gate length. This problem may be mitigated by reducing the amount of dopant implanted. However, less dopant results in higher resistivity and thus higher source/drain resistance, which is generally undesirable. Reduction in post implant anneal thermal cycle may also help to mitigate the problem, but does not generally eliminate short channel effects.

Figure 2 shows a cross section of a NAND string 200 according to an embodiment of the present invention in which source/drain regions 202-205 are not formed by implanting dopants, but by causing an inversion layer to be formed in substrate 208. An inversion layer is formed near a semiconductor surface when an electrical charge is in close proximity, the electrical charge drawing charge carriers to the surface where they form a conductive layer. Such an electrical charge may cause a flat band voltage shift and inverts the surface. A fixed interface charge may induce enough band bending to invert the surface to form a conduction channel. In Figure 2, fixed charge layer portions 210-213 (having positive charge) are present on both sides of floating gates 216-218. Each of fixed charge layer portions 210-213 contains a fixed amount of positive electrical charge. The positively charged fixed charge layer portions 210-213 cause negatively charged electrons to be drawn to portions of substrate 208 underlying the fixed charge layer portions 210-213. There, the electrons form an inversion layer (source/drain regions 202-205) within the P-well (P-doped portion of substrate 208). An inversion layer formed in this manner will form a conduction channel between two floating gates. Since the conduction channel is formed without a metallurgical junction, the floating gate transistor will not experience short channel effects from the source/drain regions as may be experienced when dopants are implanted to form source/drain regions. As in Figure 1, control gates 220-223 overlie source/drain regions 202-205 and source/drain regions 202-205 act as channels of transistors having control gates 220-223 as their gates. Unlike the example of Figure 1, here such channels are not formed by dopant that is implanted in a substrate. Instead a channel is formed by charge carriers in an inversion layer caused by fixed charge. Such a channel may be referred to as a "virtual channel."

While the example of Figure 2 shows positively charged fixed charge layer portions 210-213 (and hence negative charge in the inversion layer of source/drain regions 202-205), in other examples negatively-charged fixed charge layer portions may be provided causing positive charge carriers to form an inversion layer in an N-doped portion of a substrate. While the example of Figure 2 shows source/drain regions 202-205 being formed without source/drain implants, in other examples source/drain regions may be formed by a combination of implantation and an inversion layer. In this manner a lower implant dose may be used without resulting in an excessively high source/drain resistance. In general, the resistance of a source/drain region depends on any dopant in the region, any electrical field caused by fixed charge as described above and any electrical field caused by biasing an overlying control gate.

Fixed charge layers may be formed in a variety of ways using a variety of materials. Materials may include Hf-rich Hafnium oxide, Zr-rich Zirconium oxide, Silicon nitride, nitrided Silicon dioxide or some combination of these or other materials. Fixed charge layers may be formed by plasma deposition, plasma nitrification, plasma oxidation, chemical vapor deposition, atomic layer deposition, rapid thermal processing, ion implantation or other techniques. A fixed charge layer may contain charge as-deposited or may have charge added after deposition (such as by plasma processing). In some cases, a fixed charge layer has charge as-deposited and subsequently has additional charge added. In one example, nitridation of a Silicon dioxide surface results in a nidrided Silicon dioxide that contains positive charge. A fixed charge layer may result where surface states are created on a substrate by a process such as a plasma deposition process.

A fixed charge layer may be patterned in some manner so that fixed charge layer portions remain only where an inversion layer is to be formed. Alternatively, a fixed charge layer may be deposited as a blanket layer over a substrate having floating gates already formed. Where the fixed charge layer is on or close to the substrate surface (between floating gates) fixed charge layer portions cause inversion layer portions to be formed at these locations. Where such a fixed charge layer overlies a floating gate it has little effect and may be left in place. In this way, inversion layer portions are formed in the substrate in a manner that is self-aligned to the floating gates, since they are only formed where the fixed charge layer is in close proximity to the substrate surface. In some cases, a fixed charge layer may be deposited directly on a substrate surface, while in other cases a layer of Silicon dioxide or other material may lie between the substrate surface and the fixed charge layer.

Figures 3-8 show the formation of a NAND memory string 300 having control gates between floating gates and having a virtual channel according to an embodiment of the present invention. Figure 3 shows a cross section of NAND string 300 at an intermediate stage in a fabrication process. A substrate 330 has a surface 332 covered by a dielectric layer 334 (in this case Silicon dioxide). Dielectric layer 334 may be formed by oxidation, chemical vapor deposition or in some other manner. Floating gates 336-339 are located on dielectric layer 334 so that dielectric layer 334 forms a gate dielectric (tunnel oxide) layer to allow electron tunneling from substrate 330 into the floating gates 336-339 under certain conditions. Gate dielectric layer 334 also extends across substrate surface 332 between floating gates 336- 339. Floating gates 336-339 are covered by hardmask elements 342-345 (Silicon nitride in this example). Hardmask elements 342-345 are used to define floating gates 336-339 during an etch process. Hardmask elements 342-345 may be formed by lithographic patterning to have a width equal to the minimum feature size of the patterning process or may be formed using sidewall spacers or other techniques so that they have a width that is less than the minimum feature size of the lithographic process used. Short channel effects may be especially bad where such techniques are used to form floating gate memory cells with very short channels. To form a memory string such as that of Figure 1, source/drain implants would generally be performed at this point. However, in this process an alternative technique is used. Exemplary processes that may be used to fabricate a memory array up to the point shown in Figure 3 are described in U.S. Patent 6,888,755.

Figure 4 shows NAND string 300 of Figure 3 after a plasma nitridation process is performed. The plasma nitridation process results in nitridation of exposed surfaces of the dielectric layer 334 and floating gates 336-339. The plasma nitridation process may be performed using conventional plasma deposition equipment such as a Dual Plasma Nitride

(DPN) chamber from Applied Materials, a Slot Plane Antenna (SPA) chamber from Tokyo

Electron Limited (TEL), Modified Magnetron Typed (MMT) system from Hitachi Kokusai Electric or other plasma processing equipment. In one example a MMT system performs a nitridation process using the following conditions: Temperature = 350degrees Centigrade;

Pressure = 50Pascals; Gas = Nitrogen (N2); RF Power = 250Watts. The result of the nitridation is that a nitrided layer 450 is formed. Portions 450a-c of nitrided layer 450 between floating gates 336-339 may include Silicon nitride and nitrided Silicon dioxide. Nitrided Silicon dioxide may also be formed over floating gates 336-339. Positively charged species are incorporated into nitrided surfaces. Generally, the charge incorporated into nitrided surfaces in this manner is not free to move because the nitrided surface is not electrically conductive, so the charge remains fixed in place. Thus, a nitrided surface formed in this way may be considered a fixed charge layer. Portions 450a-c of the fixed charge layer 450 that extend between floating gates 336-339 are on or close to substrate surface 332 (some Silicon dioxide of dielectric layer 334 may remain under fixed charge layer portions 450a-c, or all Silicon dioxide may be nitrided). The presence of electrical charge affects the portions of the substrate 330 underlying fixed charge layer portions 450a-c as discussed later. It may be desirable to locate fixed charge as close to the substrate as possible (without actually being in the substrate) and process conditions may be selected accordingly. This may provide a stronger channel inversion and hence a more conductive source/drain region.

Subsequent to forming fixed charge layer 450, one or more dielectric materials are deposited over memory string 300 to form an interlay er dielectric layer 556 (a dielectric layer separating floating gates and control gates - also referred to as "interpoly dielectric" though materials other than polysilicon may be used for these layers in some cases). In the example of

Figure 5 the interlay er dielectric layer 556 is formed of three layers: a Silicon dioxide layer, then a Silicon nitride layer, then another Silicon dioxide layer forming an Oxide-Nitride- Oxide (ONO) stack. In other examples the interlayer dielectric may be formed of a single material or from a different combination of materials. An interlayer dielectric layer may be formed using a process that provides a low thermal cycle so that the fixed charge layer is not subject to high temperatures that might affect it. For example Atomic Layer Deposition

(ALD), TEL SPA, or Applied Materials' In Situ Steam Generation (ISSG) system may be used.

Subsequent to forming interlayer dielectric layer 556, a conductive material is deposited to form a conductive layer 660 as shown in Figure 6. In the present example, conductive layer 660 is formed of doped polysilicon. Conductive layer 660 is deposited as a blanket layer that extends between floating gates 336-339 to fill the spaces between neighboring floating gates. Conductive layer 660 also extends over floating gates 336-339 when it is deposited, as shown in Figure 6. Subsequently, portions of conductive layer 660 that overlie the floating gates 336-339 are removed.

Figure 7 shows string 300 after removal of excess conductive material to leave separate portions 660a-e of conductive material between floating gates 336-339. Conductive material may be removed by etch back, Chemical Mechanical Polishing (CMP) or other techniques. The resulting separate portions 660a-e of conductive material form control gates extending in a direction perpendicular to the cross section shown. Control gates of neighboring strings are connected together to form word lines that may serve many strings. A floating gate may be accessed through control gates on both sides, typically by using both control gates together.

Figure 8 illustrates how string 300 of Figure 7 operates as a string of memory cells connected in series. In particular, as previously discussed, fixed charge layer portions 450a-c are formed over substrate surface 332 between floating gates 336-339 and fixed charge layer portions 4520a-c cause inversion layer portions to be formed in underlying portions of substrate 330, these inversion layer portions forming source/drain regions 880-882. The memory cells thus formed are connected in series by the source/drain regions 880-882.

Figure 9 shows a NAND string 900 according to an alternative embodiment of the present invention in which floating gates 902-905 have an inverted-T shape. Such inverted-T shaped floating gates may be formed by a process such as that described in U.S. Patent No. 7,026,684. As with the previous example, subsequent to formation of floating gates 902-905, a fixed charge layer 908 is formed over string 900 so that fixed charge layer portions create inversion layer portions where the fixed charge layer is on or close to substrate 910 (i.e. between floating gates 902-905). A fixed charge layer may be used in this manner with floating gates of other shapes also. In some cases such a fixed charge layer eliminates the need for source/drain implants, while in other cases the fixed charge layer may be used in combination with source/drain implants.

Figure 10 shows a cross section of a NAND string 1200 according to another embodiment of the present invention. A fixed charge layer 1202 extends over a surface 1204 of a substrate 1206. Fixed charge layer 1202 affects the band bending in the conductive channel regions, thereby altering their inversion threshold voltages. Figure 10 shows a dielectric layer 1208 extending between fixed charge layer 1202 and substrate surface 1204, though in other examples a fixed charge layer may directly overlie a substrate surface without an intervening dielectric layer. Floating gates 1210a-c and control gates 1212a-c are formed over fixed charge layer 1202. Thus, in Figure 10 fixed charge layer 1202 extends under both control gates 1212a-c and floating gates 1210a-c to cause formation of a conductive layer 1214 that is continuous along NAND string 1200 in the cross section of Figure 10 (subject to biases applied to overlying control gates 1212a-c). Where conductive layer 1214 extends under control gates 1212a-c, conductive layer 1214 forms conductive source/drain regions (instead of source/drain implantation or in addition to source/drain implantation). Where conductive layer 1214 extends under floating gates 1210a-c, conductive layer 1214 forms the channels of the floating gate cells (instead of channel implantation or in addition to channel implantation). It will be understood that conductive layer 1214 is also affected by control gates 1212a-c and floating gates 1210a-c so that conductive layer 1214 may not be electrically conductive for all conditions. Conductive layer 1214 also extends under select gate 1216 where it forms the channel of a select transistor. In the example of Figure 10, no separate source/drain implanted regions are needed because the source/drain regions are sufficiently conductive as a result of overlying fixed charge layer 1202. Also, no separate channel (or threshold voltage) implant is needed because the channel is sufficiently conductive (has a desirable threshold voltage) as a result of overlying fixed charge layer 1202. In other examples, a fixed charge layer may be provided in addition to one or more implants used to affect the conductivity of portions of a substrate.

In addition to being used in a NAND array as shown, a fixed charge layer according to an embodiment of the present invention may be formed in peripheral circuits that are connected to the NAND array. Various devices in peripheral circuits may have a fixed charge layer portion to provide an appropriate threshold voltage. For example, logic circuits may be provided on the same die as a NAND memory array and transistors within such logic circuits may include fixed charge layer portions overlying channel regions or other regions. In some cases, a controller and a NAND flash memory may be formed on the same die. Such a controller may include devices that have fixed charge layer portions.

The amount of charge contained in a given portion of a fixed charge layer (charge per unit area) may be selected according to the desired device characteristics. Also, the type of charge, positive or negative, may be chosen according to the desired result. For example, in an NMOS device, a fixed charge layer may have positive charge, which attracts negatively charged electrons towards the surface of the substrate in the channel region. This has the effect of reducing the threshold voltage of the device. Where the charge per unit area of the fixed charge layer is sufficiently high, the channel region may be inverted with no bias on the gate (V_GS ⁼ 0) so that the device operates in depletion mode. Where a fixed charge layer containing negative charge is located over the channel region of an NMOS device, the threshold voltage of the device may be increased. In the case of PMOS devices, the effects of positive and negative charge over the channel are reversed.

Fixed charge layers may be formed in a variety of ways using a variety of materials. Materials may include Hf-rich Hafnium oxide, Zr-rich Zirconium oxide, Silicon nitride, nitrided Silicon dioxide or some combination of these or other materials. Fixed charge layers may be formed by plasma deposition, plasma nitrification, plasma oxidation, chemical vapor deposition, atomic layer deposition, rapid thermal processing, ion implantation or other techniques. A fixed charge layer may contain charge as-deposited or may have charge added after deposition (such as by plasma processing). In some cases, a fixed charge layer has charge as-deposited and subsequently has additional charge added. In one example, nitridation of a Silicon dioxide surface results in a nitrided Silicon dioxide that contains positive charge. A fixed charge layer may result where surface states are created on a substrate by a process such as a plasma deposition process. After a fixed charge layer is formed, the charge located in the fixed charge layer generally remains unchanged (fixed) during the lifetime of the device and is not significantly affected by voltages normally used in the device.

A fixed charge layer may be patterned in some manner so that fixed charge layer portions remain only where desired. For example, as shown in Figure 11 , fixed charge layer portions 1320a-d may be desired under floating gates 1322a-c but not under control gates 1324a-c. In this case, a separate source/drain implant may form source/drain regions 1326a-c. A fixed charge layer may be deposited as a blanket layer over the entire substrate 1328 and later etched to remove portions that are not needed. For example, floating gates 1322a-c may be used as a mask layer to pattern the fixed charge layer, leaving fixed charge layer portions 1320a-c only under floating gates 1322a-c and under select gate 1330. Other patterning schemes may also be used. While Figure 11 indicates that no fixed charge remains under control gates 1324a-c, in other cases the fixed charge layer may be reduced but not completely removed at these locations. Thus, some of the fixed charge layer may be removed, leaving a smaller amount of charge per unit area under control gates than under floating gates. Alternatively, additional processing (e.g. nitridation or implantation) may be performed to add charge to fixed charge layer portions under control gates. Other mask layers may also be provided to allow increased or decreased charge per unit area for particular regions. Such addition and removal of charge may be used to form fixed charge portions having a range of charge per unit area for different purposes. Figures 12-14 show a process for forming a NAND flash memory array, using a fixed charge layer, according to an embodiment of the present invention. Other processes may also be used to form a NAND flash memory array. Figure 12 shows a portion of a substrate 1440 at an early stage of fabrication of a NAND memory array. Substrate 1440 is a Silicon substrate that may be lightly doped and have appropriately doped wells formed near a surface 1442 to isolate the active region from the underlying bulk. A dielectric layer 1444 is formed on surface 1442 of substrate 1440. In the example shown, dielectric layer 1444 is a Silicon Dioxide (oxide) layer that is grown on substrate 1440. Dielectric layer 1444 may be grown in a furnace in a similar process to that used for forming a conventional tunnel oxide.

Subsequent to forming dielectric layer 1444, a nitridation process is performed that nitrides dielectric layer 1444. The plasma nitridation process may be performed using conventional plasma deposition equipment such as a Dual Plasma Nitride (DPN) chamber from Applied Materials, a Slot Plane Antenna (SPA) chamber from Tokyo Electron Limited (TEL), Modified Magnetron Typed (MMT) system from Hitachi Kokusai Electric or other plasma processing equipment. In one example a MMT system performs a nitridation process using the following conditions: Temperature = 350degrees Centigrade; Pressure = 50Pascals; Gas = Nitrogen (N2); RF Power = 250Watts. The result of the nitridation is that a fixed charge layer 1446 is formed. Fixed charge layer 1446 may include Silicon nitride and nitrided Silicon dioxide. Positively charged species are incorporated into nitrided surfaces. Generally, the charge incorporated into nitrided surfaces in this manner is not free to move because the nitrided surface is not electrically conductive, so the charge remains fixed in place. Thus, a nitrided surface formed in this way may be considered a fixed charge layer. Nitridation of dielectric layer 1444 may at least partially consume dielectric layer 1444. While Figure 12 shows dielectric layer 1444 remaining after nitridation, in other cases no unnitrided dielectric may remain so that a fixed charge layer is formed directly over the substrate surface. In some cases, the location of the fixed charge within a dielectric layer may be controlled by adjusting a bias voltage applied to the substrate (or to a chuck on which the substrate sits) during plasma nitridation. Thus, a fixed charge layer may be formed directly on the substrate surface or at a chosen distance from the substrate surface.

In an alternative embodiment, a fixed charge layer may be formed by implanting ions into a dielectric layer, such as a Silicon Dioxide layer. The depth of an implanted layer may be controlled by adjusting implant energy so that the distance between the fixed charge layer and the substrate may be chosen. In an alternative embodiment, a fixed charge layer is formed by deposition of a material that contains a fixed charge as-deposited, without requiring additional processing such as plasma processing or implantation as previously described. While these techniques may be considered as alternative methods of forming a fixed charge layer, they may also be combined so that, for example, a layer may be deposited containing a fixed charge as-deposited and may then be subject to additional processing (e.g. nitridation or implantation) to add more charge. Charge may also be removed, for example by etching away some or all of the fixed charge layer.

Subsequent to the nitridation of dielectric layer 1444, a layer of conductive floating gate material is deposited over fixed charge layer 1446. In the present example, doped polysilicon is used as the floating gate material. The floating gate material is subsequently patterned using a hard mask pattern. A hard mask pattern may be formed using a conventional lithographic process where a photoresist layer is patterned and the pattern transferred to a hard mask layer. This produces hard mask portions that are as small as the minimum feature size of the lithographic process used. Alternatively, a spacer scheme may be used to form hard mask portions that are smaller than the minimum feature size of the lithographic process. Examples of such spacer schemes are provided in US Patent No. 6,888,755. Figure 13 shows hard mask portions 1448a-d formed using a spacer scheme and subsequently used to pattern the floating gate layer into floating gate portions 1450a-d. In particular, the floating gate layer is patterned by performing an anisotropic etch while hard mask layer portions 1448a-d are in place over the floating gate layer. The etch stops at the fixed charge layer 1446. An etch may be used that is selective to polysilicon over nitrided Silicon Dioxide so that little or no etching of the nitrided dielectric layer occurs.

In an alternative embodiment, a fixed charge layer is also etched at this point. Nitrided dielectric material of a fixed charge layer may be completely removed where it is exposed between remaining portions of floating gate material, or may be only partially removed. By performing partial removal, the fixed charge per unit area in the exposed portions of the fixed charge layer may be reduced to a chosen level. Thus, the fixed charge per unit area under remaining floating gate material may be greater than the fixed charge per unit area elsewhere. Complete removal of exposed fixed charge layer portions may be followed by deposition of replacement fixed charge layer portions. For example, where a nitrided dielectric layer is used to fix positive charge under floating gates, it may be desirable to have negative charge between floating gates. So, the nitrided dielectric layer is removed in these areas and is replaced by another fixed charge layer that contains negative charge. Charge may also be added to exposed portions of a fixed charge layer at this point if desired so that the charge per unit area is increased over source/drain regions. For example, additional nitridation may be performed, or ions may be implanted to alter the charge per unit area in exposed portions of a fixed charge layer. It should be noted that remaining floating gate portions 1450a-d of Figure 14 may be individual floating gates at this point if Shallow Trench Isolation (STI) structures are already formed (STI structures separating floating gates in the direction perpendicular to the cross section shown). Alternatively, separation of remaining floating gate portions 1450a-d into individual floating gates may occur later when STI structures are formed.

Subsequent to patterning the floating gate material, an interlayer dielectric layer 1652 is formed over the structure of Figure 13 as shown by Figure 14. In the present example, the interlayer dielectric layer 1652 is a compound layer formed of a Silicon Dioxide (Oxide) layer, followed by a Silicon Nitride (Nitride) layer, followed by a second Silicon Dioxide (Oxide) layer. Such an Oxide -Nitride-Oxide (ONO) layer provides insulation between floating gates and control gates. In the present example a low thermal cycle ONO is used so that there is little or no diffusion of charge from the fixed charge layer. Other dielectric materials may also be used to form an interlayer dielectric layer in some cases.

Subsequent to formation of interlayer dielectric layer 1652 an electrically conductive control gate material 1754 is deposited as shown in Figure 15. In the present example, the control gate material 1754 is doped polysilicon (similar to the floating gate material), though other conductive materials may also be used. Control gate material 1754 is deposited to a thickness that is sufficient to fill the gaps between remaining floating gate portion 1450a-d.

Subsequent to deposition of control gate material 1754, excess control gate material is removed as shown in Figure 16. In the present example, removal of excess material is achieved by etching back control gate material 1754. The removal of excess control gate material results in the formation of separate control gates 1856a-c between floating gates

1450a-d. In other examples, Chemical Mechanical Polishing (CMP) or other processes may be used to remove excess control gate material. In some cases, STI structures are formed at this point to isolate adjacent NAND strings in the word line direction. In this case, word lines extending over control gates are added to connect control gates in the word line direction. Such word lines may be formed by conventional patterning of conductive material. In the example shown, no additional word lines are needed because control gates 1856a-c connect from one string to another to form word lines. Figure 16 also shows a negative charge layer 1858 that extends under floating gates 1450a-c and control gates 1856a-c of the NAND string. A negative charge layer 1858 is formed by electrons that are attracted to surface 1442 of substrate 1440 by positive charge in overlying fixed charge layer 1446.

Figure 17 shows an alternative structure in which floating gates 1960a-d in a NAND string are formed having an inverted-T shape in cross section. Examples of such floating gates and their formation are described in US Patent Application Publication No. 20050199939 and US Patent 7,026,684. Figure 17 shows a nitrided dielectric forming a fixed charge layer 1962 underlying both floating gates 1960a-d and control gates 1964a-c as before so that fixed charge affects underlying substrate 1966. Subsequent to forming fixed charge layer 1962, floating gates 1960a-c and control gates 1964a-c may be formed according to any suitable scheme to form floating gates having an inverted-T shape.

A fixed charge layer may be incorporated in any integrated circuit (memory or other circuit) by performing nitridation or other processing to place charge in a gate dielectric layer. Subsequent processing may be carried out as before, or with some adjustment for thermal budget etc. In the example of Figure 18, a NAND memory string 1000 has control gates 1002a-d lying over floating gates 1004a-d (one control gate coupled to a floating gate). A fixed charge layer 1006 holding positive charge extends across substrate 1008 so that fixed charge layer portions are present on substrate 1008 under floating gates 1004a-d and also between floating gates 1004a-d. The presence of fixed charge layer 1006 causes electrons to be drawn to the underlying channel and source/drain regions where they form a layer of negative charge 1010 as shown. Source/drain and channel implants may also be provided in this type of structure to provide added control of threshold voltage and to reduce resistance of source/drain regions.

In other examples, fixed charge layer portions are used in devices that do not include floating gates, such as logic devices used in peripheral areas of memory arrays. The use of fixed charge in such locations may be in place of, or in addition to, the use of implanted dopants to control threshold voltage. In some nonvolatile memory cells, charge trapping structures are used instead of conductive floating gates so that the state of a cell depends on the charge trapped in such a structure. Fixed charge layers may be used under such structures in a similar manner to their use under conductive floating gates.

All patents, patent applications, articles, books, specifications, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of a term between any of the incorporated publications, documents or things and the text of the present document, the definition or use of the term in the present document shall prevail.

Although the various aspects of the present invention have been described with respect to certain preferred embodiments, it is understood that the invention is entitled to protection within the full scope of the appended claims.

Claims

THE CLAIMSWhat is claimed is:

1. A nonvolatile memory array comprising: a plurality of floating gate memory cells connected together in series to form a NAND string, the plurality of floating gate memory cells electrically connected by source/drain regions, a source/drain region including an inversion layer created by a fixed electrical charge within a fixed charge layer portion that extends over the source/drain region, control gates extending between floating gates such that a control gate overlies the fixed charge layer portion.

2. The nonvolatile memory array of claim 1 further comprising additional fixed charge layer portions that underlie floating gates.

3. The nonvolatile memory array of claim 2 wherein the fixed charge layer portions and the additional fixed charge layer portions are formed of a continuous fixed charge layer.

4. The nonvolatile memory array of claim 1 wherein each of the plurality of floating gate memory cells has an inverted-T shape in cross section.

5. The nonvolatile memory array of claim 1 further comprising an interlayer dielectric layer extending between floating gates and control gates.

6. The nonvolatile memory array of claim 1 further comprising a tunnel oxide underlying the plurality of floating gates.

7. A method of forming a nonvolatile NAND memory array comprising: forming a plurality of floating gates overlying a substrate surface; forming a plurality of fixed charge layer portions overlying the substrate surface, the plurality of fixed charge layer portions interspersed between the plurality of floating gates, each of the plurality of fixed charge layer portions formed having fixed electrical charge; and forming a plurality of control gates overlying the plurality of fixed charge layer portions.

8. The method of claim 7 further comprising forming a plurality of additional fixed charge layer portions underlying the plurality of floating gates.

9. The method of claim 8 wherein the plurality of fixed charge layer portions and the plurality of additional fixed charge layer portions are formed together from a continuous fixed charge layer.

10. The method of claim 7 wherein the fixed charge layer is formed by plasma nitridation of Silicon dioxide.