WO2008091579A3 - Memory having a vertical access device - Google Patents

Memory having a vertical access device Download PDF

Info

Publication number
WO2008091579A3
WO2008091579A3 PCT/US2008/000785 US2008000785W WO2008091579A3 WO 2008091579 A3 WO2008091579 A3 WO 2008091579A3 US 2008000785 W US2008000785 W US 2008000785W WO 2008091579 A3 WO2008091579 A3 WO 2008091579A3
Authority
WO
WIPO (PCT)
Prior art keywords
floor
recess
side walls
vertical access
memory
Prior art date
Application number
PCT/US2008/000785
Other languages
French (fr)
Other versions
WO2008091579A2 (en
Inventor
Werner Juengling
Original Assignee
Micron Technology Inc
Werner Juengling
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Werner Juengling filed Critical Micron Technology Inc
Priority to JP2009546445A priority Critical patent/JP4868265B2/en
Priority to EP08724673.2A priority patent/EP2126970B1/en
Priority to CN2008800085055A priority patent/CN101669200B/en
Priority to KR1020097017513A priority patent/KR101425247B1/en
Publication of WO2008091579A2 publication Critical patent/WO2008091579A2/en
Publication of WO2008091579A3 publication Critical patent/WO2008091579A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS

Abstract

Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess (50) in a semiconductor substrate (12) that includes a pair of opposed side walls (73, 75) and a floor (48) extending between the opposed side walls. A dielectric layer (62) may be deposited on the side walls and the floor of the recess. A conductive f ilm. (64) may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
PCT/US2008/000785 2007-01-22 2008-01-22 Memory having a vertical access device WO2008091579A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009546445A JP4868265B2 (en) 2007-01-22 2008-01-22 Memory with vertical access device
EP08724673.2A EP2126970B1 (en) 2007-01-22 2008-01-22 Memory having a vertical access device
CN2008800085055A CN101669200B (en) 2007-01-22 2008-01-22 Memory having a vertical access device
KR1020097017513A KR101425247B1 (en) 2007-01-22 2008-01-22 Memory having a vertical access device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/656,125 US7859050B2 (en) 2007-01-22 2007-01-22 Memory having a vertical access device
US11/656,125 2007-01-22

Publications (2)

Publication Number Publication Date
WO2008091579A2 WO2008091579A2 (en) 2008-07-31
WO2008091579A3 true WO2008091579A3 (en) 2009-01-15

Family

ID=39462124

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/000785 WO2008091579A2 (en) 2007-01-22 2008-01-22 Memory having a vertical access device

Country Status (7)

Country Link
US (2) US7859050B2 (en)
EP (1) EP2126970B1 (en)
JP (1) JP4868265B2 (en)
KR (1) KR101425247B1 (en)
CN (1) CN101669200B (en)
TW (1) TWI384586B (en)
WO (1) WO2008091579A2 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7859050B2 (en) 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device
JP4685147B2 (en) * 2008-10-14 2011-05-18 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
JP2011014666A (en) * 2009-07-01 2011-01-20 Toshiba Corp Semiconductor device and method of manufacturing the same
US8039340B2 (en) 2010-03-09 2011-10-18 Micron Technology, Inc. Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
US9484269B2 (en) * 2010-06-24 2016-11-01 Globalfoundries Inc. Structure and method to control bottom corner threshold in an SOI device
US9385132B2 (en) 2011-08-25 2016-07-05 Micron Technology, Inc. Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of forming isolation gate constructions in the fabrication of recessed access devices
US9177872B2 (en) * 2011-09-16 2015-11-03 Micron Technology, Inc. Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
KR101906406B1 (en) 2011-12-30 2018-12-10 삼성전자주식회사 non-volatile memory device having vertical structure and fabrication method
US8878271B2 (en) 2013-03-01 2014-11-04 Micron Technology, Inc. Vertical access device and apparatuses having a body connection line, and related method of operating the same
US9005463B2 (en) 2013-05-29 2015-04-14 Micron Technology, Inc. Methods of forming a substrate opening
US10014305B2 (en) 2016-11-01 2018-07-03 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US9761580B1 (en) * 2016-11-01 2017-09-12 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US10062745B2 (en) 2017-01-09 2018-08-28 Micron Technology, Inc. Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor
US9935114B1 (en) 2017-01-10 2018-04-03 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US9837420B1 (en) 2017-01-10 2017-12-05 Micron Technology, Inc. Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor
US9842839B1 (en) 2017-01-12 2017-12-12 Micron Technology, Inc. Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above
US10388658B1 (en) 2018-04-27 2019-08-20 Micron Technology, Inc. Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors
US10546863B1 (en) * 2018-08-02 2020-01-28 Micron Technology, Inc. Method for fabricating bit line contact
WO2020076758A1 (en) 2018-10-09 2020-04-16 Micron Technology, Inc. Devices including vertical transistors having hydrogen barrier materials, and related methods
US20230180467A1 (en) * 2021-12-02 2023-06-08 Micron Technology, Inc. Vertical access line in a folded digitline sense amplifier

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3844120A1 (en) * 1987-12-28 1989-07-13 Mitsubishi Electric Corp SEMICONDUCTOR DEVICE WITH TRENCH-SHAPED STRUCTURE
US5196722A (en) * 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5414289A (en) * 1992-03-02 1995-05-09 Motorola, Inc. Dynamic memory device having a vertical transistor
US5502320A (en) * 1993-03-15 1996-03-26 Kabushiki Kaisha Toshiba Dynamic random access memory (DRAM) semiconductor device
US5529944A (en) * 1995-02-02 1996-06-25 International Business Machines Corporation Method of making cross point four square folded bitline trench DRAM cell
US5587340A (en) * 1990-07-25 1996-12-24 Semiconductor Energy Laboratory Co., Ltd. Method of forming a semiconductor device in a substrate depression
US5885864A (en) * 1996-10-24 1999-03-23 Micron Technology, Inc. Method for forming compact memory cell using vertical devices
US6177699B1 (en) * 1998-03-19 2001-01-23 Lsi Logic Corporation DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation
US20040041188A1 (en) * 2002-08-29 2004-03-04 Bissey Lucien J. Annular gate and technique for fabricating an annular gate
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors
US20070205443A1 (en) * 2006-03-02 2007-09-06 Werner Juengling Vertical gated access transistor

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811067A (en) * 1986-05-02 1989-03-07 International Business Machines Corporation High density vertically structured memory
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5554550A (en) * 1994-09-14 1996-09-10 United Microelectronics Corporation Method of fabricating electrically eraseable read only memory cell having a trench
US6072209A (en) * 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US6737696B1 (en) 1998-06-03 2004-05-18 Micron Technology, Inc. DRAM capacitor formulation using a double-sided electrode
US6026019A (en) * 1998-06-19 2000-02-15 International Business Machines Corporation Two square NVRAM cell
US6261913B1 (en) 2000-08-23 2001-07-17 Micron Technology, Inc. Method for using thin spacers and oxidation in gate oxides
DE10129958B4 (en) * 2001-06-21 2006-07-13 Infineon Technologies Ag Memory cell arrangement and manufacturing method
US6617213B2 (en) * 2002-01-25 2003-09-09 Infineon Technologies Ag Method for achieving high self-aligning vertical gate studs relative to the support isolation level
US7269071B2 (en) * 2003-12-16 2007-09-11 Micron Technology, Inc. NROM memory cell, memory array, related devices and methods
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
US7148538B2 (en) * 2003-12-17 2006-12-12 Micron Technology, Inc. Vertical NAND flash memory array
KR100526891B1 (en) * 2004-02-25 2005-11-09 삼성전자주식회사 Verticla transistor structure for use in semiconductor device and method thereof
US7518182B2 (en) * 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
TWI270977B (en) * 2005-06-27 2007-01-11 Powerchip Semiconductor Corp Non-volatile memory and manufacturing method and operating method thereof
US8338887B2 (en) * 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US7645671B2 (en) * 2006-11-13 2010-01-12 Micron Technology, Inc. Recessed access device for a memory
US7859050B2 (en) 2007-01-22 2010-12-28 Micron Technology, Inc. Memory having a vertical access device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3844120A1 (en) * 1987-12-28 1989-07-13 Mitsubishi Electric Corp SEMICONDUCTOR DEVICE WITH TRENCH-SHAPED STRUCTURE
US5587340A (en) * 1990-07-25 1996-12-24 Semiconductor Energy Laboratory Co., Ltd. Method of forming a semiconductor device in a substrate depression
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5414289A (en) * 1992-03-02 1995-05-09 Motorola, Inc. Dynamic memory device having a vertical transistor
US5196722A (en) * 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
US5502320A (en) * 1993-03-15 1996-03-26 Kabushiki Kaisha Toshiba Dynamic random access memory (DRAM) semiconductor device
US5529944A (en) * 1995-02-02 1996-06-25 International Business Machines Corporation Method of making cross point four square folded bitline trench DRAM cell
US5885864A (en) * 1996-10-24 1999-03-23 Micron Technology, Inc. Method for forming compact memory cell using vertical devices
US6177699B1 (en) * 1998-03-19 2001-01-23 Lsi Logic Corporation DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation
US20040041188A1 (en) * 2002-08-29 2004-03-04 Bissey Lucien J. Annular gate and technique for fabricating an annular gate
US20060046407A1 (en) * 2004-09-01 2006-03-02 Werner Juengling DRAM cells with vertical transistors
US20070205443A1 (en) * 2006-03-02 2007-09-06 Werner Juengling Vertical gated access transistor

Also Published As

Publication number Publication date
KR20090117744A (en) 2009-11-12
JP2010517269A (en) 2010-05-20
US7859050B2 (en) 2010-12-28
US8617953B2 (en) 2013-12-31
EP2126970A2 (en) 2009-12-02
EP2126970B1 (en) 2019-08-21
TWI384586B (en) 2013-02-01
TW200845308A (en) 2008-11-16
JP4868265B2 (en) 2012-02-01
CN101669200A (en) 2010-03-10
US20110081757A1 (en) 2011-04-07
WO2008091579A2 (en) 2008-07-31
US20080173920A1 (en) 2008-07-24
CN101669200B (en) 2011-12-21
KR101425247B1 (en) 2014-08-01

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