WO2008124328A4 - Memory devices having electrodes comprising nanowires, systems including same and methods of forming same - Google Patents

Memory devices having electrodes comprising nanowires, systems including same and methods of forming same Download PDF

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Publication number
WO2008124328A4
WO2008124328A4 PCT/US2008/058485 US2008058485W WO2008124328A4 WO 2008124328 A4 WO2008124328 A4 WO 2008124328A4 US 2008058485 W US2008058485 W US 2008058485W WO 2008124328 A4 WO2008124328 A4 WO 2008124328A4
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WO
WIPO (PCT)
Prior art keywords
conductive pad
nanowire
memory device
conductive
variable resistance
Prior art date
Application number
PCT/US2008/058485
Other languages
French (fr)
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WO2008124328A3 (en
WO2008124328A2 (en
Inventor
Jun Liu
Michael P Violette
Original Assignee
Micron Technology Inc
Jun Liu
Michael P Violette
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Jun Liu, Michael P Violette filed Critical Micron Technology Inc
Priority to JP2010502207A priority Critical patent/JP5272270B2/en
Priority to EP08799763.1A priority patent/EP2143154B1/en
Publication of WO2008124328A2 publication Critical patent/WO2008124328A2/en
Publication of WO2008124328A3 publication Critical patent/WO2008124328A3/en
Publication of WO2008124328A4 publication Critical patent/WO2008124328A4/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Claims

AMENDED CLAIMS received by the International Bureau on 10 December 2008(10.12.2008)
1. A memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material, the at least one of the anode and the cathode comprising the single nanowire further comprising a conductive catalytic structure comprising a catalyst material, the conductive catalytic structure comprising a generally conical structure having a tip in electrical contact with a second end of the single nanowire opposite the one end thereof in electrical contact with the variable resistance material.
2. The memory device of claim 1, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
3. The memory device of claim 1 , wherein the nanowire comprises a carbon nanotube having at least one wall.
4. The memory device of claim 1, wherein the nanowire comprises at least one of silicon, germanium, gallium, a III- V type semiconductor material, a II- VI type semiconductor material, and a metal.
5. The memory device of claim 1 , wherein the nanowire comprises at least one of a superlattice structure and a PN junction.
6. The memory device of claim 1 , wherein the variable resistance material comprises a phase change material.
7. The memory device of claim 1, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
8. The memory device of claim 1, wherein the generally conical structure has a base in electrical contact with a conductive pad.
9. The memory device of claim 1 , wherein the tip has a minimum cross- sectional area of less than about 300 square nanometers.
10. The memory device of claim 1 , further comprising a layer of dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
11. A memory device having at least one memory cell comprising a variable resistance material disposed between an anode and a cathode, at least one of the anode and the cathode comprising a nanowire providing electrical contact between a conductive pad and the variable resistance material, the memory cell configured to cause current flow between the anode and the cathode at least predominantly through the nanowire in response to a voltage applied between the anode and the cathode, wherein the memory device further comprises a conductive catalytic structure disposed between the conductive pad and the nanowire, the conductive catalytic structure comprising a catalyst material for forming the nanowire, and wherein the conductive catalytic structure comprises a generally conical structure having a tip electrically coupled to the nanowire.
12. The memory device of claim 11 , wherein the nanowire provides at least a portion of a sole, low-resistance electrical pathway between the variable resistance material and the conductive pad within the memory cell.
13. The memory device of claim 11 , wherein the nanowire comprises a carbon nanotube having at least one wall.
14. The memory device of claim 11 , wherein the variable resistance material comprises a phase change material.
15. The memory device of claim 11 , wherein the generally conical structure has a base electrically coupled to the conductive pad.
16. The memory device of claim 11 , further comprising a dielectric material on at least a portion of an exterior surface of the conductive catalytic structure.
17. An electronic system comprising: at least one electronic signal processor; at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising at least one memory cell having an anode, a cathode, and a volume of variable resistance material disposed between the anode and the cathode, at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material and a second, opposite end thereof in electrical contact with a tip of a generally conical catalytic structure; and at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.
18. The electronic system of claim 17, wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a conductive pad, the nanowire providing electrical contact between the volume of variable resistance material and the conductive pad.
19. The electronic system of claim 17, wherein the variable resistance material comprises a phase change material.
20. The electronic system of claim 20, wherein the catalyst material comprises at least one of aluminum, cobalt, gallium, gold, indium, iron, molybdenum, nickel, palladium, platinum, silver, tantalum, and zinc.
21. The electronic system of claim 20, wherein the generally conical catalytic structure has a base electrically coupled to a conductive pad.
22. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; providing a conductive, generally conical catalytic structure on the at least one conductive pad; and forming a single nanowire on a tip of the generally conical catalytic structure over the conductive pad and causing the single nanowire to extend generally outwardly from the conductive pad and the tip of the generally conical catalytic structure; establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the end of the single nanowire in electrical contact with the volume of variable resistance material.
23. The method of claim 22, further comprising enabling electrical communication between the volume of variable resistance material and the conductive pad at least predominantly through the single nanowire.
24. The method of claim 22, wherein forming a single nanowire comprises forming a single nanowire comprising at least one of silicon, germanium, gallium, a IH-V type semiconductor material, a II- VI type semiconductor material, and a metal.
25. The method of claim 22, further comprising forming at least one of a superlattice structure and a PN junction in the single nanowire.
26. The method of claim 22, wherein establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of variable resistance material comprises establishing electrical contact between an end of the single nanowire remote from the conductive pad and a volume of phase change material.
27. The method of claim 22, further comprising catalyzing formation of the single nanowire using the conductive, generally conical catalytic structure.
28. The method of claim 22, wherein providing a conductive, generally conical catalytic structure further comprises electrically coupling a base of the conductive, generally conical catalytic structure directly to the at least one conductive pad.
29. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: depositing catalyst material on the at least one conductive pad through an aperture in a mask, depositing catalyst material comprising: orienting the substrate in a plane oriented at an angle relative to a general direction of flow of the catalyst material; and rotating the substrate in the plane about a rotational axis.
30. The method of claim 22, wherein providing a conductive, generally conical catalytic structure comprises: forming a generally cylindrical structure and electrically coupling a base of the generally cylindrical structure to the at least one conductive pad; and sharpening an end of the generally cylindrical structure opposite the at least one conductive pad.
31. The method of claim 30, wherein sharpening an end of the generally cylindrical structure comprises using at least one of an anisotropic etching process, a sputtering process, and an oxidation process.
32. The method of claim 22, wherein providing a conductive, generally conical catalytic structure on the at least one conductive pad comprises: forming a layer of catalyst material over the at least one conductive pad; forming a discrete volume of mask material on an exposed surface of the layer of catalyst material over the at least one conductive pad; and exposing the layer of catalyst material to an etchant for a selected amount of time to remove catalyst material laterally surrounding the volume of mask material and a portion of the catalyst material covered by the volume of mask material.
33. A method of forming a memory device, the method comprising: forming a first electrode, comprising: forming at least one conductive pad on a substrate; fabricating a single nanowire at a location remote from the conductive pad; positioning the single nanowire over the conductive pad; providing electrical contact between a first end of the single nanowire and the conductive pad; and causing the single nanowire to extend generally outwardly from the conductive pad; providing electrical contact between a second end of the single nanowire and a volume of variable resistance material; and forming a second electrode in electrical contact with the volume of variable resistance material on a side thereof opposite the second end of the single nanowire.
PCT/US2008/058485 2007-04-05 2008-03-27 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same WO2008124328A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010502207A JP5272270B2 (en) 2007-04-05 2008-03-27 MEMORY DEVICE HAVING ELECTRODES CONTAINING NANOWIRE, SYSTEM INCLUDING THE MEMORY DEVICE, AND METHOD FOR FORMING THE MEMORY DEVICE
EP08799763.1A EP2143154B1 (en) 2007-04-05 2008-03-27 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/784,315 2007-04-05
US11/784,315 US7859036B2 (en) 2007-04-05 2007-04-05 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same

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WO2008124328A2 WO2008124328A2 (en) 2008-10-16
WO2008124328A3 WO2008124328A3 (en) 2008-12-18
WO2008124328A4 true WO2008124328A4 (en) 2009-02-12

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US (6) US7859036B2 (en)
EP (1) EP2143154B1 (en)
JP (1) JP5272270B2 (en)
KR (1) KR101154659B1 (en)
CN (1) CN101652873A (en)
TW (1) TWI402975B (en)
WO (1) WO2008124328A2 (en)

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