WO2008126025A3 - Method for processing a digital signal - Google Patents
Method for processing a digital signal Download PDFInfo
- Publication number
- WO2008126025A3 WO2008126025A3 PCT/IB2008/051357 IB2008051357W WO2008126025A3 WO 2008126025 A3 WO2008126025 A3 WO 2008126025A3 IB 2008051357 W IB2008051357 W IB 2008051357W WO 2008126025 A3 WO2008126025 A3 WO 2008126025A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- value
- precursor
- signal value
- duration
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
Abstract
A system receiving a digital signal (50) making a transition (50) from a first discrete signal value Il to a second discrete signal value 12 can show undesirable oscillations. The invention proposes a method for reducing such oscillations. The method comprises the step of generating a series of one or more precursor pulses (52,- 52, 53, 54, 55) prior to said signal transition, each precursor pulse having the second discrete signal- value. The i-th pulse has a duration Δi in a precursor time interval of duration Ti, and 'thus represents an average signal value Si = 11 + (12-11 ) &sdot,- Δi/Ti. This average signal value Si is continuously rising (if I2>I1) or falling (if I2<I1), preferably in a linear manner. A signal processing circuit capable of performing the method can be interposed between a. signal source and a receiving system, which may be a lighting system comprising at least one LED.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07106304 | 2007-04-17 | ||
EP07106304.4 | 2007-04-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008126025A2 WO2008126025A2 (en) | 2008-10-23 |
WO2008126025A3 true WO2008126025A3 (en) | 2008-12-31 |
Family
ID=39688802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2008/051357 WO2008126025A2 (en) | 2007-04-17 | 2008-04-10 | Method for processing a digital signal |
Country Status (2)
Country | Link |
---|---|
TW (1) | TW200908782A (en) |
WO (1) | WO2008126025A2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100677A (en) * | 1999-10-18 | 2000-08-08 | National Semiconductor Corporation | Switching controller chip with internal but not external soft start circuitry and DC to DC converter including such a controller chip |
US6505085B1 (en) * | 1999-03-04 | 2003-01-07 | Massachusetts Institute Of Technology | Method and apparatus for creating time-optimal commands for linear systems |
US20050146540A1 (en) * | 2004-01-07 | 2005-07-07 | Texas Instruments Incorporated | Method and apparatus for increasing a perceived resolution of a display |
WO2008048865A2 (en) * | 2006-10-13 | 2008-04-24 | Ipower Holdings Llc | Pulse width modulation sequence generating a near critical damped step response |
-
2008
- 2008-04-10 WO PCT/IB2008/051357 patent/WO2008126025A2/en active Application Filing
- 2008-04-14 TW TW097113532A patent/TW200908782A/en unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6505085B1 (en) * | 1999-03-04 | 2003-01-07 | Massachusetts Institute Of Technology | Method and apparatus for creating time-optimal commands for linear systems |
US6100677A (en) * | 1999-10-18 | 2000-08-08 | National Semiconductor Corporation | Switching controller chip with internal but not external soft start circuitry and DC to DC converter including such a controller chip |
US20050146540A1 (en) * | 2004-01-07 | 2005-07-07 | Texas Instruments Incorporated | Method and apparatus for increasing a perceived resolution of a display |
WO2008048865A2 (en) * | 2006-10-13 | 2008-04-24 | Ipower Holdings Llc | Pulse width modulation sequence generating a near critical damped step response |
Also Published As
Publication number | Publication date |
---|---|
WO2008126025A2 (en) | 2008-10-23 |
TW200908782A (en) | 2009-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
BRPI0409327A (en) | device for generating an output audio signal based on an input audio signal, method for providing an output audio signal based on an input audio signal and apparatus for providing an output audio signal | |
SG138449A1 (en) | Enumeration method for the link clock rate and the pixel/audio clock rate | |
GB0503721D0 (en) | Protocol conversion and arbitration circuit, system having the same, and method for converting and arbitrating signals | |
EP2136576A3 (en) | AV System | |
SG131017A1 (en) | High voltage high side transistor driver | |
WO2002095942A3 (en) | Dual-edge triggered dynamic logic | |
TW200644420A (en) | Apparatus and methods for adaptive trip point detection | |
TW200625796A (en) | Audio power amplifier IC and audio system equipped therewith | |
WO2007007321A3 (en) | Method and system for processing an electroencephalograph (eeg) signal | |
TW200627807A (en) | Analog-to-digital converter | |
TW200419910A (en) | Method and device for generating a clock signal having predetermined clock signal properties | |
WO2008043427A3 (en) | Device and method for synchronizing the states of a plurality of sequential processing units | |
WO2011113025A3 (en) | Adjustable sampling rate converter | |
EP2096785A3 (en) | Clock regeneration circuit | |
ATE440429T1 (en) | DEVICE HAVING AN MPE-FEC FRAME MEMORY | |
WO2007055731A3 (en) | Optical signal jitter reduction via electrical equalization in optical transmission systems | |
TW200636369A (en) | Optical receiver | |
WO2005117382A3 (en) | Multi-channel pulse modulator system | |
WO2007017057A3 (en) | Circuit arrangement and method for converting an alternating voltage into a rectified voltage | |
TW200618477A (en) | Flip-flop, latch and latching method | |
WO2008126025A3 (en) | Method for processing a digital signal | |
WO2005018205A3 (en) | Telephone signal generator and methods and devices using the same | |
TWI266489B (en) | Apparatus and method for increasing signal estimation accuraccy | |
TW200501115A (en) | Write pulse generator with alignment calibration | |
TWI318056B (en) | Dll circuit having two input standard clocks, clock signal generation circuit having the dll circuit and clock signal generation method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08737785 Country of ref document: EP Kind code of ref document: A2 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08737785 Country of ref document: EP Kind code of ref document: A2 |