WO2008126177A1 - Nonvolatile semiconductor storage device, and its manufacturing method - Google Patents

Nonvolatile semiconductor storage device, and its manufacturing method Download PDF

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Publication number
WO2008126177A1
WO2008126177A1 PCT/JP2007/055073 JP2007055073W WO2008126177A1 WO 2008126177 A1 WO2008126177 A1 WO 2008126177A1 JP 2007055073 W JP2007055073 W JP 2007055073W WO 2008126177 A1 WO2008126177 A1 WO 2008126177A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
cell transistor
gate electrode
storage device
floating gate
Prior art date
Application number
PCT/JP2007/055073
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuhiro Mizutani
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009508728A priority Critical patent/JPWO2008126177A1/en
Priority to PCT/JP2007/055073 priority patent/WO2008126177A1/en
Priority to TW096109326A priority patent/TW200840024A/en
Publication of WO2008126177A1 publication Critical patent/WO2008126177A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Provided is a nonvolatile semiconductor storage device comprising a memory cell transistor (MT) including a floating gate electrode (18b) formed over a semiconductor substrate (10) through a first insulating film (16) and a control gate electrode (28b) formed over the floating gate electrode (18b) through a second insulating film (26). Further comprised is a selective transistor (ST) connected with the memory cell transistor. The memory cell transistor has its gate length set so short that a threshold voltage may be lowered by a short channel effect. When the memory cell transistor is changed from an initial state to an erase state, a large quantity of positive charge need not be injected into the floating gate electrode so that the time period required for erasing the information of the memory cell transistor can be shortened.
PCT/JP2007/055073 2007-03-14 2007-03-14 Nonvolatile semiconductor storage device, and its manufacturing method WO2008126177A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009508728A JPWO2008126177A1 (en) 2007-03-14 2007-03-14 Nonvolatile semiconductor memory device and manufacturing method thereof
PCT/JP2007/055073 WO2008126177A1 (en) 2007-03-14 2007-03-14 Nonvolatile semiconductor storage device, and its manufacturing method
TW096109326A TW200840024A (en) 2007-03-14 2007-03-19 Nonvolatile semiconductor memory device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055073 WO2008126177A1 (en) 2007-03-14 2007-03-14 Nonvolatile semiconductor storage device, and its manufacturing method

Publications (1)

Publication Number Publication Date
WO2008126177A1 true WO2008126177A1 (en) 2008-10-23

Family

ID=39863361

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055073 WO2008126177A1 (en) 2007-03-14 2007-03-14 Nonvolatile semiconductor storage device, and its manufacturing method

Country Status (3)

Country Link
JP (1) JPWO2008126177A1 (en)
TW (1) TW200840024A (en)
WO (1) WO2008126177A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160365311A1 (en) * 2015-06-10 2016-12-15 Macronix International Co.Ltd. Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned double patterning

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144878A (en) * 1996-11-06 1998-05-29 Hitachi Ltd Semiconductor integrated circuit device and fabrication thereof
JP2005197750A (en) * 2004-01-07 2005-07-21 Programmable Microelectron Corp Two-transistor pmos memory cell and manufacturing method therefor
JP2006059869A (en) * 2004-08-17 2006-03-02 Sony Corp Toggle mode writing type nonvolatile magnetic memory device
JP2006303022A (en) * 2005-04-18 2006-11-02 Toshiba Corp Method of manufacturing semiconductor device
JP2007005654A (en) * 2005-06-24 2007-01-11 Toshiba Corp Nonvolatile semiconductor memory
JP2007027726A (en) * 2005-07-12 2007-02-01 Samsung Electronics Co Ltd Nand type flash memory device and its manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4053232B2 (en) * 2000-11-20 2008-02-27 株式会社ルネサステクノロジ Semiconductor integrated circuit device and manufacturing method thereof
JP2003282705A (en) * 2002-03-27 2003-10-03 Toshiba Corp Semiconductor device and method of manufacturing the same
JP3947135B2 (en) 2003-05-30 2007-07-18 株式会社東芝 Nonvolatile semiconductor memory device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144878A (en) * 1996-11-06 1998-05-29 Hitachi Ltd Semiconductor integrated circuit device and fabrication thereof
JP2005197750A (en) * 2004-01-07 2005-07-21 Programmable Microelectron Corp Two-transistor pmos memory cell and manufacturing method therefor
JP2006059869A (en) * 2004-08-17 2006-03-02 Sony Corp Toggle mode writing type nonvolatile magnetic memory device
JP2006303022A (en) * 2005-04-18 2006-11-02 Toshiba Corp Method of manufacturing semiconductor device
JP2007005654A (en) * 2005-06-24 2007-01-11 Toshiba Corp Nonvolatile semiconductor memory
JP2007027726A (en) * 2005-07-12 2007-02-01 Samsung Electronics Co Ltd Nand type flash memory device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
TW200840024A (en) 2008-10-01
JPWO2008126177A1 (en) 2010-07-15

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