WO2008147928A1

WO2008147928A1 - Vlsi layouts of fully connected generalized networks

Info

Publication number: WO2008147928A1
Application number: PCT/US2008/064605
Authority: WO
Inventors: Venkat Konda
Original assignee: Venkat Konda
Priority date: 2007-05-25
Filing date: 2008-05-22
Publication date: 2008-12-04
Also published as: US20110037498A1; US8269523B2

Abstract

In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub- integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub- integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.

Description

VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS

Venkat Konda

CROSS REFERENCE TO RELATED APPLICATIONS

This application is Continuation In Part PCT Application to and incorporates by reference in its entirety the U.S. Provisional Patent Application Serial No. 60/940, 394 entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the PCT Application Serial No. PCT/US08/56064 entitled "FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed March 6, 2008, the U.S. Provisional Patent Application Serial No. 60/905,526 entitled "LARGE SCALE CROSSPOINT REDUCTION WITH NONB LOCKING UNICAST & MULTICAST IN ARBITRARILY LARGE MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed March 6, 2007, and the U.S. Provisional Patent Application Serial No. 60/940, 383 entitled "FULLY CONNECTED GENERALIZED MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the PCT Application Docket No. S-0038PCT entitled "FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed concurrently, the U.S. Provisional Patent

Application Serial No. 60/940, 387 entitled "FULLY CONNECTED GENERALIZED BUTTERFLY FAT TREE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, and the U.S. Provisional Patent Application Serial No. 60/940, 390 entitled "FULLY CONNECTED GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007

This application is related to and incorporates by reference in its entirety the PCT

Application Docket No. S-0039PCT entitled "FULLY CONNECTED GENERALIZED MULTI-LINK MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed concurrently, the U.S. Provisional Patent Application Serial No. 60/940, 389 entitled "FULLY CONNECTED GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007, the U.S. Provisional Patent Application Serial No. 60/940, 391 entitled "FULLY CONNECTED GENERALIZED FOLDED MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007 and the U.S. Provisional Patent Application Serial No. 60/940, 392 entitled "FULLY

CONNECTED GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTISTAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed May 25, 2007.

This application is related to and incorporates by reference in its entirety the U.S. Provisional Patent Application Serial No. 60/984, 724 entitled "VLSI LAYOUTS OF

FULLY CONNECTED NETWORKS WITH LOCALITY EXPLOITATION" by Venkat Konda assigned to the same assignee as the current application, filed November 2, 2007.

This application is related to and incorporates by reference in its entirety the U.S. Provisional Patent Application Serial No. 61/018, 494 entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS" by Venkat Konda assigned to the same assignee as the current application, filed January 1, 2008. BACKGROUND OF INVENTION

Multi-stage interconnection networks such as Benes networks and butterfly fat tree networks are widely useful in telecommunications, parallel and distributed computing. However VLSI layouts, known in the prior art, of these interconnection networks in an integrated circuit are inefficient and complicated.

Other multi-stage interconnection networks including butterfly fat tree networks, Banyan networks, Batcher-Banyan networks, Baseline networks, Delta networks, Omega networks and Flip networks have been widely studied particularly for self routing packet switching applications. Also Benes Networks with radix of two have been widely studied and it is known that Benes Networks of radix two are shown to be built with back to back baseline networks which are rearrangeably nonblocking for unicast connections.

The most commonly used VLSI layout in an integrated circuit is based on a two- dimensional grid model comprising only horizontal and vertical tracks. An intuitive interconnection network that utilizes two-dimensional grid model is 2D Mesh Network and its variations such as segmented mesh networks. Hence routing networks used in VLSI layouts are typically 2D mesh networks and its variations. However Mesh Networks require large scale cross points typically with a growth rate of O(N²) where N is the number of computing elements, ports, or logic elements depending on the application.

Multi-stage interconnection with a growth rate of O(N x log N) requires significantly small number of cross points. U.S. Patent 6,185,220 entitled "Grid Layouts of Switching and Sorting Networks" granted to Muthukrishnan et al. describes a VLSI layout using existing VLSI grid model for Benes and Butterfly networks. U.S. Patent 6,940,308 entitled "Interconnection Network for a Field Programmable Gate Array" granted to Wong describes a VLSI layout where switches belonging to lower stage of Benes Network are layed out close to the logic cells and switches belonging to higher stages are layed out towards the center of the layout. Due to the inefficient and in some cases impractical VLSI layout of Benes and butterfly fat tree networks on a semiconductor chip, today mesh networks and segmented mesh networks are widely used in the practical applications such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), and parallel computing interconnects. The prior art VLSI layouts of Benes and butterfly fat tree networks and VLSI layouts of mesh networks and segmented mesh networks require large area to implement the switches on the chip, large number of wires, longer wires, with increased power consumption, increased latency of the signals which effect the maximum clock speed of operation. Some networks may not even be implemented practically on a chip due to the lack of efficient layouts.

SUMMARY OF INVENTION

When large scale sub-integrated circuit blocks with inlet and outlet links are layed out in an integrated circuit device in a two-dimensional grid arrangement, (for example in an FPGA where the sub-integrated circuit blocks are Lookup Tables) the most intuitive routing network is a network that uses horizontal and vertical links only (the most often used such a network is one of the variations of a 2D Mesh network). A direct embedding of a generalized multi-stage network on to a 2D Mesh network is neither simple nor efficient.

In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. The VLSI layouts presented are applicable to generalized multi-stage networks

V(N₁ , N₂ , d, s) , generalized folded multi-stage networks V_fold (N₁ , N₂ , d, s) , generalized butterfly fat tree networks V_bft (N₁ , N₂ , d, s) , generalized multi-link multi-stage networks V_mlmk (N₁ ,N₂ , d, s) , generalized folded multi-link multi-stage networks V_foi_d-_mii_nk (N₁ , N ₂ , d , s) , generalized multi-link butterfly fat tree networks

V_mlmk__bβ (N₁ , N₂ , d, s) , and generalized hypercube networks V_hcube (N₁ , N₂, d, s) for s =

1,2,3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.

BRIEF DESCRIPTION OF DRAWINGS

FIG. IA is a diagram IOOA of an exemplary symmetrical multi-link multi-stage network V_fold__mlmk (N, d, s) having inverse Benes connection topology of nine stages with

Ν = 32, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention.

FIG. IB is a diagram IOOB of the equivalent symmetrical folded multi-link multistage network V_fold__mlιnk (N,d, s) of the network IOOA shown in FIG. IA, having inverse

Benes connection topology of five stages with Ν = 32, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan- out multicast connections, in accordance with the invention.

FIG. 1C is a diagram IOOC layout of the network V_fold__mlmk (N,d, s) shown in FIG.

IB, in one embodiment, illustrating the connection links belonging with in each block only. FIG. ID is a diagram IOOD layout of the network V_fold__mlmk (N,d, s) shown in

FIG. IB, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 64] and ML(8,i) for i = [1,64].

FIG. IE is a diagram IOOE layout of the network V_fold__mlιnk (N, d, s) shown in FIG. IB, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 64] and ML(7,i) for i = [1,64].

FIG. IF is a diagram IOOF layout of the network V_fold__mlmk (N,d, s) shown in FIG.

IB, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and ML(6,i) for i = [1,64].

FIG. IG is a diagram IOOG layout of the network V_fold__mlmk (N, d, s) shown in

FIG. IB, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and ML(5,i) for i = [1,64].

FIG. IH is a diagram IOOH layout of a network V_fM__mlmk (N, d, s) where Ν = 128, d = 2, and s = 2, in one embodiment, illustrating the connection links belonging with in each block only.

FIG. II is a diagram 1001 detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) .

FIG. IJ is a diagram 10OJ detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) .

FIG. IK is a diagram IOOK detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) . FIG. IKl is a diagram 100Ml detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) for s = 1.

FIG. IL is a diagram IOOL detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) .

FIG. ILl is a diagram IOOLI detailed connections of BLOCK 1_2 in the network layout IOOC in one embodiment, illustrating the connection links going in and coming out when the layout IOOC is implementing V(N, d, s) or V_fold (N, d, s) for s = 1.

FIG. 2Al is a diagram 200Al of an exemplary symmetrical multi-link multi-stage network V_fold__mlιnk (N, d, s) having inverse Benes connection topology of one stage with Ν

= 2, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG. 2A2 is a diagram 200A2 of the equivalent symmetrical folded multi-link multi-stage network V_fold__mlmk(N, d, s) of the network

200Al shown in FIG. 2Al, having inverse Benes connection topology of one stage with Ν = 2, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG. 2A3 is a diagram 200A3 layout of the network V _foi_d-_mhnk (N, d, s) shown in FIG. 2A2, in one embodiment, illustrating all the connection links.

FIG. 2Bl is a diagram 200B 1 of an exemplary symmetrical multi-link multi-stage network V_fold__mlmk (N, d, s) having inverse Benes connection topology of one stage with Ν

= 4, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG. 2B2 is a diagram 200B2 of the equivalent symmetrical folded multi-link multi-stage network V_fold__mlmk (N, d, s) of the network 200B 1 shown in FIG. 2B 1 , having inverse Benes connection topology of one stage with N = 4, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG. 2B3 is a diagram 200B3 layout of the network V_foi_d-_mi_mk(N, d, s) shown in FIG. 2B2, in one embodiment, illustrating the connection links belonging with in each block only. FIG. 2B4 is a diagram 200B4 layout of the network V_fold__mlιnk (N, d, s) shown in FIG. 2B2, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 8] and ML(2,i) for i = [1,8].

FIG. 2C 11 is a diagram 200C 11 of an exemplary symmetrical multi-link multi- stage network V_fold__mlιnk (N, d, s) having inverse Benes connection topology of one stage with N = 8, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention. FIG. 2Cl 2 is a diagram 200C 12 of the equivalent symmetrical folded multi-link multi-stage network V_fold__mlmk (N, d, s) of the network 200C 11 shown in FIG. 2Cl 1, having inverse Benes connection topology of one stage with N = 8, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention.

FIG. 2C21 is a diagram 200C21 layout of the network V_fold__mlιnk (N, d, s) shown in FIG. 2Cl 2, in one embodiment, illustrating the connection links belonging with in each block only. FIG. 2C22 is a diagram 200C22 layout of the network V_fM__mlmk (N, d, s) shown in FIG. 2Cl 2, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 16] and ML(4,i) for i = [1,16]. FIG. 2C23 is a diagram 200C23 layout of the network V_fold__mlmk (N, d, s) shown in FIG. 2C12, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 16] and ML(3,i) for i = [1,16].

FIG. 2Dl is a diagram 200Dl of an exemplary symmetrical multi-link multi-stage network V_fold__mlmk (N, d, s) having inverse Benes connection topology of one stage with N

= 16, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention.

FIG. 2D2 is a diagram 200D2 of the equivalent symmetrical folded multi-link multi-stage network V_fold__mlιnk(N, d, s) of the network 200Dl shown in FIG. 2Dl, having inverse Benes connection topology of one stage with N = 16, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention.

FIG. 2D3 is a diagram 200D3 layout of the network V_fold__mlmk (N,d, s) shown in

FIG. 2D2, in one embodiment, illustrating the connection links belonging with in each block only.

FIG. 2D4 is a diagram 200D4 layout of the network V_fold__mlmk (N, d, s) shown in

FIG. 2D2, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 32] and ML(6,i) for i = [1,32].

FIG. 2D5 is a diagram 200D5 layout of the network V_fold__mlmk (N, d, s) shown in FIG. 2D2, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 32] and ML(5,i) for i = [1,32].

FIG. 2D6 is a diagram 200D6 layout of the network V_fold__mlmk (N,d, s) shown in

FIG. 2D2, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 32] and ML(4,i) for i = [1,32].

FIG. 3A is a diagram 300A of an exemplary symmetrical multi-link multi-stage network V_hcube(N,d, s) having inverse Benes connection topology of nine stages with N =

32, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in accordance with the invention.

FIG. 3B is a diagram 300B of the equivalent symmetrical folded multi-link multistage network V_hcube(N,d, s) of the network 300A shown in FIG. 3 A, having inverse Benes connection topology of five stages with N = 32, d = 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably nonblocking network for arbitrary fan- out multicast connections, in accordance with the invention.

FIG. 3C is a diagram 300C layout of the network V_hcube(N,d, s) shown in FIG. 3B, in one embodiment, illustrating the connection links belonging with in each block only.

FIG. 3D is a diagram IOOD layout of the network V_hcube(N,d, s) shown in FIG.

3B, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 64] and ML(8,i) for i = [1,64].

FIG. 3E is a diagram 300E layout of the network V_hcube (N, d, s) shown in FIG.

3B, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 64] and ML(7,i) for i = [1,64].

FIG. 3F is a diagram 300F layout of the network V_hcube (N, d, s) shown in FIG. 3B, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and ML(6,i) for i = [1,64].

FIG. 3G is a diagram 300G layout of the network V_hcube(N, d, s) shown in FIG.

3B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and ML(5,i) for i = [1,64].

FIG. 3H is a diagram 300H layout of a network V_hcube(N, d, s) where N = 128, d = 2, and s = 2, in one embodiment, illustrating the connection links belonging with in each block only.

FIG. 4A is a diagram 400A layout of the network V_fold__mlmk (N,d, s) shown in

FIG. IB, in one embodiment, illustrating the connection links belonging with in each block only. FIG. 4B is a diagram 400B layout of the network V_foId__mhnk (N, d, s) shown in FIG.

IB, in one embodiment, illustrating the connection links ML(I, i) for i = [1, 64] and ML(8,i) for i = [1,64].

FIG. 4C is a diagram 400C layout of the network V_fold__mlmk (N, d, s) shown in FIG. 4C, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 64] and ML(7,i) for i = [1,64].

FIG. 4D is a diagram 400D layout of the network V_fold__mlmk (N,d, s) shown in

FIG. 4D, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and ML(6,i) for i = [1,64].

FIG. 4E is a diagram 400E layout of the network V_fold__mlmk (N, d, s) shown in FIG.

4E, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and ML(5,i) for i = [1,64].

FIG. 4Cl is a diagram 400Cl layout of the network V_fold__mlmk (N, d, s) shown in

FIG. IB, in one embodiment, illustrating the connection links belonging with in each block only.

FIG. 5Al is a diagram 500Al of an exemplary prior art implementation of a two by two switch; FIG. 5A2 is a diagram 500A2 for programmable integrated circuit prior art implementation of the diagram 500Al of FIG. 5Al; FIG. 5A3 is a diagram 500A3 for one-time programmable integrated circuit prior art implementation of the diagram 500Al of FIG. 5Al; FIG. 5A4 is a diagram 500A4 for integrated circuit placement and route implementation of the diagram 500Al of FIG. 5Al.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is concerned with the VLSI layouts of arbitrarily large switching networks for broadcast, unicast and multicast connections. Particularly switching networks considered in the current invention include: generalized multi-stage networks V(N₁ , N₂ , d, s) , generalized folded multi-stage networks V_fold (N₁ , N₂ , d, s) , generalized butterfly fat tree networks V_bft (N₁ , N₂ , d, s) , generalized multi-link multistage networks V_mlmk (N₁ , N₂ ,d, s) , generalized folded multi-link multi-stage networks V_foi_d-_mi_mk (N₁ , N₂ , d, s) , generalized multi-link butterfly fat tree networks v_mi_mk-_bfl (N₁ , N₂ , d, s) , and generalized hypercube networks V_hcube (N₁ , N₂, d, s) for s = 1,2,3 or any number in general.

Efficient VLSI layout of networks on a semiconductor chip are very important and greatly influence many important design parameters such as the area taken up by the network on the chip, total number of wires, length of the wires, latency of the signals, capacitance and hence the maximum clock speed of operation. Some networks may not even be implemented practically on a chip due to the lack of efficient layouts. The different varieties of multi-stage networks described above have not been implemented previously on the semiconductor chips efficiently. For example in Field Programmable Gate Array (FPGA) designs, multi-stage networks described in the current invention have not been successfully implemented primarily due to the lack of efficient VLSI layouts. Current commercial FPGA products such as Xilinx Vertex, Altera' s Stratix implement island-style architecture using mesh and segmented mesh routing interconnects using either full crossbars or sparse crossbars. These routing interconnects consume large silicon area for crosspoints, long wires, large signal propagation delay and hence consume lot of power.

The current invention discloses the VLSI layouts of numerous types of multistage networks which are very efficient. Moreover they can be embedded on to mesh and segmented mesh routing interconnects of current commercial FPGA products. The VLSI layouts disclosed in the current invention are applicable to including the numerous generalized multi-stage networks disclosed in the following patent applications, filed concurrently:

1) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-stage networks V(N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in the PCT Application Serial No. PCT/US08/56064 that is incorporated by reference above.

2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized butterfly fat tree networks V_bft (N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in U.S.

Provisional Patent Application Serial No. 60/940, 387 that is incorporated by reference above.

3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and strictly nonblocking for unicast for generalized multi-link multi-stage networks V_mhnk (N₁ ,N₂ , d, s) and generalized folded multi-link multi-stage networks

V_foi_d-_mi_mk (N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in U.S. Provisional Patent Application Serial No. 60/940, 389 that is incorporated by reference above.

4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized multi-link butterfly fat tree networks V_mlmk__bft (N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in U.S. Provisional Patent Application Serial No. 60/940, 390 that is incorporated by reference above.

5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and unicast for generalized folded multi-stage networks V^_y (N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in U.S. Provisional Patent Application Serial No. 60/940, 391 that is incorporated by reference above.

6) Strictly nonblocking for arbitrary fan-out multicast for generalized multi-link multi-stage networks V_mlmk (N₁, N₂ ,d, s) and generalized folded multi-link multi-stage networks V_fold__mlmk (N₁ , N₂ , d, s) with numerous connection topologies and the scheduling methods are described in detail in U.S. Provisional Patent Application Serial No. 60/940, 392 that is incorporated by reference above.

7) VLSI layouts of numerous types of multi-stage networks with locality exploitation are described in U.S. Provisional Patent Application Serial No. 60/984, 724 that is incorporated by reference above.

8) VLSI layouts of numerous types of multistage pyramid networks are described in U.S. Provisional Patent Application Serial No. 61/018, 494 that is incorporated by reference above.

In addition the layouts of the current invention are also applicable to generalized multi-stage pyramid networks V_p (N₁ , N₂ , d, s) , generalized folded multi-stage pyramid networks V_fold_ (N₁ , N₂ , d, s) , generalized butterfly fat pyramid networks V_bf (N₁ , N₂ , d, s) , generalized multi-link multi-stage pyramid networks V_mlmk__p (N₁ , N₂ ,d, s) , generalized folded multi-link multi-stage pyramid networks V_foi_d-_mi_mk-_p (N₁ , N₂ , d, s) , generalized multi-link butterfly fat pyramid networks V_mi_mk-_bfP (N₁, N₂ , d, s) , and generalized hypercube networks V_hcube (N₁ , N₂, d, s) for s = 1,2,3 or any number in general.

Symmetric RΝB generalized multi-link multi-stage network V_1n^(N₁, N₂, d,s) :

Referring to diagram IOOA in FIG. IA, in one embodiment, an exemplary generalized multi-link multi-stage network V_mlmk (N₁ , N₂ ,d, s) where Ni = Ν₂ = 32; d =

2; and s = 2 with nine stages of one hundred and forty four switches for satisfying communication requests, such as setting up a telephone call or a data call, or a connection between configurable logic blocks, between an input stage 110 and output stage 120 via middle stages 130, 140, 150, 160, 170, 180 and 190 is shown where input stage 110 consists of sixteen, two by four switches ISl -IS 16 and output stage 120 consists of sixteen, four by two switches OSl -OS 16. And all the middle stages namely the middle stage 130 consists of sixteen, four by four switches MS(I₅I) - MS(1, 16), middle stage 140 consists of sixteen, four by four switches MS(2,1) - MS(2,16), middle stage 150 consists of sixteen, four by four switches MS(3,1) - MS(3,16), middle stage 160 consists of sixteen, four by four switches MS(4,1) - MS(4,16), middle stage 170 consists of sixteen, four by four switches MS(5,1) - MS(5,16), middle stage 180 consists of sixteen, four by four switches MS(6,1) - MS(6,16), and middle stage 190 consists of sixteen, four by four switches MS(7,1) - MS(7,16).

As disclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is incorporated by reference above, such a network can be operated in rearrangeably non- blocking manner for arbitrary fan-out multicast connections and also can be operated in strictly non-blocking manner for unicast connections.

In one embodiment of this network each of the input switches IS 1 -IS4 and output switches OS1-OS4 are crossbar switches. The number of switches of input stage 110 and

N of output stage 120 can be denoted in general with the variable — , where N is the total d number of inlet links or outlet links. The number of middle switches in each middle stage

N is denoted by — . The size of each input switch IS1-IS4 can be denoted in general with d the notation d * 2d and each output switch OS1-OS4 can be denoted in general with the notation 2d * d . Likewise, the size of each switch in any of the middle stages can be denoted as 2d * 2d . A switch as used herein can be either a crossbar switch, or a network of switches each of which in turn may be a crossbar switch or a network of switches. A symmetric multi-stage network can be represented with the notation V_mlmk (N, d, s) , where N represents the total number of inlet links of all input switches

(for example the links IL1-IL32), d represents the inlet links of each input switch or outlet links of each output switch, and s is the ratio of number of outgoing links from each input switch to the inlet links of each input switch.

N

Each of the — input switches ISl - IS 16 are connected to exactly d switches in

middle stage 130 through two links each for a total of 2x d links (for example input switch ISl is connected to middle switch MS(I₅I) through the links ML(I₅I), ML(1, 2), and also connected to middle switch MS(1,2) through the links ML(1, 3) and ML(1, 4)). The middle links which connect switches in the same row in two successive middle stages are called hereinafter straight middle links; and the middle links which connect switches in different rows in two successive middle stages are called hereinafter cross middle links. For example, the middle links ML(1,1) and ML(1, 2) connect input switch ISl and middle switch MS(1, 1), so middle links ML(1, 1) and ML(1, 2) are straight middle links; where as the middle links ML(1, 3) and ML(1, 4) connect input switch ISl and middle switch MS(1, 2), since input switch ISl and middle switch MS(1,2) belong to two different rows in diagram IOOA of FIG. IA, middle links ML(1, 3) and ML(1,4) are cross middle links.

N

Each of the — middle switches MS(1, 1) - MS(1, 16) in the middle stage 130 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(1, 1) and ML(1,2) are connected to the middle switch MS(1, 1) from input switch ISl, and the links ML(1, 7) and ML(1, 8) are connected to the middle switch MS(1, 1) from input switch IS2) and also are connected to exactly d switches in middle stage 140 through two links each for a total of 2x d links (for example the links ML(2,1) and ML(2,2) are connected from middle switch MS(1, 1) to middle switch MS(2,1), and the links ML(2,3) and ML(2,4) are connected from middle switch MS(1,1) to middle switch MS(2,3)).

N

Each of the — middle switches MS(2,1) - MS(2,16) in the middle stage 140 are d connected from exactly d input switches through two links each for a total of 2 X d links (for example the links ML(2,1) and ML(2,2) are connected to the middle switch MS(2,1) from input switch MS(1, 1), and the links ML(I₅I l) and ML(1, 12) are connected to the middle switch MS(2,1) from input switch MS(1, 3)) and also are connected to exactly d switches in middle stage 150 through two links each for a total of 2 x d links (for example the links ML(3,1) and ML(3,2) are connected from middle switch MS(2,1) to middle switch MS(3,1), and the links ML(3,3) and ML(3,4) are connected from middle switch MS(2,1) to middle switch MS(3,5)). N

Each of the — middle switches MS(3,1) - MS(3,16) in the middle stage 150 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(3,1) and ML(3,2) are connected to the middle switch MS(3,1) from input switch MS(2,1), and the links ML(2,19) and ML(2,20) are connected to the middle switch MS(3,1) from input switch MS(2,5)) and also are connected to exactly d switches in middle stage 160 through two links each for a total of 2 x d links (for example the links ML(4,1) and ML(4,2) are connected from middle switch MS(3,1) to middle switch MS(4,1), and the links ML(4,3) and ML(4,4) are connected from middle switch MS(3,1) to middle switch MS(4,9)).

Each of the — middle switches MS(4,1) - MS(4,16) in the middle stage 160 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(4,1) and ML(4,2) are connected to the middle switch MS(4,1) from input switch MS(3,1), and the links ML(4,35) and ML(4,36) are connected to the middle switch MS(4,1) from input switch MS(3,9)) and also are connected to exactly d switches in middle stage 170 through two links each for a total of 2x d links (for example the links ML(5,1) and ML(5,2) are connected from middle switch MS(4,1) to middle switch MS(5,1), and the links ML(5,3) and ML(5,4) are connected from middle switch MS(4,1) to middle switch MS(5,9)).

N

Each of the — middle switches MS(5,1) - MS(5,16) in the middle stage 170 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(5,1) and ML(5,2) are connected to the middle switch MS(5,1) from input switch MS(4,1), and the links ML(5,35) and ML(5,36) are connected to the middle switch MS(5,1) from input switch MS(4,9)) and also are connected to exactly d switches in middle stage 180 through two links each for a total of 2 x d links (for example the links ML(6,1) and ML(6,2) are connected from middle switch MS(5,1) to middle switch MS(6,1), and the links ML(6,3) and ML(6,4) are connected from middle switch MS(5,1) to middle switch MS(6,5)). N

Each of the — middle switches MS(6,1) - MS(6,16) in the middle stage 180 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(6,1) and ML(6,2) are connected to the middle switch MS(6,1) from input switch MS(5,1), and the links ML(6,19) and ML(6,20) are connected to the middle switch MS(6,1) from input switch MS(5,5)) and also are connected to exactly d switches in middle stage 190 through two links each for a total of 2x d links (for example the links ML(7,1) and ML(7,2) are connected from middle switch MS(6,1) to middle switch MS(7,1), and the links ML(7,3) and ML(7,4) are connected from middle switch MS(6,1) to middle switch MS(7,3)).

Each of the — middle switches MS(7,1) - MS(7,16) in the middle stage 190 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(7,1) and ML(7,2) are connected to the middle switch MS(7,1) from input switch MS(6,1), and the links ML(7,11) and ML(7,12) are connected to the middle switch MS(7,1) from input switch MS(6,3)) and also are connected to exactly d switches in middle stage 120 through two links each for a total of 2x d links (for example the links ML(8,1) and ML(8,2) are connected from middle switch MS(7,1) to middle switch MS(8,1), and the links ML(8,3) and ML(8,4) are connected from middle switch MS(7,1) to middle switch OS2).

N

Each of the — middle switches OSl - OS 16 in the middle stage 120 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(8,1) and ML(8,2) are connected to the output switch OSl from input switch MS(7,1), and the links ML(8,7) and ML(7,8) are connected to the output switch OSl from input switch MS(7,2)).

Finally the connection topology of the network IOOA shown in FIG. IA is known to be back to back inverse Benes connection topology.

Referring to diagram IOOB in FIG. IB, is a folded version of the multi-link multistage network IOOA shown in FIG. IA. The network IOOB in FIG. IB shows input stage 110 and output stage 120 are placed together. That is input switch ISl and output switch OSl are placed together, input switch IS2 and output switch OS2 are placed together, and similarly input switch IS 16 and output switch OS 16 are placed together. All the right going middle links (hereinafter "forward connecting links") {i.e., inlet links ILl - IL32 and middle links ML(1, 1) - ML(1, 64)} correspond to input switches ISl - IS16, and all the left going middle links (hereinafter "backward connecting links") {i.e., middle links ML(8,1) - ML(8,64) and outlet links OL1-OL32} correspond to output switches OSl - OS16.

Middle stage 130 and middle stage 190 are placed together. That is middle switches MS(1, 1) and MS(7,1) are placed together, middle switches MS(1,2) and

MS(7,2) are placed together, and similarly middle switches MS(1, 16) and MS(7,16) are placed together. All the right going middle links {i.e., middle links ML(1, 1) - ML(1, 64) and middle links ML(2,1) - ML(2,64)} correspond to middle switches MS(1, 1) - MS(1, 16), and all the left going middle links {i.e., middle links ML(7,1) - ML(7,64) and middle links ML(8,1) and ML(8,64)} correspond to middle switches MS(7,1) - MS(7,16).

Middle stage 140 and middle stage 180 are placed together. That is middle switches MS(2,1) and MS(6,1) are placed together, middle switches MS(2,2) and MS(6,2) are placed together, and similarly middle switches MS(2,16) and MS(6,16) are placed together. All the right going middle links {i.e., middle links ML(2,1) - ML(2,64) and middle links ML(3,1) - ML(3,64)} correspond to middle switches MS(2,1) - MS(2,16), and all the left going middle links {i.e., middle links ML(6,1) - ML(6,64) and middle links ML(7,1) and ML(7,64)} correspond to middle switches MS(6,1) - MS(6,16).

Middle stage 150 and middle stage 170 are placed together. That is middle switches MS(3,1) and MS(5,1) are placed together, middle switches MS(3,2) and MS(5,2) are placed together, and similarly middle switches MS(3,16) and MS(5,16) are placed together. All the right going middle links {i.e., middle links ML(3,1) - ML(3,64) and middle links ML(4,1) - ML(4,64)} correspond to middle switches MS(3,1) - MS(3,16), and all the left going middle links {i.e., middle links ML(5,1) - ML(5,64) and middle links ML(6,1) and ML(6,64)} correspond to middle switches MS(5,1) - MS(5,16).

Middle stage 160 is placed alone. All the right going middle links are the middle links ML(4,1) - ML(4,64) and all the left going middle links are middle links ML(5,1) - ML(5,64).

In one embodiment, in the network IOOB of FIG. IB, the switches that are placed together are implemented as separate switches then the network IOOB is the generalized folded multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a two by four switch and a four by two switch. For example the switch input switch IS 1 and output switch OS 1 are placed together; so input switch IS 1 is implemented as two by four switch with the inlet links ILl and IL2 being the inputs of the input switch ISl and middle links ML(1, 1) - ML(1, 4) being the outputs of the input switch ISl; and output switch OSl is implemented as four by two switch with the middle links ML(8,1), ML(8,2), ML(8,7) and ML(8,8) being the inputs of the output switch OSl and outlet links OLl - OL2 being the outputs of the output switch OSl. Similarly in this embodiment of network IOOB all the switches that are placed together in each middle stage are implemented as separate switches.

Hypercube Topology layout schemes:

Referring to layout IOOC of FIG. 1C, in one embodiment, there are sixteen blocks namely Block 1_2, Block 3_4, Block 5_6, Block 7_8, Block 9_10, Block 11_12, Block 13_14, Block 15_16, Block 17_18, Block 19_20, Block 21_22, Block 23_24, Block 25_26, Block 27_28, Block 29_30, and Block 31_32. Each block implements all the switches in one row of the network IOOB of FIG. IB, one of the key aspects of the current invention. For example Block 1_2 implements the input switch ISl, output Switch OSl, middle switch MS(I₅I), middle switch MS(7,1), middle switch MS(2,1), middle switch MS(6,1), middle switch MS(3,1), middle switch MS(5,1), and middle switch MS(4,1). For the simplification of illustration, Input switch ISl and output switch OSl together are denoted as switch 1; Middle switch MS(1, 1) and middle switch MS(7,1) together are denoted by switch 2; Middle switch MS(2,1) and middle switch MS(6,1) together are denoted by switch 3; Middle switch MS(3,1) and middle switch MS(5,1) together are denoted by switch 4; Middle switch MS(4,1) is denoted by switch 5.

All the straight middle links are illustrated in layout IOOC of FIG. 1C. For example in Block 1_2, inlet links ILl - IL2, outlet links OLl - 0L2, middle link ML(1, 1), middle link ML(1,2), middle link ML(8,1), middle link ML(8,2), middle link ML(2,1), middle link ML(2,2), middle link ML(7,1), middle link ML(7,2), middle link ML(3,1), middle link ML(3,2), middle link ML(6,1), middle link ML(6,2), middle link ML(4,1), middle link ML(4,2), middle link ML(5,1) and middle link ML(5,2) are illustrated in layout IOOC of FIG. 1C.

Even though it is not illustrated in layout IOOC of FIG. 1C, in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit (hereinafter "sub-integrated circuit block") depending on the applications in different embodiments. There are four quadrants in the layout IOOC of FIG. 1C namely top-left, bottom-left, top-right and bottom-right quadrants. Top-left quadrant implements Block 1_2, Block 3_4, Block 5_6, and Block 7_8. Bottom-left quadrant implements Block 9_10, Block 11_12, Block 13_14, and Block 15_16. Top-right quadrant implements Block 17_18, Block 19_20, Block 21_22, and Block 23_24. Bottom-right quadrant implements Block 25_26, Block 27_28, Block 29_30, and Block 31_32. There are two halves in layout IOOC of FIG. 1C namely left-half and right-half. Left-half consists of top-left and bottom-left quadrants. Right-half consists of top-right and bottom- right quadrants.

Recursively in each quadrant there are four sub-quadrants. For example in top-left quadrant there are four sub-quadrants namely top-left sub-quadrant, bottom-left sub- quadrant, top-right sub-quadrant and bottom-right sub-quadrant. Top-left sub-quadrant of top-left quadrant implements Block 1_2. Bottom-left sub-quadrant of top-left quadrant implements Block 3_4. Top-right sub-quadrant of top-left quadrant implements Block 5_6. Finally bottom-right sub-quadrant of top-left quadrant implements Block 7_8. Similarly there are two sub-halves in each quadrant. For example in top-left quadrant there are two sub-halves namely left-sub-half and right- sub-half. Left-sub-half of top-left quadrant implements Block 1_2 and Block 3_4. Right-sub-half of top-left quadrant implements Block 5_6 and Block 7_8. Finally applicant notes that in each quadrant or half the blocks are arranged as a general binary hypercube. Recursively in larger multistage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = Ν₂ > 32, the layout in this embodiment in accordance with the current invention, will be such that the super-quadrants will also be arranged in d-ary hypercube manner. (In the embodiment of the layout IOOC of FIG. 1C, it is binary hypercube manner since d = 2, in the network V_fold__mlmk (N₁ , N₂ , d, s) lOOB of FIG. IB).

Layout IOOD of FIG. ID illustrates the inter-block links between switches 1 and 2 of each block. For example middle links ML(1,3), ML(1, 4), ML(8,7), and ML(8,8) are connected between switch 1 of Block 1_2 and switch 2 of Block 3_4. Similarly middle links ML(IJ), ML(1, 8), ML(8,3), and ML(8,4) are connected between switch 2 of Block 1_2 and switch 1 of Block 3_4. Applicant notes that the inter-block links illustrated in layout IOOD of FIG. ID can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(1,4) and ML(8,8) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(1, 4) and ML(8,8) are implemented as a time division multiplexed single track).

Layout IOOE of FIG. IE illustrates the inter-block links between switches 2 and 3 of each block. For example middle links ML(2,3), ML(2,4), ML(7,11), and ML(7,12) are connected between switch 2 of Block 1_2 and switch 3 of Block 3_4. Similarly middle links ML(2,11), ML(2,12), ML(7,3), and ML(7,4) are connected between switch 3 of Block 1_2 and switch 2 of Block 3_4. Applicant notes that the inter-block links illustrated in layout IOOE of FIG. IE can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(2,12) and ML(7,4) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(2,12) and ML(7,4) are implemented as a time division multiplexed single track).

Layout IOOF of FIG. IF illustrates the inter-block links between switches 3 and 4 of each block. For example middle links ML(3,3), ML(3,4), ML(6,19), and ML(6,20) are connected between switch 3 of Block 1_2 and switch 4 of Block 3_4. Similarly middle links ML(3,19), ML(3,20), ML(6,3), and ML(6,4) are connected between switch 4 of Block 1_2 and switch 3 of Block 3_4. Applicant notes that the inter-block links illustrated in layout IOOF of FIG. IF can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(3,4) and ML(6,20) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(3,4) and ML(6,20) are implemented as a time division multiplexed single track).

Layout IOOG of FIG. IG illustrates the inter-block links between switches 4 and 5 of each block. For example middle links ML(4,3), ML(4,4), ML(5,35), and ML(5,36) are connected between switch 4 of Block 1_2 and switch 5 of Block 3_4. Similarly middle links ML(4,35), ML(4,36), ML(5,3), and ML(5,4) are connected between switch 5 of Block 1_2 and switch 4 of Block 3_4. Applicant notes that the inter-block links illustrated in layout IOOG of FIG. IG can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(4,4) and ML(5,36) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(4,4) and ML(5,36) are implemented as a time division multiplexed single track).

The complete layout for the network IOOB of FIG. IB is given by combining the links in layout diagrams of lOOC, 10OD, 10OE, IOOF, and IOOG. Applicant notes that in the layout IOOC of FIG. 1C, the inter-block links between switch 1 and switch 2 of corresponding blocks are vertical tracks as shown in layout IOOD of FIG. ID; the inter- block links between switch 2 and switch 3 of corresponding blocks are horizontal tracks as shown in layout IOOE of FIG. IE; the inter-block links between switch 3 and switch 4 of corresponding blocks are vertical tracks as shown in layout IOOF of FIG. IF; and finally the inter-block links between switch 4 and switch 5 of corresponding blocks are horizontal tracks as shown in layout IOOG of FIG. IG. The pattern is alternate vertical tracks and horizontal tracks. It continues recursively for larger networks of N > 32 as will be illustrated later.

Some of the key aspects of the current invention are discussed. 1) All the switches in one row of the multi-stage network IOOB are implemented in a single block. 2) The blocks are placed in such a way that all the inter-block links are either horizontal tracks or vertical tracks; 3) Since all the inter-block links are either horizontal or vertical tracks, all the inter-block links can be mapped on to island-style architectures in current commercial FPGA' s; 4) The length of the longest wire is about half of the width (or length) of the complete layout (For example middle link ML(4,4) is about half the width of the complete layout).

In accordance with the current invention, the layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized folded multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) the sub-quadrants, quadrants, and super-quadrants are arranged in d-ary hypercube manner and also the inter-blocks are accordingly connected in d-ary hypercube topology. Even though all the embodiments in the current invention are illustrated for N₁ = N₂ , the embodiments can be extended for N₁ ≠ N₂.

Referring to layout IOOH of FIG. IH, illustrates the extension of layout IOOC for the network V_foM__mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 128; d = 2; and s = 2. There are four super-quadrants in layout IOOH namely top-left super-quadrant, bottom-left super- quadrant, top-right super-quadrant, bottom-right super-quadrant. Total number of blocks in the layout IOOH is sixty four. Top-left super-quadrant implements the blocks from block 1_2 to block 31_32. Each block in all the super-quadrants has two more switches namely switch 6 and switch 7 in addition to the switches [1-5] illustrated in layout IOOC of FIG. 1C. The inter-block link connection topology is the exactly the same between the switches 1 and 2; switches 2 and 3; switches 3 and 4; switches 4 and 5 as it is shown in the layouts of FIG. ID, FIG. IE, FIG. IF, and FIG. IG respectively.

Bottom-left super-quadrant implements the blocks from block 33_34 to block 63_64. Top-right super-quadrant implements the blocks from block 65_66 to block 95_96. And bottom-right super-quadrant implements the blocks from block 97_98 to block 127_128. In all these three super-quadrants also, the inter-block link connection topology is the exactly the same between the switches 1 and 2; switches 2 and 3; switches 3 and 4; switches 4 and 5 as that of the top-left super-quadrant.

Recursively in accordance with the current invention, the inter-block links connecting the switch 5 and switch 6 will be vertical tracks between the corresponding switches of top-left super-quadrant and bottom-left super-quadrant. And similarly the inter-block links connecting the switch 5 and switch 6 will be vertical tracks between the corresponding switches of top-right super-quadrant and bottom-right super-quadrant. The inter-block links connecting the switch 6 and switch 7 will be horizontal tracks between the corresponding switches of top-left super-quadrant and top-right super-quadrant. And similarly the inter-block links connecting the switch 6 and switch 7 will be horizontal tracks between the corresponding switches of bottom-left super-quadrant and bottom- right super-quadrant.

Referring to diagram 1001 of FIG. II illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) of the layout IOOC of FIG. 1C which represents a generalized folded multi-link multi-stage network V_foi_d-_mi_mk (^Ni ^₂ , d, ^s) ^where Ni = N₂ = 32; d = 2; and s = 2. Block 1_2 in 1001 illustrates both the intra-block and inter-block links connected to Block 1_2. The layout diagram 1001 corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network IOOB of FIG. IB. As noted before then the network IOOB is the generalized folded multi-link multi-stage network V_foi_d-_mi_mk (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is incorporated by reference above. That is the switches that are placed together in Block 1_2 as shown in FIG. II are namely input switch ISl and output switch OSl belonging to switch 1, illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switches implemented are input switch ISl and output switch OSl); middle switch MS(1, 1) and middle switch MS(7,1) belonging to switch 2; middle switch MS(2,1) and middle switch MS(6,1) belonging to switch 3; middle switch MS(3,1) and middle switch MS(5,1) belonging to switch 4; And middle switch MS(4,1) belonging to switch 5.

Input switch ISl is implemented as two by four switch with the inlet links ILl and IL2 being the inputs of the input switch ISl and middle links ML(1,1) - ML(1, 4) being the outputs of the input switch ISl ; and output switch OSl is implemented as four by two switch with the middle links ML(8,1) - ML(8,4) being the inputs of the output switch OSl and outlet links OLl - 0L2 being the outputs of the output switch OSl.

Middle switch MS(1, 1) is implemented as four by four switch with the middle links ML(1, 1), ML(1,2), ML(1, 7) and ML(1, 8) being the inputs and middle links ML(2,1) - ML(2,4) being the outputs; and middle switch MS(7,1) is implemented as four by four switch with the middle links ML(7,1), ML(7,2), ML(7,11) and ML(7,12) being the inputs and middle links ML(8,1) - ML(8,4) being the outputs. Similarly all the other middle switches are also implemented as four by four switches as illustrated in 1001 of FIG. II.

Now the VLSI layouts of generalized multi-link multi-stage network V_mlmk (N₁ , N₂ , d, s) where Ni = N₂ < 32; d = 2; s = 2 and its corresponding version of folded generalized multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = N₂

< 32; d = 2; s = 2 are discussed. Referring to diagram 200Al of FIG. 2Al is generalized multi-link multi-stage network V_mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 2; d = 2. Diagram 200A2 of FIG. 2A2 illustrates the corresponding folded generalized multi-link multi- stage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 2; d = 2, version of the diagram

200Al of FIG. 2Al. Layout 200A3 of FIG. 2A3 illustrates the VLSI layout of the network 200A2 of FIG. 2A2. There is only one block i.e., Block 1_2 comprising switch 1. Just like in the layout IOOC of FIG. 1C, switch 1 consists of input switch ISl and output switch OS 1. Referring to diagram 200B 1 of FIG. 2B 1 is generalized multi-link multi-stage network V_mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 4; d = 2; s = 2. Diagram 200B2 of FIG. 2B2 illustrates the corresponding folded generalized multi-link multi-stage network ^v _foi_d-_mi_mk (N₁, N₂ , d, s) where Ni = N₂ = 4; d = 2; s = 2, version of the diagram 200B 1 of FIG. 2B 1. Layout 200B3 of FIG. 2B3 illustrates the VLSI layout of the network 200B2 of FIG. 2B2. There are two blocks i.e., Block 1_2 and Block 3_4 each comprising switch 1 and switch 2. Switch 1 in each block consists of the corresponding input switch and output switch. For example switch 1 in Block 1_2 consists of input switch ISl and output switch OSl. Similarly switch 2 in Block 1_2 consists of middle switch (1,1). Layout 200B4 of FIG. 2B4 illustrates the inter-block links of the VLSI layout diagram 200B3 of FIG. 2B3. For example middle links ML(1, 4) and ML(2,8). It must be noted that all the inter-block links are vertical tracks in this layout. (Alternatively all the inter-blocks can also be implemented as horizontal tracks).

Referring to diagram 200Cl 1 of FIG. 2Cl 1 is generalized multi-link multi-stage network V_mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 8; d = 2; s = 2. Diagram 200C 12 of FIG. 2Cl 2 illustrates the corresponding folded generalized multi-link multi-stage network V_foi_d-_mM (^Ni > ^N ₂ > ^d> ^s) ^where Ni = N₂ = 8; d = 2; s = 2, version of the diagram 200Cl 1 of FIG. 2Cl 1. Layout 200C21 of FIG. 2C21 illustrates the VLSI layout of the network 200C 12 of FIG. 2C12. There are four blocks i.e., Block 1_2, Block 3_4, Block 5_6, and Block 7_8 each comprising switch 1, switch 2 and switch 3. For example switch 1 in Block 1_2 consists of input switch ISl and output switch OSl; Switch 2 in Block 1_2 consists of MS(l,l) and MS(3,l). Switch 3 in Block 1_2 consists of MS(2,1).

Layout 200C22 of FIG. 2C22 illustrates the inter-block links between the switch 1 and switch 2 of the VLSI layout diagram 200C21 of FIG. 2C21. For example middle links ML(1, 4) and ML(4,8) are connected between Block 1_2 and Block 3_4. It must be noted that all the inter-block links between switch 1 and switch 2 of all blocks are vertical tracks in this layout. Layout 200C23 of FIG. 2C23 illustrates the inter-block links between the switch 2 and switch 3 of the VLSI layout diagram 200C21 of FIG. 2C21. For example middle links ML(2,12) and ML(3,4) are connected between Block 1_2 and Block 5_6. It must be noted that all the inter-block links between switch 2 and switch 3 of all blocks are horizontal tracks in this layout

Referring to diagram 200Dl of FIG. 2Dl is generalized multi-link multi-stage network V_mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 16; d = 2; s = 2. Diagram 200D2 of FIG. 2D2 illustrates the corresponding folded generalized multi-link multi-stage network

V_foi_d-_mi_mk (^Ni > ^N ₂ > ^d> ^s) ^where Ni = N₂ = 16; d = 2; s = 2, version of the diagram 200Dl of FIG. 2Dl. Layout 200D3 of FIG. 2D3 illustrates the VLSI layout of the network 200D2 of FIG. 2D2. There are eight blocks i.e., Block 1_2, Block 3_4, Block 5_6, Block 7_8, Block 9_10, Block 11_12, Block 13_14 and Block 15_16 each comprising switch 1, switch 2, switch 3 and switch 4. For example switch 1 in Block 1_2 consists of input switch ISl and output switch OSl ; Switch 2 in Block 1_2 consists of MS(I₅I) and MS(5,1). Switch 3 in Block 1_2 consists of MS(2,1) and MS(4,1), and switch 4 in Block 1_2 consists of MS(3,1).

Layout 200D4 of FIG. 2D4 illustrates the inter-block links between the switch 1 and switch 2 of the VLSI layout diagram 200D3 of FIG. 2D3. For example middle links ML(1, 4) and ML(6,8) are connected between Block 1_2 and Block 3_4. It must be noted that all the inter-block links between switch 1 and switch 2 of all blocks are vertical tracks in this layout. Layout 200D5 of FIG. 2D5 illustrates the inter-block links between the switch 2 and switch 3 of the VLSI layout diagram 200D3 of FIG. 2D3. For example middle links ML(2,12) and ML(5,4) are connected between Block 1_2 and Block 5_6. It must be noted that all the inter-block links between switch 2 and switch 3 of all blocks are horizontal tracks in this layout. Layout 200D6 of FIG. 2D6 illustrates the inter-block links between the switch 3 and switch 4 of the VLSI layout diagram 200D3 of FIG. 2D3. For example middle links ML(3,4) and ML(4,20) are connected between Block 1_2 and Block 9_10. It must be noted that all the inter-block links between switch 3 and switch 4 of all blocks are vertical tracks in this layout.

Generalized Multi-link Butterfly Fat Tree Network Embodiment:

In another embodiment in the network IOOB of FIG. IB, the switches that are placed together are implemented as combined switch then the network IOOB is the generalized multi-link butterfly fat tree network V_mlmk__bfi (N₁ , N₂ , d, s) where Ni = Ν₂ =

32; d = 2; and s = 2 with five stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,390 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a six by six switch. For example the input switch IS 1 and output switch OS 1 are placed together; so input switch IS 1 and output OS 1 are implemented as a six by six switch with the inlet links ILl, IL2, ML(8,1), ML(8,2), ML(8,7) and ML(8,8) being the inputs of the combined switch (denoted as IS1&OS1) and middle links ML(1, 1), ML(1,2), ML(1, 3), ML(1, 4), OLl and OL2 being the outputs of the combined switch IS1&0S1. Similarly in this embodiment of network IOOB all the switches that are placed together are implemented as a combined switch.

Layout diagrams IOOC in FIG. 1C, IOOD in FIG. ID, IOOE in FIG. IE, IOOF in FIG. IG are also applicable to generalized multi-link butterfly fat tree network V_mhnk-_bft (^Ni , N₂, d, s) where N₁ = N₂ = 32; d = 2; and s = 2 with five stages. The layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized multi- link butterfly fat tree network V_mlmk__bft (N₁ , N₂ , d, s) . Accordingly layout IOOH of FIG. IH is also applicable to generalized multi-link butterfly fat tree network

Referring to diagram 10OJ of FIG. IJ illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) of the layout IOOC of FIG. 1C which represents a generalized multi-link butterfly fat tree network v_mi_mk-_bft (^Ni ' ^₂ ' d, s) where Ni = N₂ = 32; d = 2; and s = 2. Block 1_2 in 10OJ illustrates both the intra-block and inter-block links. The layout diagram 10OJ corresponds to the embodiment where the switches that are placed together are implemented as combined switch in the network IOOB of FIG. IB. As noted before then the network IOOB is the generalized multi-link butterfly fat tree network V_mlmk__bfi (N₁ , N₂ , d, s) where Ni = N₂ =

32; d = 2; and s = 2 with five stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,390 that is incorporated by reference above. That is the switches that are placed together in Block 1_2 as shown in FIG. IJ are namely the combined input and output switch IS 1 &OS 1 belonging to switch 1 , illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switch implemented is combined input and output switch IS1&0S1); middle switch MS(1, 1) belonging to switch 2; middle switch MS(2,1) belonging to switch 3; middle switch MS(3,1) belonging to switch 4; And middle switch MS(4,1) belonging to switch 5.

Combined input and output switch IS1&0S1 is implemented as six by six switch with the inlet links ILl, IL2 and ML(8,1) - ML(8,4) being the inputs and middle links ML(1, 1) - ML(1,4), and outlet links OLl - OL2 being the outputs.

Middle switch MS(1, 1) is implemented as eight by eight switch with the middle links ML(1, 1), ML(1,2), ML(1,7), ML(1, 8), ML(7,1), ML(7,2), ML(7,11) and ML(7,12) being the inputs and middle links ML(2,1) - ML(2,4) and middle links ML(8,1) - ML(8,4) being the outputs. Similarly all the other middle switches are also implemented as eight by eight switches as illustrated in 10OJ of FIG. U. Applicant observes that in middle switch MS(1, 1) any one of the right going middle links can be switched to any one of the left going middle links and hereinafter middle switch MS(1, 1) provides U-turn links. In general, in the network V_mlmk__bft (N₁ , N₂ , d, s) each input switch, each output switch and each middle switch provides U-turn links.

In another embodiment, middle switch MS(1, 1) (or the middle switches in any of the middle stage excepting the root middle stage) of Block 1_2 of

V_mlmk__bβ (N₁ , N₂ , d, s) can be implemented as a four by eight switch and a four by four switch to save cross points. This is because the left going middle links of these middle switches are never setup to the right going middle links. For example, in middle switch MS(1, 1) of Block 1_2 as shown FIG. IJ, the left going middle links namely ML(7,1), ML(7,2), ML(7,11), and ML(7,12) are never switched to the right going middle links ML(2,1), ML(2,2), ML(2,3), and ML(2,4). And hence to implement MS(1, 1) two switches namely: 1) a four by eight switch with the middle links ML(1, 1), ML(1,2), ML(1,7), and ML(1,8) as inputs and the middle links ML(2,1), ML(2,2), ML(2,3), ML(2,4), ML(8,1), ML(8,2), ML(8,3), and ML(8,4) as outputs and 2) a four by four switch with the middle links ML(7,1), ML(7,2), ML(7,11), and ML(7,12) as inputs and the middle links ML(8,1), ML(8,2), ML(8,3), and ML(8,4) as outputs are sufficient without loosing any connectivity of the embodiment of MS(I₅I) being implemented as an eight by eight switch as described before.)

Generalized multi-stage network Embodiment:

In one embodiment, in the network IOOB of FIG. IB, the switches that are placed together are implemented as two separate switches in input stage 110 and output stage 120; and as four separate switches in all the middle stages, then the network IOOB is the generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) where Ni = Ν₂ = 32; d = 2; and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,391 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a two by four switch and a four by two switch respectively. For example the switch input switch IS 1 and output switch OSl are placed together; so input switch ISl is implemented as two by four switch with the inlet links ILl and IL2 being the inputs and middle links ML(1,1) -

ML(1, 4) being the outputs; and output switch OSl is implemented as four by two switch with the middle links ML(8,1), ML(8,4), ML(8,7) and ML(8,8) being the inputs and outlet links OLl - OL2 being the outputs.

The switches, corresponding to the middle stages that are placed together are implemented as four two by two switches. For example middle switches MS(1, 1), MS(1, 17), MS(7,1), and MS(7,17) are placed together; so middle switch MS(1, 1) is implemented as two by two switch with middle links ML(1,1) and ML(1, 7) being the inputs and middle links ML(2,1) and ML(2,3) being the outputs; middle switch MS(1, 17) is implemented as two by two switch with the middle links ML(1, 2) and ML(1, 8) being the inputs and middle links ML(2,2) and ML(2,4) being the outputs; middle switch

MS(7,1) is implemented as two by two switch with middle links ML(7,1) and ML(7,11) being the inputs and middle links ML(8,1) and ML(8,3) being the outputs; And middle switch MS(7,17) is implemented as two by two switch with the middle links ML(7,2) and ML(7,12) being the inputs and middle links ML(8,2) and ML(8,4) being the outputs; Similarly in this embodiment of network IOOB all the switches that are placed together are implemented as separate switches.

Layout diagrams IOOC in FIG. 1C, IOOD in FIG. ID, IOOE in FIG. IE, IOOF in FIG. IG are also applicable to generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with nine stages. The layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized folded multistage network V_fold (N₁ , N₂ , d, s) . Accordingly layout IOOH of FIG. IH is also applicable to generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) .

Referring to diagram IOOK of FIG. IK illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) of the layout IOOC of FIG. 1C which represents a generalized folded multi-stage network V_foi_d (^Ni > ^N ₂ > ^d> ^s) ^where Ni = N₂ = 32; d = 2; and s = 2. Block 1_2 in IOOK illustrates both the intra-block and inter-block links. The layout diagram IOOK corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network IOOB of FIG. IB. As noted before then the network IOOB is the generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,391 that is incorporated by reference above.

That is the switches that are placed together in Block 1_2 as shown in FIG. IK are namely the input switch ISl and output switch OSl belonging to switch 1, illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switches implemented are input switch ISl and output switch OSl); middle switches MS(1, 1), MS(1, 17), MS(7,1) and MS(7,17) belonging to switch 2; middle switches MS(2,1), MS(2,17), MS(6,1) and MS(6,17) belonging to switch 3; middle switches MS(3,1), MS(3,17), MS(5,1) and MS(5,17) belonging to switch 4; And middle switches MS(4,1), and MS(4,17) belonging to switch 5.

Input switch ISl and output switch OSl are placed together; so input switch ISl is implemented as two by four switch with the inlet links ILl and IL2 being the inputs and middle links ML(I₅I) - ML(1, 4) being the outputs; and output switch OSl is implemented as four by two switch with the middle links ML(8,1), ML(8,4), ML(8,7) and ML(8,8) being the inputs and outlet links OLl - 0L2 being the outputs.

Middle switches MS(I₅I), MS(1, 17), MS(7,1), and MS(7,17) are placed together; so middle switch MS(1, 1) is implemented as two by two switch with middle links

ML(1, 1) and ML(1,7) being the inputs and middle links ML(2,1) and ML(2,3) being the outputs; middle switch MS(1, 17) is implemented as two by two switch with the middle links ML(1, 2) and ML(1, 8) being the inputs and middle links ML(2,2) and ML(2,4) being the outputs; middle switch MS(7,1) is implemented as two by two switch with middle links ML(7,1) and ML(7,11) being the inputs and middle links ML(8,1) and ML(8,3) being the outputs; And middle switch MS(7,17) is implemented as two by two switch with the middle links ML(7,2) and ML(7,12) being the inputs and middle links ML(8,2) and ML(8,4) being the outputs. Similarly all the other middle switches are also implemented as two by two switches as illustrated in IOOK of FIG. IK.

Generalized multi-stage network Embodiment with S = I:

In one embodiment, in the network IOOB of FIG. IB (where it is implemented with s = l), the switches that are placed together are implemented as two separate switches in input stage 110 and output stage 120; and as two separate switches in all the middle stages, then the network IOOB is the generalized folded multi-stage network V _fo_ld (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 1 with nine stages as disclosed in

U.S. Provisional Patent Application Serial No. 60/940,391 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a two by two switch and a two by two switch. For example the switch input switch IS 1 and output switch OS 1 are placed together; so input switch ISl is implemented as two by two switch with the inlet links ILl and IL2 being the inputs and middle links ML(1,1) - ML(1, 2) being the outputs; and output switch OSl is implemented as two by two switch with the middle links ML(8,1) and ML(8,3) being the inputs and outlet links OLl - OL2 being the outputs. The switches, corresponding to the middle stages that are placed together are implemented as two, two by two switches. For example middle switches MS(1,1) and MS(7,1) are placed together; so middle switch MS(1, 1) is implemented as two by two switch with middle links ML(1,1) and ML(1, 3) being the inputs and middle links ML(2,1) and ML(2,2) being the outputs; middle switch MS(7,1) is implemented as two by two switch with middle links ML(7,1) and ML(7,5) being the inputs and middle links ML(8,1) and ML(8,2) being the outputs; Similarly in this embodiment of network IOOB all the switches that are placed together are implemented as two separate switches.

Layout diagrams IOOC in FIG. 1C, IOOD in FIG. ID, IOOE in FIG. IE, IOOF in FIG. IG are also applicable to generalized folded multi-stage network

V _fou (^Ni _> N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 1 with nine stages. The layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized folded multistage network V_fold (N₁ , N₂ , d, s) . Accordingly layout IOOH of FIG. IH is also applicable to generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) .

Referring to diagram IOOKI of FIG. IKl illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) for the layout IOOC of FIG. 1C when s = 1 which represents a generalized folded multi-stage network V_foi_d (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 1 (All the double links are replaced by single links when s = 1). Block 1_2 in IOOKI illustrates both the intra-block and inter- block links. The layout diagram IOOKI corresponds to the embodiment where the switches that are placed together are implemented as separate switches in the network IOOB of FIG. IB when s = 1. As noted before then the network IOOB is the generalized folded multi-stage network V_fold (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 1 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,391 that is incorporated by reference above.

That is the switches that are placed together in Block 1_2 as shown in FIG. IKl are namely the input switch IS 1 and output switch OS 1 belonging to switch 1 , illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switches implemented are input switch ISl and output switch OSl); middle switches MS(I₅I) and MS(7,1) belonging to switch 2; middle switches MS(2,1) and MS(6,1) belonging to switch 3; middle switches MS(3,1) and MS(5,1) belonging to switch 4; And middle switch MS(4,1) belonging to switch 5.

Input switch ISl and output switch OSl are placed together; so input switch ISl is implemented as two by two switch with the inlet links ILl and IL2 being the inputs and middle links ML(I₅I) - ML(1, 2) being the outputs; and output switch OSl is implemented as two by two switch with the middle links ML(8,1) and ML(8,3) being the inputs and outlet links OLl - 0L2 being the outputs.

Middle switches MS(I₅I) and MS(7,1) are placed together; so middle switch MS(I₅I) is implemented as two by two switch with middle links ML(I₅I) and ML(1,3) being the inputs and middle links ML(2,1) and ML(2,2) being the outputs; And middle switch MS(7,1) is implemented as two by two switch with middle links ML(7,1) and ML(7,5) being the inputs and middle links ML(8,1) and ML(8,2) being the outputs. Similarly all the other middle switches are also implemented as two by two switches as illustrated in IOOKI of FIG. IKl.

Generalized Butterfly Fat Tree Network Embodiment:

In another embodiment in the network IOOB of FIG. IB, the switches that are placed together are implemented as two combined switches then the network IOOB is the generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with five stages as disclosed in U.S. Provisional Patent Application Serial No.

60/940,387 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a six by six switch. For example the input switch IS 1 and output switch OS 1 are placed together; so input output switch IS1&0S1 are implemented as a six by six switch with the inlet links ILl, IL2, ML(8,1), ML(8,2), ML(8,7) and ML(8,8) being the inputs of the combined switch (denoted as IS1&0S1) and middle links ML(1, 1), ML(1,2), ML(1,3), ML(1,4), OLl and OL2 being the outputs of the combined switch IS 1 &OS 1. The switches, corresponding to the middle stages that are placed together are implemented as two four by four switches. For example middle switches MS(I₅I) and MS(1, 17) are placed together; so middle switch MS(I₅I) is implemented as four by four switch with middle links ML(I₅I), ML(IJ), ML(7,1) and ML(7,11) being the inputs and middle links ML(2,1), ML(2,3), ML(8,1) and ML(8,3) being the outputs; middle switch MS(1, 17) is implemented as four by four switch with the middle links ML(1,2), ML(1, 8), ML(7,2) and ML(7,12) being the inputs and middle links ML(2,2), ML(2,4), ML(8,2) and ML(8,4) being the outputs. Similarly in this embodiment of network IOOB all the switches that are placed together are implemented as a two combined switches.

Layout diagrams IOOC in FIG. 1C, IOOD in FIG. ID, IOOE in FIG. IE, IOOF in

FIG. IG are also applicable to generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with five stages. The layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized butterfly fat tree network V_bft (N₁ , N₂, d, s) . Accordingly layout IOOH of FIG. IH is also applicable to generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) .

Referring to diagram IOOL of FIG. IL illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) of the layout IOOC of FIG. 1C which represents a generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) where

N₁ = N₂ = 32; d = 2; and s = 2. Block 1_2 in IOOL illustrates both the intra-block and inter-block links. The layout diagram IOOL corresponds to the embodiment where the switches that are placed together are implemented as two combined switches in the network IOOB of FIG. IB. As noted before then the network IOOB is the generalized butterfly fat tree network V_bft (N₁ , N₂, d, s) where Ni = N₂ = 32; d = 2; and s = 2 with five stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,387 that is incorporated by reference above.

That is the switches that are placed together in Block 1_2 as shown in FIG. IL are namely the combined input and output switch IS 1 &OS 1 belonging to switch 1 , illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switch implemented is combined input and output switch IS1&0S1); middle switch MS(I₅I) and MS(1, 17) belonging to switch 2; middle switch MS(2,1) and MS(2,17) belonging to switch 3; middle switch MS(3,1) and MS(3,17) belonging to switch 4; And middle switch MS(4,1) belonging to switch 5.

Combined input and output switch IS1&0S1 is implemented as six by six switch with the inlet links ILl , IL2, ML(8, 1) , ML(8,2), ML(8,7) and ML(8,8) being the inputs and middle links ML(I₅I) - ML(1, 4) and outlet links OLl - 0L2 being the outputs.

Middle switch MS(I₅I) is implemented as four by four switch with middle links ML(I₅I), ML(1,7), ML(7,1) and ML(7,11) being the inputs and middle links ML(2,1), ML(2,3), ML(8,1) and ML(8,3) being the outputs; And middle switch MS(1, 17) is implemented as four by four switch with the middle links ML(1,2), ML(1, 8), ML(7,2) and ML(7,12) being the inputs and middle links ML(2,2), ML(2,4), ML(8,2) and ML(8,4) being the outputs. Similarly all the other middle switches are also implemented as two four by four switches as illustrated in IOOL of FIG. IL. Applicant observes that in middle switch MS(1, 1) any one of the right going middle links can be switched to any one of the left going middle links and hereinafter middle switch MS(1, 1) provides U-turn links. In general, in the network V_bft (N₁ , N₂, d, s) each input switch, each output switch and each middle switch provides U-turn links.

In another embodiment, middle switch MS(1, 1) (or the middle switches in any of the middle stage excepting the root middle stage) of Block 1_2 of V_bfi (N₁ , N₂ , d, s) can be implemented as a two by four switch and a two by two switch to save cross points.

This is because the left going middle links of these middle switches are never setup to the right going middle links. For example, in middle switch MS(1, 1) of Block 1_2 as shown FIG. IL, the left going middle links namely ML(7,1) and ML(7,11) are never switched to the right going middle links ML(2,1) and ML(2,3). And hence to implement MS(1, 1) two switches namely: 1) a two by four switch with the middle links ML(1, 1) and ML(1,7) as inputs and the middle links ML(2,1), ML(2,3), ML(8,1), and ML(8,3) as outputs and 2) a two by two switch with the middle links ML(7,1) and ML(7,11) as inputs and the middle links ML(8,1) and ML(8,3) as outputs are sufficient without loosing any connectivity of the embodiment of MS(I₅I) being implemented as an eight by eight switch as described before.)

Generalized Butterfly Fat Tree Network Embodiment with S = I:

In one embodiment, in the network IOOB of FIG. IB (where it is implemented with s = 1), the switches that are placed together are implemented as a combined switch in input stage 110 and output stage 120; and as a combined switch in all the middle stages, then the network IOOB is the generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) where Ni = Ν₂ = 32; d = 2; and s = 1 with five stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,387 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a four by four switch. For example the switch input switch ISl and output switch OSl are placed together; so input and output switch IS1&0S1 is implemented as four by four switch with the inlet links ILl, IL2, ML(8,1) and ML(8,3) being the inputs and middle links ML(1, 1) - ML(1, 2) and outlet links OLl - OL2 being the outputs

The switches, corresponding to the middle stages that are placed together are implemented as a four by four switch. For example middle switches MS(1, 1) is implemented as four by four switch with middle links ML(1, 1), ML(1, 3), ML(7,1) and ML(7,5) being the inputs and middle links ML(2,1), ML(2,2), ML(8,1) and ML(8,2) being the outputs..

Layout diagrams IOOC in FIG. 1C, IOOD in FIG. ID, IOOE in FIG. IE, IOOF in FIG. IG are also applicable to generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 1 with five stages. The layout IOOC in FIG. 1C can be recursively extended for any arbitrarily large generalized butterfly fat tree network V_bfi (N₁ , N₂, d, s) . Accordingly layout IOOH of FIG. IH is also applicable to generalized butterfly fat tree network V_bft (N₁ , N₂ , d, s) . Referring to diagram IOOLI of FIG. ILl illustrates a high-level implementation of Block 1_2 (Each of the other blocks have similar implementation) for the layout IOOC of FIG. 1C when s = 1 which represents a generalized butterfly fat tree network

V_bft (N₁ , N₂, d, s) where Ni = N₂ = 32; d = 2; and s = 1 (All the double links are replaced by single links when s = 1). Block 1_2 in IOOKI illustrates both the intra-block and interblock links. The layout diagram IOOLI corresponds to the embodiment where the switches that are placed together are implemented as a combined switch in the network IOOB of FIG. IB when s = 1. As noted before then the network IOOB is the generalized butterfly fat tree network V_bft (N₁ , N₂, d, s) where Ni = N₂ = 32; d = 2; and s = 1 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,387 that is incorporated by reference above.

That is the switches that are placed together in Block 1_2 as shown in FIG. ILl are namely the input and output switch IS1&0S1 belonging to switch 1, illustrated by dotted lines, (as noted before switch 1 is for illustration purposes only, in practice the switches implemented are input switch ISl and output switch OSl); middle switch

MS(1, 1) belonging to switch 2; middle switch MS(2,1) belonging to switch 3; middle switch MS(3,1) belonging to switch 4; And middle switch MS(4,1) belonging to switch 5.

Input and output switch IS1&0S1 are placed together; so input and output switch IS1&0S1 is implemented as four by four switch with the inlet links ILl, IL2, ML(8,1) and ML(8,3) being the inputs and middle links ML(1 , 1) - ML(1 ,2) and outlet links OLl - OL2 being the outputs.

Middle switch MS(1, 1) is implemented as four by four switch with middle links ML(1, 1), ML(1,3), ML(7,1) and ML(7,5) being the inputs and middle links ML(2,1), ML(2,2), ML(8,1) and ML(8,2) being the outputs. Similarly all the other middle switches are also implemented as four by four switches as illustrated in IOOLI of FIG. ILL

In another embodiment, middle switch MS(1, 1) (or the middle switches in any of the middle stage excepting the root middle stage) of Block 1_2 of V_mi_mk-_bfi (N₁ , N₂ , d, s) can be implemented as a two by four switch and a two by two switch to save cross points. This is because the left going middle links of these middle switches are never setup to the right going middle links. For example, in middle switch MS(I₅I) of Block 1_2 as shown FIG. ILl, the left going middle links namely ML(7,1) and ML(7,5) are never switched to the right going middle links ML(2,1) and ML(2,2). And hence to implement MS(I₅I) two switches namely: 1) a two by four switch with the middle links ML(I₅I) and ML(1 ,3) as inputs and the middle links ML(2,1), ML(2,2), ML(8,1), and ML(8,2) as outputs and 2) a two by two switch with the middle links ML(7,1) and ML(7,5) as inputs and the middle links ML(8,1) and ML(8,2) as outputs are sufficient without loosing any connectivity of the embodiment of MS(I₅I) being implemented as an eight by eight switch as described before.)

Hypercube-like Topology layout schemes:

Referring to diagram 300A in FIG. 3A, in one embodiment, an exemplary generalized multi-link multi-stage network V_mlmk (N₁ , N₂ ,d, s) where Ni = Ν₂ = 32; d = 2; and s = 2 with nine stages of one hundred and forty four switches for satisfying communication requests, such as setting up a telephone call or a data call, or a connection between configurable logic blocks, between an input stage 110 and output stage 120 via middle stages 130, 140, 150, 170, 170, 180 and 190 is shown where input stage 110 consists of sixteen, two by four switches ISl -IS 16 and output stage 120 consists of sixteen, four by two switches OSl -OS 16.

The diagram 300A in FIG. 3 A is exactly the same as the diagram IOOA in FIG.

IA excepting the connection links between middle stage 150 and middle stage 160 as well as between middle stage 160 and middle stage 170. N

Each of the — middle switches are connected to exactly d switches in middle

stage 160 through two links each for a total of 2x d links (for example the links ML(4,1) and ML(4,2) are connected from middle switch MS(3,1) to middle switch MS(4,1), and the links ML(4,3) and ML(4,4) are connected from middle switch MS(3,1) to middle switch MS(4, 15)).

N

Each of the — middle switches MS(4,1) - MS(4,16) in the middle stage 160 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(4,1) and ML(4,2) are connected to the middle switch MS(4,1) from input switch MS(3,1), and the links ML(4,59) and ML(4,60) are connected to the middle switch MS(4,1) from input switch MS(3,15)) and also are connected to exactly d switches in middle stage 170 through two links each for a total of 2x d links (for example the links ML(5,1) and ML(5,2) are connected from middle switch MS(4,1) to middle switch MS(5,1), and the links ML(5,3) and ML(5,4) are connected from middle switch MS(4,1) to middle switch MS(5,15)).

N Each of the — middle switches MS(5,1) - MS(5,16) in the middle stage 170 are d connected from exactly d input switches through two links each for a total of 2 x d links (for example the links ML(5,1) and ML(5,2) are connected to the middle switch MS(5,1) from input switch MS(4,1), and the links ML(5,59) and ML(5,60) are connected to the middle switch MS(5,1) from input switch MS(4,15)).

Finally the connection topology of the network IOOA shown in FIG. IA is also basically back to back inverse Benes connection topology but with a slight variation. All the cross middle links from middle switches MS(3,1) - MS(3,8) connect to middle switches MS(4,9) - MS(4,16) and all the cross middle links from middle switches MS(3,9) - MS(3,16) connect to middle switches MS(4,1) - MS(4,8). Applicant makes a key observation that there are many combinations of connections possible using this property. The difference in the connection topology between diagram IOOA of FIG. IA and diagram 300A of FIG. 3A is that the connections formed by cross middle links between middle stage 150 and middle stage 160 are made of two different combinations otherwise both the diagrams IOOA and 300A implement back to back inverse Benes connection topology. Since these networks implement back to back inverse Benes topologies since there is difference in the connections of cross middle links between middle stage 150 and middle stage 160, the same difference in the connections of cross middle links between 160 and middle stage 170 occurs.

Referring to diagram 300B in FIG. 3B, is a folded version of the multi-link multistage network 300A shown in FIG. 3A. The network 300B in FIG. 3B shows input stage 110 and output stage 120 are placed together. That is input switch ISl and output switch OSl are placed together, input switch IS2 and output switch OS2 are placed together, and similarly input switch IS 16 and output switch OS 16 are placed together. All the right going middle links {i.e., inlet links ILl - IL32 and middle links ML(1, 1) - ML(1, 64)} correspond to input switches ISl - IS16, and all the left going middle links {i.e., middle links ML(7,1) - ML(7,64) and outlet links OL1-OL32} correspond to output switches OS1 - OS16.

Just the same way there is difference in the connection topology between diagram IOOA of FIG. IA and diagram 300A of FIG. 3 A in the way the connections are formed by cross middle links between middle stage 150 and middle stage 160 and also between middle stage 160 and middle stage 170, the exact similar difference is there between the diagram IOOB of FIG. IB and the diagram 300B of FIG. 3B, i.e., in the way the connections are formed by cross middle links between middle stage 150 and middle stage 160 and also between middle stage 160 and middle stage 170.

In one embodiment, in the network 300B of FIG. 3B, the switches that are placed together are implemented as separate switches then the network 300B is the generalized folded multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = N₂ = 32; d = 2; and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is incorporated by reference above. That is the switches that are placed together in input stage 110 and output stage 120 are implemented as a two by four switch and a four by two switch. For example the switch input switch IS 1 and output switch OS 1 are placed together; so input switch ISl is implemented as two by four switch with the inlet links ILl and IL2 being the inputs of the input switch ISl and middle links ML(I₅I) - ML(1, 4) being the outputs of the input switch ISl; and output switch OSl is implemented as four by two switch with the middle links ML(8,1), ML(8,2), ML(8,7) and ML(8,8) being the inputs of the output switch OSl and outlet links OLl - 0L2 being the outputs of the output switch OSl. Similarly in this embodiment of network 300B all the switches that are placed together are implemented as separate switches.

Referring to layout 300C of FIG. 3C, in one embodiment, there are sixteen blocks namely Block 1_2, Block 3_4, Block 5_6, Block 7_8, Block 9_10, Block 11_12, Block 13_14, Block 15_16, Block 17_18, Block 19_20, Block 21_22, Block 23_24, Block 25_26, Block 27_28, Block 29_30, and Block 31_32. Each block implements all the switches in one row of the network 300B of FIG. 3B, one of the key aspects of the current invention. For example Block 1_2 implements the input switch ISl, output Switch OSl, middle switch MS(1, 1), middle switch MS(7,1), middle switch MS(2,1), middle switch MS(6,1), middle switch MS(3,1), middle switch MS(5,1), and middle switch MS(4,1). For the simplification of illustration, Input switch ISl and output switch OSl together are denoted as switch 1; Middle switch MS(1, 1) and middle switch MS(7,1) together are denoted by switch 2; Middle switch MS(2,1) and middle switch MS(6,1) together are denoted by switch 3; Middle switch MS(3,1) and middle switch MS(5,1) together are denoted by switch 4; And middle switch MS(4,1) is denoted by switch 5.

All the straight middle links are illustrated in layout 300C of FIG. 3C. For example in Block 1_2, inlet links ILl - IL2, outlet links OLl - OL2, middle link ML(1, 1), middle link ML(1,2), middle link ML(8,1), middle link ML(8,2), middle link ML(2,1), middle link ML(2,2), middle link ML(7,1), middle link ML(7,2), middle link ML(3,1), middle link ML(3,2), middle link ML(6,1), middle link ML(6,2), middle link ML(4, 1), middle link ML(4,2), middle link ML(5, 1) and middle link ML(5,2) are illustrated in layout 300C of FIG. 3C.

Even though it is not illustrated in layout 300C of FIG. 3C, in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. There are four quadrants in the layout 300C of FIG. 3C namely top-left, bottom-left, top-right and bottom-right quadrants. Top-left quadrant implements Block 1_2, Block 3_4, Block 5_6, and Block 7_8. Bottom-left quadrant implements Block 9_10, Block 11_12, Block 13_14, and Block 15_16. Top-right quadrant implements Block 25_26, Block 27_28, Block 29_30, and Block 31_32. Bottom-right quadrant implements Block 17_18, Block 19_20, Block 21_22, and Block 23_24. There are two halves in layout 300C of FIG. 3C namely left-half and right-half. Left-half consists of top-left and bottom-left quadrants. Right-half consists of top-right and bottom-right quadrants.

Recursively in each quadrant there are four sub-quadrants. For example in top-left quadrant there are four sub-quadrants namely top-left sub-quadrant, bottom-left sub- quadrant, top-right sub-quadrant and bottom-right sub-quadrant. Top-left sub-quadrant of top-left quadrant implements Block 1_2. Bottom-left sub-quadrant of top-left quadrant implements Block 3_4. Top-right sub-quadrant of top-left quadrant implements Block 7_8. Finally bottom-right sub-quadrant of top-left quadrant implements Block 5_6. Similarly there are two sub-halves in each quadrant. For example in top-left quadrant there are two sub-halves namely left-sub-half and right- sub-half. Left-sub-half of top-left quadrant implements Block 1_2 and Block 3_4. Right-sub-half of top-left quadrant implements Block 7_8 and Block 5_6. Recursively in larger multi-stage network V_foi_d-_mii_nk (^i _> N₂ ' ^' ^s) where Ni = N2 > 32, the layout in this embodiment in accordance with the current invention, will be such that the super-quadrants will also be arranged in a similar manner.

Layout 300D of FIG. 3D illustrates the inter-block links (in the layout 300C of FIG. 3C all the cross middle links are inter-block links) between switches 1 and 2 of each block. For example middle links ML(1, 3), ML(1,4), ML(8,7), and ML(8,8) are connected between switch 1 of Block 1_2 and switch 2 of Block 3_4. Similarly middle links

ML(1, 7), ML(1, 8), ML(8,3), and ML(8,4) are connected between switch 2 of Block 1_2 and switch 1 of Block 3_4. Applicant notes that the inter-block links illustrated in layout IOOD of FIG. ID can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(1, 4) and ML(8,8) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(1, 4) and ML(8,8) are implemented as a time division multiplexed single track).

Layout 300E of FIG. 3E illustrates the inter-block links between switches 2 and 3 of each block. For example middle links ML(2,3), ML(2,4), ML(7,11), and ML(7,12) are connected between switch 2 of Block 1_2 and switch 3 of Block 3_4. Similarly middle links ML(2,11), ML(2,12), ML(7,3), and ML(7,4) are connected between switch 3 of Block 1_2 and switch 2 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 300E of FIG. 3E can be implemented as diagonal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(2,12) and ML(7,4) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(2,12) and ML(7,4) are implemented as a time division multiplexed single track).

Layout 300F of FIG. 3F illustrates the inter-block links between switches 3 and 4 of each block. For example middle links ML(3,3), ML(3,4), ML(6,19), and ML(6,20) are connected between switch 3 of Block 1_2 and switch 4 of Block 3_4. Similarly middle links ML(3,19), ML(3,20), ML(6,3), and ML(6,4) are connected between switch 4 of Block 1_2 and switch 3 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 300F of FIG. 3F can be implemented as vertical tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(3,4) and ML(6,20) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(3,4) and ML(6,20) are implemented as a time division multiplexed single track).

Layout 300G of FIG. 3G illustrates the inter-block links between switches 4 and 5 of each block. For example middle links ML(4,3), ML(4,4), ML(5,35), and ML(5,36) are connected between switch 4 of Block 1_2 and switch 5 of Block 3_4. Similarly middle links ML(4,35), ML(4,36), ML(5,3), and ML(5,4) are connected between switch 5 of Block 1_2 and switch 4 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 300G of FIG. 3G can be implemented as horizontal tracks in one embodiment. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(4,4) and ML(5,36) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(4,4) and ML(5,36) are implemented as a time division multiplexed single track).

The complete layout for the network 300B of FIG. 3B is given by combining the links in layout diagrams of 300C, 300D, 300E, 300F, and 300G. Applicant notes that in the layout 300C of FIG. 3C, the inter-block links between switch 1 and switch 2 are vertical tracks as shown in layout 300D of FIG. 3D; the inter-block links between switch 2 and switch 3 are horizontal tracks as shown in layout 300E of FIG. 3E; the inter-block links between switch 3 and switch 4 are vertical tracks as shown in layout 300F of FIG. 3F; and finally the inter-block links between switch 4 and switch 5 are horizontal tracks as shown in layout 300G of FIG. 3G. The pattern is either vertical tracks, horizontal tracks or diagonal tracks. It continues recursively for larger networks of N > 32 as will be illustrated later.

Some of the key aspects of the current invention related to layout diagram 300C of IFG. 3C are noted. 1) All the switches in one row of the multi-stage network 300B are implemented in a single block. 2) The blocks are placed in such a way that all the inter- block links are either horizontal tracks, vertical tracks or diagonal tracks; 3) The length of the longest wire is about half of the width (or length) of the complete layout (For example middle link ML(4,4) is about half the width of the complete layout.);

The layout 300C in FIG. 3C can be recursively extended for any arbitrarily large generalized folded multi-link multi-stage network V_fold__mlmk (N₁, N₂ , d, s) . Referring to layout 300H of FIG. 3H, illustrates the extension of layout 300C for the network ^v _foi_d-_mi_mk (^Ni ^₂ , d, ^s) ^where Ni = N₂ = 128; d = 2; and s = 2. There are four super- quadrants in layout 300H namely top-left super-quadrant, bottom-left super-quadrant, top-right super-quadrant, bottom-right super-quadrant. Total number of blocks in the layout 300H is sixty four. Top-left super-quadrant implements the blocks from block 1_2 to block 31_32. Each block in all the super-quadrants has two more switches namely switch 6 and switch 7 in addition to the switches [1-5] illustrated in layout 300C of FIG. 3C. The inter-block link connection topology is the exactly the same between the switches 1 and 2; switches 2 and 3; switches 3 and 4; switches 4 and 5 as it is shown in the layouts of FIG. 3D, FIG. 3E, FIG. 3F, and FIG. 3G respectively.

Recursively in accordance with the current invention, the inter-block links connecting the switch 5 and switch 6 will be vertical tracks between the corresponding switches of top-left super-quadrant and bottom-left super-quadrant. And similarly the inter-block links connecting the switch 5 and switch 6 will be vertical tracks between the corresponding switches of top-right super-quadrant and bottom-right super-quadrant. The inter-block links connecting the switch 6 and switch 7 will be horizontal tracks between the corresponding switches of top-left super-quadrant and top-right super-quadrant. And similarly the inter-block links connecting the switch 6 and switch 7 will be horizontal tracks between the corresponding switches of bottom- left super-quadrant and bottom- right super-quadrant.

Ring Topology layout schemes:

Layout diagram 400C of FIG. 4C is another embodiment for the generalized folded multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) diagram IOOB in FIG. IB.

Referring to layout 400C of FIG. 4C, there are sixteen blocks namely Block 1_2, Block 3_4, Block 5_6, Block 7_8, Block 9_10, Block 11_12, Block 13_14, Block 15_16, Block 17_18, Block 19_20, Block 21_22, Block 23_24, Block 25_26, Block 27_28, Block 29_30, and Block 31_32. Each block implements all the switches in one row of the network IOOB of FIG. IB, one of the key aspects of the current invention. For example Block 1_2 implements the input switch ISl, output Switch OSl, middle switch MS(1, 1), middle switch MS(7,1), middle switch MS(2,1), middle switch MS(6,1), middle switch MS(3,1), middle switch MS(5,1), and middle switch MS(4,1). For the simplification of illustration, Input switch IS 1 and output switch OS 1 together are denoted as switch 1 ; Middle switch MS(1, 1) and middle switch MS(7,1) together are denoted by switch 2; Middle switch MS(2,1) and middle switch MS(6,1) together are denoted by switch 3; Middle switch MS(3,1) and middle switch MS(5,1) together are denoted by switch 4; And middle switch MS(4,1) is denoted by switch 5.

All the straight middle links are illustrated in layout 400C of FIG. 4C. For example in Block 1_2, inlet links ILl - IL2, outlet links OLl - OL2, middle link ML(1, 1), middle link ML(1,2), middle link ML(8,1), middle link ML(8,2), middle link ML(2,1), middle link ML(2,2), middle link ML(7,1), middle link ML(7,2), middle link ML(3, 1), middle link ML(3,2), middle link ML(6, 1), middle link ML(6,2), middle link ML(4,1), middle link ML(4,2), middle link ML(5,1) and middle link ML(5,2) are illustrated in layout 400C of FIG. 4C.

Even though it is not illustrated in layout 400C of FIG. 4C, in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. The topology of the layout 400C in FIG. 4C is a ring. For each of the neighboring rows in diagram IOOB of FIG. IB the corresponding blocks are also physically neighbors in layout diagram 400C of FIG. 4C. In addition the topmost row is also logically considered as neighbor to the bottommost row. For example Block 1_2 (implementing the switches belonging to a row in diagram IOOB of FIG. IB) has Block 3_4 as neighbor since Block 3_4 implements the switches in its neighboring row. Similarly Block 1_2 also has Block 31_32 as neighbor since Block 1_2 implements topmost row of switches and Block 31_32 implements bottommost row of switches in diagram IOOB of FIG. IB. The ring layout scheme illustrated in 400C of FIG. 4C can be generalized for a large multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) where Ni = N₂ > 32, in accordance with the current invention.

Layout 400B of FIG. 4B illustrates the inter-block links (in the layout 400A of FIG. 4A all the cross middle links are inter-block links) between switches 1 and 2 of each block. For example middle links ML(1, 3), ML(1,4), ML(8,7), and ML(8,8) are connected between switch 1 of Block 1_2 and switch 2 of Block 3_4. Similarly middle links ML(1,7), ML(1, 8), ML(8,3), and ML(8,4) are connected between switch 2 of Block 1_2 and switch 1 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 400B of FIG. 4B are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(1, 4) and ML(8,8) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(1, 4) and ML(8,8) are implemented as a time division multiplexed single track).

Layout 400C of FIG. 4C illustrates the inter-block links between switches 2 and 3 of each block. For example middle links ML(2,3), ML(2,4), ML(7,11), and ML(7,12) are connected between switch 2 of Block 1_2 and switch 3 of Block 3_4. Similarly middle links ML(2,11), ML(2,12), ML(7,3), and ML(7,4) are connected between switch 3 of Block 1_2 and switch 2 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 400C of FIG. 4C are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(2,12) and ML(7,4) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(2,12) and ML(7,4) are implemented as a time division multiplexed single track).

Layout 400D of FIG. 4D illustrates the inter-block links between switches 3 and 4 of each block. For example middle links ML(3,3), ML(3,4), ML(6,19), and ML(6,20) are connected between switch 3 of Block 1_2 and switch 4 of Block 3_4. Similarly middle links ML(3,19), ML(3,20), ML(6,3), and ML(6,4) are connected between switch 4 of Block 1_2 and switch 3 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 400D of FIG. 4D are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(3,4) and ML(6,20) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(3,4) and ML(6,20) are implemented as a time division multiplexed single track).

Layout 400E of FIG. 4E illustrates the inter-block links between switches 4 and 5 of each block. For example middle links ML(4,3), ML(4,4), ML(5,35), and ML(5,36) are connected between switch 4 of Block 1_2 and switch 5 of Block 3_4. Similarly middle links ML(4,35), ML(4,36), ML(5,3), and ML(5,4) are connected between switch 5 of

Block 1_2 and switch 4 of Block 3_4. Applicant notes that the inter-block links illustrated in layout 400E of FIG. 4E are implemented as vertical tracks or horizontal tracks or diagonal tracks. Also in one embodiment inter-block links are implemented as two different tracks (for example middle links ML(4,4) and ML(5,36) are implemented as two different tracks); or in an alternative embodiment inter-block links are implemented as a time division multiplexed single track (for example middle links ML(4,4) and ML(5,36) are implemented as a time division multiplexed single track).

The complete layout for the network IOOB of FIG. IB is given by combining the links in layout diagrams of 400A, 400B, 400C, 400D, and 400E.

Some of the key aspects of the current invention related to layout diagram 400A of FIG. 4A are noted. 1) All the switches in one row of the multi-stage network IOOB are implemented in a single block. 2) The blocks are placed in such a way that all the interblock links are either horizontal tracks, vertical tracks or diagonal tracks; 3) Length of the different wires between the same two middle stages is not the same. However it gives an opportunity to implement the most connected circuits to place and route through the blocks which have shorter wires.

Layout diagram 400Cl of FIG. 4Cl is another embodiment for the generalized folded multi-link multi-stage network V_fold__mlmk (N₁ , N₂ , d, s) diagram IOOB in FIG. IB.

Referring to layout 400Cl of FIG. 4Cl, there are sixteen blocks namely Block 1_2, Block 3_4, Block 5_6, Block 7_8, Block 9_10, Block 11_12, Block 13_14, Block 15_16, Block 17_18, Block 19_20, Block 21_22, Block 23_24, Block 25_26, Block 27_28, Block 29_30, and Block 31_32. Each block implements all the switches in one row of the network IOOB of FIG. IB, one of the key aspects of the current invention. For example Block 1_2 implements the input switch ISl, output Switch OSl, middle switch MS(1, 1), middle switch MS(7,1), middle switch MS(2,1), middle switch MS(6,1), middle switch MS(3,1), middle switch MS(5,1), and middle switch MS(4,1). For the simplification of illustration, Input switch ISl and output switch OSl together are denoted as switch 1 ; Middle switch MS(1, 1) and middle switch MS(7,1) together are denoted by switch 2; Middle switch MS(2,1) and middle switch MS(6,1) together are denoted by switch 3; Middle switch MS(3,1) and middle switch MS(5,1) together are denoted by switch 4; And middle switch MS(4,1) is denoted by switch 5.

All the straight middle links are illustrated in layout 400Cl of FIG. 4Cl. For example in Block 1_2, inlet links ILl - IL2, outlet links OLl - OL2, middle link ML(1, 1), middle link ML(1,2), middle link ML(8,1), middle link ML(8,2), middle link ML(2,1), middle link ML(2,2), middle link ML(7,1), middle link ML(7,2), middle link ML(3,1), middle link ML(3,2), middle link ML(6,1), middle link ML(6,2), middle link ML(4,1), middle link ML(4,2), middle link ML(5,1) and middle link ML(5,2) are illustrated in layout 400Cl of FIG. 4Cl.

Even though it is not illustrated in layout 400Cl of FIG. 4Cl, in each block, in addition to the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital circuit or sub-integrated circuit block depending on the applications in different embodiments. The topology of the layout 400Cl in FIG. 4Cl is another embodiment of ring layout topology. For each of the neighboring rows in diagram IOOB of FIG. IB the corresponding blocks are also physically neighbors in layout diagram 400C of FIG. 4C. In addition the topmost row is also logically considered as neighbor to the bottommost row. For example Block 1_2 (implementing the switches belonging to a row in diagram IOOB of FIG. IB) has Block 3_4 as neighbor since Block 3_4 implements the switches in its neighboring row. Similarly Block 1_2 also has Block 31_32 as neighbor since Block 1_2 implements topmost row of switches and Block 31_32 implements bottommost row of switches in diagram IOOB of FIG. IB. The ring layout scheme illustrated in 400C of FIG.4C can be generalized for a large multi-stage network V_fold__mlmk (N₁ ,N₂,d, s) where Ni = N₂ > 32, in accordance with the current invention.

All the layout embodiments disclosed in the current invention are applicable to generalized multi-stage networks V(N₁ ,N₂,d,s) , generalized folded multi-stage networks V_fold (N₁ ,N₂,d,s) , generalized butterfly fat tree networks V_bft (N₁ ,N₂,d,s) , generalized multi-link multi-stage networks V_mlmk (N₁ ,N₂,d,s) , generalized folded multi- link multi-stage networks V_fold__mlmk (N₁ ,N₂,d,s) , generalized multi-link butterfly fat tree networks V_mlmk__bft (N₁ ,N₂,d,s) , and generalized hypercube networks V_hcube (N₁ ,N₂,d,s) for s = 1,2,3 or any number in general, and for both N₁ = N₂ = N .and N₁ ≠ N₂, and d is any integer.

Conversely applicant makes another important observation that generalized hypercube networks V_hcube (N₁ ,N₂,d, s) are implemented with the layout topology being the hypercube topology shown in layout IOOC of FIG.1C with large scale cross point reduction as any one of the networks described in the current invention namely: generalized multi-stage networks V(N₁ ,N₂,d,s) , generalized folded multi-stage networks V_fold (N₁ ,N₂,d,s) , generalized butterfly fat tree networks V_bft (N₁ ,N₂,d,s) , generalized multi-link multi-stage networks V_mlmk (N₁ ,N₂,d,s) , generalized folded multi- link multi-stage networks V_fold__mlmk (N₁ ,N₂,d,s) , generalized multi-link butterfly fat tree networks V_mlmk__bft (N₁ ,N₂,d,s) for s = 1,2,3 or any number in general, and for both N₁ = N₂ = N .and N₁ ≠ N₂, and d is any integer.

Applications Embodiments:

All the embodiments disclosed in the current invention are useful in many varieties of applications. FIG.5Al illustrates the diagram of 500Al which is a typical two by two switch with two inlet links namely ILl and IL2, and two outlet links namely OLl and OL2. The two by two switch also implements four crosspoints namely CP(I₅I), CP(1,2), CP(2,1) and CP(2,2) as illustrated in FIG. 5Al. For example the diagram of 500Al may the implementation of middle switch MS(I₅I) of the diagram IOOK of FIG. IK where inlet link ILl of diagram 500Al corresponds to middle link ML(I₅I) of diagram 100K₅ inlet link IL2 of diagram 500Al corresponds to middle link ML(1,7) of diagram 100K₅ outlet link OLl of diagram 500Al corresponds to middle link ML(2,1) of diagram 100K₅ outlet link OL2 of diagram 500Al corresponds to middle link ML(2,3) of diagram IOOK.

1) Programmable Integrated Circuit Embodiments:

All the embodiments disclosed in the current invention are useful in programmable integrated circuit applications. FIG. 5A2 illustrates the detailed diagram 500A2 for the implementation of the diagram 500Al in programmable integrated circuit embodiments. Each crosspoint is implemented by a transistor coupled between the corresponding inlet link and outlet link, and a programmable cell in programmable integrated circuit embodiments. Specifically crosspoint CP(I₅I) is implemented by transistor C(I₅I) coupled between inlet link ILl and outlet link OLl₅ and programmable cell P(I₅I); crosspoint CP(1 ,2) is implemented by transistor C(1 ,2) coupled between inlet link ILl and outlet link OL2, and programmable cell P(l,2); crosspoint CP(2,1) is implemented by transistor C(2,l) coupled between inlet link IL2 and outlet link OLl₅ and programmable cell P(2,l); and crosspoint CP(2,2) is implemented by transistor C(2,2) coupled between inlet link IL2 and outlet link OL2, and programmable cell P(2,2).

If the programmable cell is programmed ON₅ the corresponding transistor couples the corresponding inlet link and outlet link. If the programmable cell is programmed OFF₅ the corresponding inlet link and outlet link are not connected. For example if the programmable cell P(I₅I) is programmed ON₅ the corresponding transistor C(I₅I) couples the corresponding inlet link ILl and outlet link OLl. If the programmable cell P(I₅I) is programmed OFF₅ the corresponding inlet link ILl and outlet link OLl are not connected. In volatile programmable integrated circuit embodiments the programmable cell may be an SRAM (Static Random Address Memory) cell. In non- volatile programmable integrated circuit embodiments the programmable cell may be a Flash- memory cell. Also the programmable integrated circuit embodiments may implement field programmable logic arrays (FPGA) devices, or programmable Logic devices (PLD), or Application Specific Integrated Circuits (ASIC) embedded with programmable logic circuits or 3D-FPGAs.

FIG. 5 A2 also illustrates a buffer B 1 on inlet link IL2. The signals driven along inlet link IL2 are amplified by buffer B 1. Buffer B 1 can be inverting or non-inverting buffer. Buffers such as B 1 are used to amplify the signal in links which are usually long.

2) One-time Programmable Integrated Circuit Embodiments:

All the embodiments disclosed in the current invention are useful in one-time programmable integrated circuit applications. FIG. 5A3 illustrates the detailed diagram 500A3 for the implementation of the diagram 500Al in one-time programmable integrated circuit embodiments. Each crosspoint is implemented by a via coupled between the corresponding inlet link and outlet link in one-time programmable integrated circuit embodiments. Specifically crosspoint CP(1, 1) is implemented by via V(1, 1) coupled between inlet link ILl and outlet link OLl ; crosspoint CP(1, 2) is implemented by via V(1, 2) coupled between inlet link ILl and outlet link OL2; crosspoint CP(2,1) is implemented by via V(2,l) coupled between inlet link IL2 and outlet link OLl; and crosspoint CP(2,2) is implemented by via V(2,2) coupled between inlet link IL2 and outlet link OL2.

If the via is programmed ON, the corresponding inlet link and outlet link are permanently connected which is denoted by thick circle at the intersection of inlet link and outlet link. If the via is programmed OFF, the corresponding inlet link and outlet link are not connected which is denoted by the absence of thick circle at the intersection of inlet link and outlet link. For example in the diagram 500A3 the via V(l,l) is programmed ON, and the corresponding inlet link ILl and outlet link OLl are connected as denoted by thick circle at the intersection of inlet link ILl and outlet link OLl; the via V(2,2) is programmed ON, and the corresponding inlet link IL2 and outlet link OL2 are connected as denoted by thick circle at the intersection of inlet link IL2 and outlet link OL2; the via V(1, 2) is programmed OFF, and the corresponding inlet link ILl and outlet link OL2 are not connected as denoted by the absence of thick circle at the intersection of inlet link ILl and outlet link OL2; the via V(2,l) is programmed OFF, and the corresponding inlet link IL2 and outlet link OLl are not connected as denoted by the absence of thick circle at the intersection of inlet link IL2 and outlet link OLl . One-time programmable integrated circuit embodiments may be anti-fuse based programmable integrated circuit devices or mask programmable structured ASIC devices.

3) Integrated Circuit Placement and Route Embodiments:

All the embodiments disclosed in the current invention are useful in Integrated

Circuit Placement and Route applications, for example in ASIC backend Placement and Route tools. FIG. 5A4 illustrates the detailed diagram 500A4 for the implementation of the diagram 500Al in Integrated Circuit Placement and Route embodiments. In an integrated circuit since the connections are known a-priori, the switch and crosspoints are actually virtual. However the concept of virtual switch and virtal crosspoint using the embodiments disclosed in the current invention reduces the number of required wires, wire length needed to connect the inputs and outputs of different netlists and the time required by the tool for placement and route of netlists in the integrated circuit.

Each virtual crosspoint is used to either to hardwire or provide no connectivity between the corresponding inlet link and outlet link. Specifically crosspoint CP(1,1) is implemented by direct connect point DCP(I₅I) to hardwire (i.e., to permanently connect) inlet link ILl and outlet link OLl which is denoted by the thick circle at the intersection of inlet link ILl and outlet link OLl; crosspoint CP(2,2) is implemented by direct connect point DCP(2,2) to hardwire inlet link IL2 and outlet link OL2 which is denoted by the thick circle at the intersection of inlet link IL2 and outlet link OL2. The diagram 500A4 does not show direct connect point DCP(1, 2) and direct connect point DCP(1, 3) since they are not needed and in the hardware implementation they are eliminated. Alternatively inlet link ILl needs to be connected to outlet link OLl and inlet link ILl does not need to be connected to outlet link OL2. Also inlet link IL2 needs to be connected to outlet link OL2 and inlet link IL2 does not need to be connected to outlet link OLl. Furthermore in the example of the diagram 500A4, there is no need to drive the signal of inlet link ILl horizontally beyond outlet link OLl and hence the inlet link ILl is not even extended horizontally until the outlet link 0L2. Also the absence of direct connect point DCP(2,1) illustrates there is no need to connect inlet link IL2 and outlet link OLl.

In summary in integrated circuit placement and route tools, the concept of virtual switches and virtual cross points is used during the implementation of the placement & routing algorithmically in software, however during the hardware implementation cross points in the cross state are implemented as hardwired connections between the corresponding inlet link and outlet link, and in the bar state are implemented as no connection between inlet link and outlet link.

3) More Application Embodiments:

All the embodiments disclosed in the current invention are also useful in the design of SoC interconnects, Field programmable interconnect chips, parallel computer systems and in time-space-time switches.

Numerous modifications and adaptations of the embodiments, implementations, and examples described herein will be apparent to the skilled artisan in view of the disclosure.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit device comprising a plurality of sub-integrated circuit blocks and a routing network, and Said each plurality of sub-integrated circuit blocks comprising a plurality of inlet links and a plurality of outlet links; and

Said routing network interconnects any one of said outlet link of one of said sub- integrated circuit block to one or more said inlet links of one or more of said sub- integrated circuit blocks; and

Said routing network comprising of a plurality of stages y , starting from the lowest stage to the highest stage; and

Said routing network comprising a plurality of switches of size d x d , where d ≥ 2 , in each said stage and each said switch of size d X d having d inlet links and d outlet links; and

Said each sub-integrated circuit block comprising a plurality of said switches corresponding to each said stage; and

Said each sub-integrated circuit block comprising a plurality of forward connecting links connecting from switches in lower stage to switches in the immediate succeeding higher stage, and also comprising a plurality of backward connecting links connecting from switches in higher stage to switches in the immediate preceding lower stage; and

Said each sub-integrated circuit block comprising a plurality straight links in said forward connecting links from switches in lower stage to switches in the immediate succeeding higher stage and a plurality cross links in said forward connecting links from switches in lower stage to switches in the immediate succeeding higher stage, and further comprising a plurality of straight links in said backward connecting links from switches in higher stage to switches in the immediate preceding lower stage and a plurality of cross links in said backward connecting links from switches in higher stage to switches in the immediate preceding lower stage.

2. The integrated circuit device of claim 1, wherein said all straight links are connecting from switches in each said sub-integrated circuit block are connecting to switches in the same said sub-integrated circuit block; and said all cross links are connecting as either vertical or horizontal links between switches in two different said sub-integrated circuit blocks.

3. The integrated circuit device of claim 2, wherein said plurality of sub- integrated circuit blocks arranged in a two-dimensional grid.

4. The integrated circuit device of claim 3, wherein said cross links in succeeding stages are connecting as alternative vertical and horizontal links between switches in said sub-integrated circuit blocks.

5. The integrated circuit device of claim 4, wherein said cross links from switches in a stage in one of said sub-integrated circuit blocks are connecting to switches in the succeeding stage in another of said sub-integrated circuit blocks so that said cross links are either vertical links or horizontal and vice versa, and hereinafter such cross links are "shuffle exchange links").

6. The integrated circuit device of claim 5, wherein said all horizontal shuffle exchange links between switches in any two corresponding said succeeding stages are substantially of equal length and said vertical shuffle exchange links between switches in any two corresponding said succeeding stages are substantially of equal length in the entire said integrated circuit device.

7. The integrated circuit device of claim 6, wherein the shortest horizontal shuffle exchange links are connecting at the lowest stage and between switches in two nearest neighboring said sub-integrated circuit blocks, and length of the horizontal shuffle exchange links is doubled in each succeeding stage; and the shortest vertical shuffle exchange links are connecting at the lowest stage and between switches in two nearest neighboring said sub-integrated circuit blocks, and length of the vertical shuffle exchange links is doubled in each succeeding stage.

8. The integrated circuit device of claim 7, wherein y ≥ (log₂ N) so that the length of the horizontal shuffle exchange links in the highest stage is equal to half the size of the horizontal size of said two dimensional grid of sub-integrated circuit blocks and the length of the vertical shuffle exchange links in the highest stage is equal to half the size of the vertical size of said two dimensional grid of sub-integrated circuit blocks.

9. The integrated circuit device of claim 8, wherein d = 2 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast Benes network with full bandwidth.

10. The integrated circuit device of claim 8, wherein d = 2 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast Benes network and rearrangeably nonblocking for arbitrary fan-out multicast Benes network with full bandwidth.

11. The integrated circuit device of claim 8, wherein d = 2 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast Benes network with full bandwidth.

12. The integrated circuit device of claim 7, wherein y ≥ (log₂ N) so that the length of the horizontal shuffle exchange links in the highest stage is equal to half the size of the horizontal size of said two dimensional grid of sub-integrated circuit blocks and the length of the vertical shuffle exchange links in the highest stage is equal to half the size of the vertical size of said two dimensional grid of sub-integrated circuit blocks, and said each sub-integrated circuit block further comprising a plurality of U-turn links within switches in each of said stages in each of said sub-integrated circuit blocks.

13. The integrated circuit device of claim 12, wherein d = 2 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast butterfly fat tree network with full bandwidth.

14. The integrated circuit device of claim 12, wherein d = 2 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast butterfly fat tree network and rearrangeably nonblocking for arbitrary fan-out multicast butterfly fat tree network with full bandwidth.

15. The integrated circuit device of claim 12, wherein d = 2 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast butterfly fat tree network with full bandwidth.

16. The integrated circuit device of claim 1, wherein said horizontal and vertical links are implemented on two or more metal layers.

17. The integrated circuit device of claim 1, wherein said switches comprising active and reprogrammable cross points and said each cross point is programmable by an SRAM cell or a Flash Cell.

18. The integrated circuit device of claim 1, wherein said sub-integrated circuit blocks are of equal die size.

19. The integrated circuit device of claim 16, wherein said sub-integrated circuit blocks are Lookup Tables (hereinafter "LUTs") and said integrated circuit device is a field programmable gate array (FPGA) device or field programmable gate array (FPGA) block embedded in another integrated circuit device.

20. The integrated circuit device of claim 16, wherein said sub-integrated circuit blocks are AND or OR gates and said integrated circuit device is a programmable logic device (PLD).

21. The integrated circuit device of claim 1, wherein said sub-integrated circuit blocks comprising any arbitrary hardware logic or memory circuits.

22. The integrated circuit device of claim 1 , wherein said switches comprising active one-time programmable cross points and said integrated circuit device is a mask programmable gate array (MPGA) device or a structured ASIC device.

23. The integrated circuit device of claim 1, wherein said switches comprising passive cross points or just connection of two links or not and said integrated circuit device is a Application Specific Integrated Circuit (ASIC) device.

24. The integrated circuit device of claim 1, wherein said sub-integrated circuit blocks further recursively comprise one or more super-sub-integrated circuit blocks and a sub-routing network.

25. The integrated circuit device of claim 5, wherein said all horizontal shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and said vertical shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and y ≥ (log₂ N) .

26. The integrated circuit device of claim 25, wherein d = 2 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast generalized multi-stage network with full bandwidth.

27. The integrated circuit device of claim 25, wherein d = 2 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast generalized multi-stage network and rearrangeably nonblocking for arbitrary fan-out multicast generalized multi-stage network with full bandwidth.

28. The integrated circuit device of claim 25, wherein d = 2 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast generalized multistage network with full bandwidth.

29. The integrated circuit device of claim 5, wherein said all horizontal shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and said vertical shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and y ≥ (log₂ N) , and said each sub-integrated circuit block further comprising a plurality of U-turn links within switches in each of said stages in each of said sub-integrated circuit blocks.

30. The integrated circuit device of claim 29, wherein d = 2 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast generalized butterfly fat tree network with full bandwidth.

31. The integrated circuit device of claim 29, wherein d = 2 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast generalized butterfly fat tree Network and rearrangeably nonblocking for arbitrary fan-out multicast generalized butterfly fat tree network with full bandwidth.

32. The integrated circuit device of claim 29, wherein d = 2 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast generalized butterfly fat tree network with full bandwidth.

33. The integrated circuit device of claim 1, wherein said straight links connecting from switches in each said sub-integrated circuit block are connecting to switches in the same said sub-integrated circuit block; and said cross links are connecting as vertical or horizontal or diagonal links between two different said sub-integrated circuit blocks.

34. The integrated circuit device of claim 8, wherein d = 4 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast multi-link Benes network with full bandwidth.

35. The integrated circuit device of claim 8, wherein d = 4 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast multi-link Benes network and rearrangeably nonblocking for arbitrary fan-out multicast multi-link Benes network with full bandwidth.

36. The integrated circuit device of claim 8, wherein d = 4 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast multi-link Benes network with full bandwidth.

37. The integrated circuit device of claim 12, wherein d = 4 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast multi-link butterfly fat tree network with full bandwidth.

38. The integrated circuit device of claim 12, wherein d = 4 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast multi-link butterfly fat tree network and rearrangeably nonblocking for arbitrary fan-out multicast multi-link butterfly fat tree network with full bandwidth.

39. The integrated circuit device of claim 12, wherein d = 4 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast multi-link butterfly fat tree network with full bandwidth.

40. The integrated circuit device of claim 5, wherein said all horizontal shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and said vertical shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and y ≥ (log₂ N) .

41. The integrated circuit device of claim 40, wherein d = 4 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast generalized multi-link multi-stage network with full bandwidth.

42. The integrated circuit device of claim 40, wherein d = 4 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast generalized multi-link multi-stage network and rearrangeably nonblocking for arbitrary fan-out multicast generalized multi- link multi-stage network with full bandwidth.

43. The integrated circuit device of claim 40, wherein d = 4 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast generalized multi- link multi-stage network with full bandwidth.

44. The integrated circuit device of claim 5, wherein said all horizontal shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and said vertical shuffle exchange links between switches in any two corresponding said succeeding stages are of different length and y ≥ (log₂ N) , and said each sub-integrated circuit block further comprising a plurality of U-turn links within switches in each of said stages in each of said sub-integrated circuit blocks.

45. The integrated circuit device of claim 44, wherein d = 4 and there is only one switch in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there is only one switch in each said stage in each said sub- integrated circuit block connecting said backward connecting links and said routing network is rearrangeably nonblocking for unicast generalized multi-link butterfly fat tree network with full bandwidth.

46. The integrated circuit device of claim 44, wherein d = 4 and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least two switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for unicast generalized multi-link butterfly fat tree Network and rearrangeably nonblocking for arbitrary fan-out multicast generalized multi- link butterfly fat tree network with full bandwidth.

47. The integrated circuit device of claim 44, wherein d = 4 and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said forward connecting links and there are at least three switches in each said stage in each said sub-integrated circuit block connecting said backward connecting links and said routing network is strictly nonblocking for arbitrary fan-out multicast generalized multi- link butterfly fat tree network with full bandwidth.

48. The integrated circuit device of claim 1, wherein said plurality of forward connecting links use a plurality of buffers to amplify signals driven through them and said plurality of backward connecting links use a plurality of buffers to amplify signals driven through them; and said buffers can be inverting or non-inverting buffers.

49. The integrated circuit device of claim 1, wherein said wherein said all switches of size d X d are either fully populated or partially populated.