WO2008148044A3 - Resonant clock and interconnect architecture for digital devices with multiple clock networks - Google Patents

Resonant clock and interconnect architecture for digital devices with multiple clock networks Download PDF

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Publication number
WO2008148044A3
WO2008148044A3 PCT/US2008/064766 US2008064766W WO2008148044A3 WO 2008148044 A3 WO2008148044 A3 WO 2008148044A3 US 2008064766 W US2008064766 W US 2008064766W WO 2008148044 A3 WO2008148044 A3 WO 2008148044A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
digital devices
interconnect architecture
networks
resonant
Prior art date
Application number
PCT/US2008/064766
Other languages
French (fr)
Other versions
WO2008148044A2 (en
Inventor
Alexander T Ishii
Marios C Papaefthymiou
Original Assignee
Cyclos Semiconductor
Alexander T Ishii
Marios C Papaefthymiou
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cyclos Semiconductor, Alexander T Ishii, Marios C Papaefthymiou filed Critical Cyclos Semiconductor
Priority to JP2010509576A priority Critical patent/JP5319666B2/en
Priority to EP08756240A priority patent/EP2156263A2/en
Publication of WO2008148044A2 publication Critical patent/WO2008148044A2/en
Publication of WO2008148044A3 publication Critical patent/WO2008148044A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Abstract

A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
PCT/US2008/064766 2007-05-23 2008-05-23 Resonant clock and interconnect architecture for digital devices with multiple clock networks WO2008148044A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010509576A JP5319666B2 (en) 2007-05-23 2008-05-23 Resonant clock and interconnect architecture for digital devices with multi-clock networks
EP08756240A EP2156263A2 (en) 2007-05-23 2008-05-23 Resonant clock and interconnect architecture for digital devices with multiple clock networks

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93158207P 2007-05-23 2007-05-23
US60/931,582 2007-05-23

Publications (2)

Publication Number Publication Date
WO2008148044A2 WO2008148044A2 (en) 2008-12-04
WO2008148044A3 true WO2008148044A3 (en) 2009-02-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/064766 WO2008148044A2 (en) 2007-05-23 2008-05-23 Resonant clock and interconnect architecture for digital devices with multiple clock networks

Country Status (5)

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US (2) US7973565B2 (en)
EP (1) EP2156263A2 (en)
JP (1) JP5319666B2 (en)
KR (1) KR20100023000A (en)
WO (1) WO2008148044A2 (en)

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Also Published As

Publication number Publication date
EP2156263A2 (en) 2010-02-24
US8461873B2 (en) 2013-06-11
US20110210761A1 (en) 2011-09-01
US20090027085A1 (en) 2009-01-29
JP2010528377A (en) 2010-08-19
JP5319666B2 (en) 2013-10-16
KR20100023000A (en) 2010-03-03
US7973565B2 (en) 2011-07-05
WO2008148044A2 (en) 2008-12-04

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