WO2008152774A1 - メモリカードおよびその製造方法 - Google Patents

メモリカードおよびその製造方法 Download PDF

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Publication number
WO2008152774A1
WO2008152774A1 PCT/JP2008/001301 JP2008001301W WO2008152774A1 WO 2008152774 A1 WO2008152774 A1 WO 2008152774A1 JP 2008001301 W JP2008001301 W JP 2008001301W WO 2008152774 A1 WO2008152774 A1 WO 2008152774A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
semiconductor
memory card
wire
electrode
Prior art date
Application number
PCT/JP2008/001301
Other languages
English (en)
French (fr)
Inventor
Yuichiro Yamada
Hidenobu Nishikawa
Hiroyuki Yamada
Shuichi Takeda
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to JP2009519147A priority Critical patent/JP5187305B2/ja
Priority to US12/664,475 priority patent/US8223500B2/en
Priority to CN200880020434A priority patent/CN101689252A/zh
Publication of WO2008152774A1 publication Critical patent/WO2008152774A1/ja

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

回路基板、回路基板上の異なった領域に実装された半導体チップ、上面に半導体電極を有し下面の少なくとも一部が半導体チップの上面の少なくとも一部と対面するように固定した半導体チップ、半導体電極と回路基板上の基板電極とを接続し半導体チップを実装状態にするワイヤ、回路基板上側から3つの半導体チップ、ワイヤを含む回路形成領域を覆うカバー、を備え、3つの半導体チップの少なくとも一部と、回路基板の少なくとも一部と、ワイヤが二次封止樹脂、一次封止樹脂で覆われている。
PCT/JP2008/001301 2007-06-15 2008-05-26 メモリカードおよびその製造方法 WO2008152774A1 (ja)

Priority Applications (3)

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JP2009519147A JP5187305B2 (ja) 2007-06-15 2008-05-26 メモリカードおよびその製造方法
US12/664,475 US8223500B2 (en) 2007-06-15 2008-05-26 Memory card and method for manufacturing the same
CN200880020434A CN101689252A (zh) 2007-06-15 2008-05-26 存储卡及其制造方法

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JP2007158090 2007-06-15
JP2007-158090 2007-06-15

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US20100165587A1 (en) 2010-07-01
JPWO2008152774A1 (ja) 2010-08-26
US8223500B2 (en) 2012-07-17
CN101689252A (zh) 2010-03-31
JP5187305B2 (ja) 2013-04-24

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