WO2009001368A3 - System-on-chip fabric, as well as method and system for producing it - Google Patents

System-on-chip fabric, as well as method and system for producing it Download PDF

Info

Publication number
WO2009001368A3
WO2009001368A3 PCT/IN2007/000262 IN2007000262W WO2009001368A3 WO 2009001368 A3 WO2009001368 A3 WO 2009001368A3 IN 2007000262 W IN2007000262 W IN 2007000262W WO 2009001368 A3 WO2009001368 A3 WO 2009001368A3
Authority
WO
WIPO (PCT)
Prior art keywords
fabric
application
resources
clusters
hll
Prior art date
Application number
PCT/IN2007/000262
Other languages
French (fr)
Other versions
WO2009001368A2 (en
Inventor
Soumitra Kumar Nandy
Ranjani Narayan
Keshavan Varadarajan
Mythri Alle
Amar Nath Satrawala
Shimoga Janakiram Adarsha Rao
Original Assignee
Indian Institute Of Science
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Indian Institute Of Science filed Critical Indian Institute Of Science
Priority to PCT/IN2007/000262 priority Critical patent/WO2009001368A2/en
Publication of WO2009001368A2 publication Critical patent/WO2009001368A2/en
Publication of WO2009001368A3 publication Critical patent/WO2009001368A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

This invention provides a fabric within a SoC framework, along with a system and method, in which resources can be composed as computational structures that best match the application's needs. The fabric, disclosed herein, contains compute, storage and communication resources that can be aggregated at runtime to perform specific application tasks. The system comprises of a scheduler (42), a cluster configuration store (41 ), an execution fabric (45) containing a plurality of computational resources, a resource binding agent (43), a Load Store Unit (46), and Store Destination Decision Logic (49). The method of the present invention comprises the steps of developing High Level Language (HLL) descriptions of applications modules; converting the HLL description of the modules of the application to an intermediate representation; compiling into clusters using the dataflow graph of the application; performing binding operations; and Performing controlled dataflow execution wherein a set of clusters are scheduled and executed on the fabric.
PCT/IN2007/000262 2007-06-28 2007-06-28 A method and system-on-chip fabric WO2009001368A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IN2007/000262 WO2009001368A2 (en) 2007-06-28 2007-06-28 A method and system-on-chip fabric

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IN2007/000262 WO2009001368A2 (en) 2007-06-28 2007-06-28 A method and system-on-chip fabric

Publications (2)

Publication Number Publication Date
WO2009001368A2 WO2009001368A2 (en) 2008-12-31
WO2009001368A3 true WO2009001368A3 (en) 2009-09-24

Family

ID=40186127

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IN2007/000262 WO2009001368A2 (en) 2007-06-28 2007-06-28 A method and system-on-chip fabric

Country Status (1)

Country Link
WO (1) WO2009001368A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10089761B2 (en) 2016-04-29 2018-10-02 Hewlett Packard Enterprise Development Lp Graph processing using a shared memory
CN116501594B (en) * 2023-06-27 2023-09-08 上海燧原科技有限公司 System modeling evaluation method and device, electronic equipment and storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175948B1 (en) * 1998-02-05 2001-01-16 Motorola, Inc. Method and apparatus for a waveform compiler
WO2004004008A1 (en) * 2002-06-28 2004-01-08 Koninklijke Philips Electronics N.V. Integrated circuit having building blocks
US20050021871A1 (en) * 2003-07-25 2005-01-27 International Business Machines Corporation Self-contained processor subsystem as component for system-on-chip design
US20050283768A1 (en) * 2004-06-21 2005-12-22 Sanyo Electric Co., Ltd. Data flow graph processing method, reconfigurable circuit and processing apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175948B1 (en) * 1998-02-05 2001-01-16 Motorola, Inc. Method and apparatus for a waveform compiler
WO2004004008A1 (en) * 2002-06-28 2004-01-08 Koninklijke Philips Electronics N.V. Integrated circuit having building blocks
US20050021871A1 (en) * 2003-07-25 2005-01-27 International Business Machines Corporation Self-contained processor subsystem as component for system-on-chip design
US20050283768A1 (en) * 2004-06-21 2005-12-22 Sanyo Electric Co., Ltd. Data flow graph processing method, reconfigurable circuit and processing apparatus

Also Published As

Publication number Publication date
WO2009001368A2 (en) 2008-12-31

Similar Documents

Publication Publication Date Title
CN102360309B (en) Scheduling system and scheduling execution method of multi-core heterogeneous system on chip
Liu et al. Power-efficient time-sensitive mapping in heterogeneous systems
JP2008541302A5 (en)
WO2006055864A3 (en) Method and apparatus for implementing task management of computer operations
JP2013545169A5 (en)
WO2012135041A3 (en) Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2008090665A1 (en) Program parallelizing method and device
WO2009012296A3 (en) Scheduling by growing and shrinking resource allocation
WO2006083543A3 (en) Multithreading processor including thread scheduler based on instruction stall likelihood prediction
WO2010037177A8 (en) Scheduling an application for performance on a heterogeneous computing system
WO2012135050A3 (en) Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2007025220A3 (en) Automated resource planning tool and user interface
WO2005122681A3 (en) Goal-oriented predictive scheduling in a grid environment
EP2359256A4 (en) Saving program execution state
WO2007137034A3 (en) Managing computing resources in graph-based computations
JP2012522320A5 (en)
IN2014CN02852A (en)
CN102520925A (en) AADL2TASM (Architecture Analysis and Design Language-to-Timed Abstract State Machine) model transformation method
WO2011084883A3 (en) Task list generation, parallelism templates, and memory management for multi-core systems
Han et al. Compiling control-intensive loops for CGRAs with state-based full predication
WO2009001368A3 (en) System-on-chip fabric, as well as method and system for producing it
Wang et al. FPM: A flexible programming model for MPSoC on FPGA
Malik et al. Executing synchronous data flow graphs on heterogeneous execution architectures using integer linear programming
Prell et al. Task Parallelism on the SCC.
Chronaki et al. Poster: Exploiting asymmetric multi-core processors with flexible system sofware

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07805632

Country of ref document: EP

Kind code of ref document: A2

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 7659/CHENP/2009

Country of ref document: IN

122 Ep: pct application non-entry in european phase

Ref document number: 07805632

Country of ref document: EP

Kind code of ref document: A2