WO2009018059A3 - Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures - Google Patents

Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures Download PDF

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Publication number
WO2009018059A3
WO2009018059A3 PCT/US2008/070932 US2008070932W WO2009018059A3 WO 2009018059 A3 WO2009018059 A3 WO 2009018059A3 US 2008070932 W US2008070932 W US 2008070932W WO 2009018059 A3 WO2009018059 A3 WO 2009018059A3
Authority
WO
WIPO (PCT)
Prior art keywords
spacers
negative photoresist
semiconductor fabrication
associated structures
mask overlay
Prior art date
Application number
PCT/US2008/070932
Other languages
French (fr)
Other versions
WO2009018059A2 (en
Inventor
Luan C Tran
Original Assignee
Micron Technology Inc
Luan C Tran
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Luan C Tran filed Critical Micron Technology Inc
Publication of WO2009018059A2 publication Critical patent/WO2009018059A2/en
Publication of WO2009018059A3 publication Critical patent/WO2009018059A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

Spacers (175) are formed by pitch multiplication and a layer of negative photoresist (200) is deposited on and over the spacers (175) to form additional mask features. The deposited negative photoresist layer (200) is patterned, thereby removing photoresist from between the spacers (175) in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers (175) is facilitated. The pattern defined by the spacers (175) and the patterned negative photoresist is transferred to one or more underlying masking layers (130), (140) before being transferred to a substrate (110).
PCT/US2008/070932 2007-07-31 2008-07-23 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures WO2009018059A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/831,012 US8563229B2 (en) 2007-07-31 2007-07-31 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US11/831,012 2007-07-31

Publications (2)

Publication Number Publication Date
WO2009018059A2 WO2009018059A2 (en) 2009-02-05
WO2009018059A3 true WO2009018059A3 (en) 2009-04-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/070932 WO2009018059A2 (en) 2007-07-31 2008-07-23 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures

Country Status (3)

Country Link
US (2) US8563229B2 (en)
TW (1) TW200913016A (en)
WO (1) WO2009018059A2 (en)

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TW200913016A (en) 2009-03-16
US20090035665A1 (en) 2009-02-05

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