WO2009034557A3 - Method and apparatus for forming arbitrary structures for integrated circuit devices - Google Patents

Method and apparatus for forming arbitrary structures for integrated circuit devices Download PDF

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Publication number
WO2009034557A3
WO2009034557A3 PCT/IB2008/053714 IB2008053714W WO2009034557A3 WO 2009034557 A3 WO2009034557 A3 WO 2009034557A3 IB 2008053714 W IB2008053714 W IB 2008053714W WO 2009034557 A3 WO2009034557 A3 WO 2009034557A3
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WIPO (PCT)
Prior art keywords
arbitrary structures
arbitrary
integrated circuits
integrated circuit
circuit devices
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Application number
PCT/IB2008/053714
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French (fr)
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WO2009034557A2 (en
Inventor
Christopher Wyland
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Nxp B.V.
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Priority to EP08807647A priority Critical patent/EP2195830A2/en
Priority to CN200880106804A priority patent/CN101802989A/en
Publication of WO2009034557A2 publication Critical patent/WO2009034557A2/en
Publication of WO2009034557A3 publication Critical patent/WO2009034557A3/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A method of implementing arbitrary structures to provide electrical interconnection and mechanical fixturing for integrated circuits is provided. According to exemplary embodiments of the invention said arbitrary structures are manufactured using three dimensional manufacturing processes employing only additive steps for all materials within the arbitrary structure. Accordingly the arbitrary structure is provided in a single step incorporating mechanical, electrical, and thermal elements as required by the design incorporating simultaneously dielectric and metallic materials. The arbitrary structures may be manufactured directly in association with the integrated circuits or separately for subsequent assembly to the integrated circuits. Arbitrary structures ranging from a fraction of to all of the structural and electrical elements required for packaging the integrated circuit(s) being provided by the arbitrary structures according to the design boundary established.
PCT/IB2008/053714 2007-09-14 2008-09-12 Method and apparatus for forming arbitrary structures for integrated circuit devices WO2009034557A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08807647A EP2195830A2 (en) 2007-09-14 2008-09-12 Method and apparatus for forming arbitrary structures for integrated circuit devices
CN200880106804A CN101802989A (en) 2007-09-14 2008-09-12 Method and apparatus for forming arbitrary structures for integrated circuit devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US97270107P 2007-09-14 2007-09-14
US60/972,701 2007-09-14

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WO2009034557A2 WO2009034557A2 (en) 2009-03-19
WO2009034557A3 true WO2009034557A3 (en) 2009-10-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485416B (en) * 2013-11-22 2018-11-27 北京大学 A kind of resistance-variable storing device and preparation method thereof using Meta Materials electrode structure
US9818665B2 (en) 2014-02-28 2017-11-14 Infineon Technologies Ag Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled surfaces
EP3216690B1 (en) 2016-03-07 2018-11-07 Airbus Operations GmbH Method for manufacturing a lining panel
DE102018104144B4 (en) 2018-02-23 2022-12-15 Technische Universität Chemnitz Process for contacting and packaging a semiconductor chip
CN111640842A (en) * 2020-07-02 2020-09-08 江文涛 Packaging structure for packaging LED flip chip and packaging method thereof

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5140937A (en) * 1989-05-23 1992-08-25 Brother Kogyo Kabushiki Kaisha Apparatus for forming three-dimensional article
EP0523981A1 (en) * 1991-07-15 1993-01-20 Fritz B. Prinz Method of making electronic packages and smart structures formed by thermal spray deposition
US5779833A (en) * 1995-08-04 1998-07-14 Case Western Reserve University Method for constructing three dimensional bodies from laminations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140937A (en) * 1989-05-23 1992-08-25 Brother Kogyo Kabushiki Kaisha Apparatus for forming three-dimensional article
EP0523981A1 (en) * 1991-07-15 1993-01-20 Fritz B. Prinz Method of making electronic packages and smart structures formed by thermal spray deposition
US5779833A (en) * 1995-08-04 1998-07-14 Case Western Reserve University Method for constructing three dimensional bodies from laminations

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JOHANDER ET AL: "Layer Manufacturing as a Generic Tool for Microsystem Integration", 2 July 2007 (2007-07-02), XP002541940, Retrieved from the Internet <URL:http://www.4m-net.org/KnowledgeBase/papers/PID373481> [retrieved on 20090819] *

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EP2195830A2 (en) 2010-06-16
CN101802989A (en) 2010-08-11

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