WO2009045863A1 - Semiconductor device and method for manufacturing thereof - Google Patents

Semiconductor device and method for manufacturing thereof Download PDF

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Publication number
WO2009045863A1
WO2009045863A1 PCT/US2008/077762 US2008077762W WO2009045863A1 WO 2009045863 A1 WO2009045863 A1 WO 2009045863A1 US 2008077762 W US2008077762 W US 2008077762W WO 2009045863 A1 WO2009045863 A1 WO 2009045863A1
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Prior art keywords
insulating film
forming
gate electrode
semiconductor substrate
gate
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PCT/US2008/077762
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French (fr)
Inventor
Takayuki Maruyama
Fumihiko Inoue
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Spansion Llc
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Publication of WO2009045863A1 publication Critical patent/WO2009045863A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing thereof. More particularly, the present invention relates to a semiconductor device including separated charge storage layers and a method for manufacturing thereof.
  • a non-volatile memory as a semiconductor device capable of rewiring data, and retaining stored data after turning the power OFF has been widely used.
  • a transistor which forms a memory cell includes a floating gate or an insulating film so called a charge storage layer for accumulating charges to store data.
  • a flash memory with a SONOS (Silicon Oxide Nitride Oxide Silicon) structure having charge accumulated in the charge storage layer inside an ONO (Oxide Nitride Oxide) film has been introduced as the one having the insulating film serving as the charge storage layer.
  • United State Patent No. 6011725 discloses the flash memory with a virtual ground type memory cell for symmetrically operating a source and a drain which may be switchable as one of the SONOS type flash memories.
  • FIG. 1 is a sectional view of the flash memory disclosed in USP No. 6011725.
  • a tunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially layered on a semiconductor substrate 10.
  • Bit lines 18 each serving as a source and a drain extend inside the semiconductor substrate 10.
  • a gate electrode 24 is formed on the top insulating film 16 between the bit lines 18.
  • a distance L between the bit lines 18 is a channel length.
  • the source and the drain may be set and operated by switching between the bit lines 18 (BLl) and 18 (BL2) so as to accumulate the charge in charge storage regions Cl and C2, respectively. This makes it possible to store 2-bit data in a single transistor.
  • Japanese Patent Application Publication NO. JP-A-2005-108915 and Japanese Patent Application Publication NO. JP-A-2004-343014 disclose a process for forming charge storage layers in a separated state. Specifically, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a side wall of the gate electrode, or the side wall of the gate electrode and the gate insulating film are partially removed to form the separated charge storage layers in the thus removed regions.
  • the present invention provides a semiconductor device which includes a bit line formed to extend inside a semiconductor substrate, a gate electrode formed above the semiconductor substrate between the bit lines, a gate insulating film formed on the semiconductor substrate below a center of the gate electrode, charge storage layers each formed on the semiconductor substrate below the gate electrode to interpose the gate insulating film in a width direction of the bit line, and a first insulating film formed on the semiconductor substrate between the gate electrodes in an extending direction of the bit line.
  • a width of the first insulating film in the width direction of the bit line is larger than a width of the gate insulating film.
  • the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction are alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode.
  • the charge storage layers are separately formed to interpose the gate insulating film in the bit line width direction, thus suppressing the influence of CBD (Complementary Bit Disturb).
  • the first insulating film may be embedded in a groove formed in the semiconductor substrate between the gate electrodes in the extending direction of the bit line. This structure makes it possible to suppress fringe current flowing in the semiconductor substrate around the gate electrode.
  • the above-described structure may further include a protection film formed on a side surface of the first insulating film.
  • the protection film may be formed of a material which is different from a material for forming the gate insulating film and a material for forming the first insulating film. This structure allows easy formation of the first insulating film having a larger width than that of the gate insulating film.
  • each of the gate insulating film and the first insulating film may be formed of a silicon oxide film, and the protection film may be formed of a silicon nitride film.
  • an upper surface of the first insulating film may be formed further away from a surface of the semiconductor substrate than an upper surface of the gate insulating film. This structure can further suppress tilting of the gate electrode.
  • the above-described structure may further include a word line which is electrically coupled with the gate electrode to be formed thereon, and extends across the bit line.
  • the charge storage layer may be formed of either a polysilicon film or a silicon nitride film.
  • the present invention provides a method for manufacturing a semiconductor device, which includes the steps of: forming a second insulating film on a semiconductor substrate; forming a first opening in the second insulating film by removing the second insulating film formed on the semiconductor substrate in a region other than a region where a bit line and a gate electrode are to be formed; forming a first insulating film in the first opening; forming a conducting layer on the second insulating film; forming second openings by removing the conducting layer and the second insulating layer formed on the semiconductor substrate in a region where the bit line is to be formed, and forming the gate electrode as the conducting layer between the second openings; forming a gate insulating film as the second insulating film below a center of the gate electrode, by removing the second insulating film formed below the gate electrode from the second opening; forming a charge storage layer in a region where the second insulating film formed below the gate electrode has been removed; and forming the bit line defined by each of the second openings in the semiconductor
  • the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction are alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode. Further, the separated charge storage layers can be formed to interpose the gate insulating film in the bit line width direction. Thus, it is possible to suppress the influence of the CBD.
  • the above-described method may further include the step of forming a groove in the semiconductor substrate at a lower portion of the first opening.
  • the step of forming the first insulating film may include a step of forming the first insulating film in the groove. This method makes it possible to suppress fringe current flowing in the semiconductor substrate around the gate electrode.
  • the first insulating film may be formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode. This method makes it possible to easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction.
  • the above-described method may further include the step of forming a protection film on a side surface of the first opening prior to the step of forming the first insulating film.
  • the protection film may be formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode. This method makes it possible to easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction.
  • the above-described method may further include the step of forming the protection film on an exposed portion of a side surface of the first insulating film prior to the step of forming the conducting layer after performing the step of forming the first insulating film.
  • This method makes it possible to further easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction.
  • each of the first and the second insulating films may be formed of a silicon oxide film, and the protection film may be formed of a silicon nitride film.
  • the second insulating film may be removed using a mask layer formed on the second insulating film to form the first opening.
  • a step of reducing a width of the mask layer may be added prior to the step of forming the first insulating film after performing the step of forming the first opening.
  • the step of forming the first insulating film may include a step of forming the first insulating film such that an upper surface of the first insulating film is further away from a surface of the semiconductor substrate than an upper surface of the gate insulating film. This method makes it possible to further suppress tilting of the gate electrode.
  • the second insulating film may be etched through an isotropic etching process to form the gate insulating film. This method makes it possible to easily form the gate insulating film below the center of the gate electrode.
  • the above-described method may further include the step of forming a word line which is electrically coupled with the gate electrode to be formed thereon, and extends across the bit line.
  • the charge storage layer may be formed of either a polysilicon film or a silicon nitride film.
  • the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction can be alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode.
  • FIG 1 is a sectional view of a flash memory of related art
  • FIG. 2 is a sectional view for illustrating a method for suppressing the interference of charge
  • FIG. 3 shows sectional views each illustrating an example of a method for forming separated charge storage layers:
  • FIG. 4 is a sectional view for illustrating a problem which occurs when forming the separated charge storage layers
  • FIG 5 is a top view of a flash memory according to a first embodiment of the present invention.
  • FIG. 6A is a sectional view taken along line A-A shown in FIG 5;
  • FIG. 6B is a sectional view taken along line B-B shown in FIG. 5;
  • FIG. 6C is a sectional view taken along line C-C shown in FIG. 5;
  • FIG 6D is a sectional view taken along line D-D shown in FIG. 5;
  • FIGS. 7A to 7C show a method (part 1) for manufacturing the flash memory according to the first embodiment, wherein FIG. 7A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG 7B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG 7C is a sectional view corresponding to the one taken along line C-C shown in FIG.
  • FIGS. 8A to 8C show the method (part 2) for manufacturing the flash memory according to the first embodiment, wherein FIG. 8A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG 8B is a sectional view corresponding to the one taken along line B-B shown in FIG 5, and FIG. 8C is a sectional view corresponding to the one taken along line C-C shown in FIG. 5;
  • FIGS. 9A to 9C show the method (part 3) for manufacturing the flash memory according to the first embodiment, wherein FIG. 9A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. 9B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 9C is a sectional view taken along line C-C shown in FIG 5;
  • FIGS. 1OA to 1OC show the method (part 4) for manufacturing the flash memory according to the first embodiment, wherein FIG 1OA is a sectional view corresponding to the one taken along line A-A shown in FIG 5, FIG. 1OB is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 1OC is a sectional view taken along line C-C shown in FIG. 5;
  • FIGS. HA to HC show the method (part 5) for manufacturing the flash memory according to the first embodiment, wherein FIG. 1 IA is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. HB is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 11C is a sectional view taken along line C-C shown in FIG 5;
  • FIGS. 12A to 12D show the method (part 6) for manufacturing the flash memory according to the first embodiment, wherein FIG.12A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. 12B is a sectional view corresponding to the one taken along line B-B shown in
  • FIG. 5 is a sectional view taken along line C-C shown in FIG. 5, and FIG. 12D is a sectional view taken along line D-D shown in FIG. 5;
  • FIGS. 13A to 13D show a method (part 1) for manufacturing a flash memory according to a second embodiment of the present invention, wherein FIGS. 13A and 13B are sectional views corresponding to those taken along line A-A shown in FIG 5, and FIGS. 13C and 13D are sectional views corresponding to those taken along line B-B shown in FIG. 5;
  • FIGS. 14A to 14D show the method (part 2) for manufacturing the flash memory according to the second embodiment, wherein FIGS. 14A and 14B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 14C and 14D are sectional views corresponding to those taken along line B-B shown in FIG. 5;
  • FIGS. 15A to 15D show the method (part 3) for manufacturing the flash memory according to the second embodiment, wherein FIGS. 15A and 15B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 15C and 15D are sectional views corresponding to those taken along line B-B shown in FIG. 5;
  • FIGS. 16A to 16D show a method (part 1) for manufacturing a flash memory according to a third embodiment of the present invention, wherein FIGS. 16A and 16B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 16C and 16D are sectional views corresponding to those taken along line B-B shown in FIG. 5; and
  • FIGS. 17Ato 17D show the method (part 2) for manufacturing the flash memory according to the third embodiment, wherein FIGS. 17A and 17B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 17C and 17D are sectional views corresponding to those taken along line B-B shown in FIG. 5.
  • CBD Complementary Bit Disturb
  • a method for suppressing the influence of the CBD has been proposed by employing the structure as shown in FIG. 2 to suppress the movement of the charge stored in the charge storage region in the channel direction.
  • a gate insulating film 22 is disposed on a semiconductor substrate 10 below the center of a gate electrode 24 between the bit lines 18.
  • Charge storage layers 14 are separated to interpose the gate insulating film 22.
  • the movement of the charge stored in the charge storage region in the channel direction may be controlled to suppress the influence of the CBD.
  • the gate insulating film 22 is disposed at the center of the channel, thus suppressing storage of charge in the center of the channel. This makes it possible to simultaneously prevent deterioration in the reliability of the continuous writing and reading operations.
  • FIGS. 3A to 3C A method for manufacturing the separated charge storage layers 14 will be described referring to FIGS. 3A to 3C.
  • the tunnel insulating film 12 and the top insulating film 16 are not shown, and explanation thereof, thus will be omitted for simplifying the description.
  • the gate electrode 24 is disposed on the semiconductor substrate 10 via the gate insulating film 22.
  • the gate insulating film 22 is etched from both side surfaces so as to be left below the center of the gate electrode 24.
  • FIG. 3C the charge storage layers 14 are formed in the regions where the gate insulating film 22 is etched. Then the separated charge storage layers 14 which interpose the gate insulating film 22 are formed.
  • FIG. 5 is a top view of a flash memory according to a first embodiment.
  • FIG. 6A is a sectional view taken along line A-A shown in FIG. 5.
  • FIG. 6B is a sectional view taken along line B-B shown in FIG. 5.
  • FIG. 6C is a sectional view taken along line C-C shown in FIG. 5.
  • FIG. 6A is a sectional view taken along line A-A shown in FIG. 5.
  • FIG. 6B is a sectional view taken along line B-B shown in FIG. 5.
  • FIG. 6C is a sectional view taken along line C-C shown in FIG. 5.
  • FIG. 6D is a sectional view taken along line D-D shown in FIG. 5.
  • a bit line 18 is shown through a first silicon oxide film 34 and an inter-layer insulating film 36.
  • the bit line 18 with an N-type diffusion region extends inside a semiconductor substrate 10 as a P-type silicon substrate.
  • a gate insulating film 22 as a silicon oxide film is formed on the semiconductor substrate 10 between the bit lines 18. Atunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially layered to interpose the gate insulating film 22.
  • Each of the tunnel insulating film 12 and the top insulating film 16 is formed of a silicon oxide film, and the charge storage layer 14 is formed of a polysilicon film. Those films form an OPO (Oxide Poly-Silicon Oxide) film 26 on the semiconductor substrate 10.
  • a gate electrode 24 formed of a polysilicon film is provided on the gate insulating film 22 and the OPO films 26. Second silicon oxide films 39 are formed on both side surfaces of the gate electrode 24.
  • a word line 20 is disposed on the gate electrode 24 to be electrically coupled therewith, and to extend across the bit lines 18. Referring to FIGS. 6B and 6C, the gate insulating film 22 is disposed on the semiconductor substrate 10 below the center of the gate electrode 24.
  • a groove (not shown) is formed in the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. That is, the groove is formed in the semiconductor substrate 10 around the gate electrode 24.
  • a first insulating film 30 formed of a silicon oxide film is applied to be embedded in the groove.
  • a protection film 32 formed of a silicon nitride film which is different from the material for forming the gate insulating film 22 and the first insulating film 30 is applied on the side surfaces and the bottom surface of the first insulating film 30.
  • the width of the first insulating film 30 in the width direction of the bit line 18 is larger than that of the gate insulating film 22.
  • the upper surface of the first insulating film 30 is further away from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22. In other words, the upper surface of the first insulating film 30 protrudes more than the upper surface of the gate insulating film 22. The upper surface of the first insulating film 30 is flush with that of the gate electrode 24.
  • the first silicon oxide film 34 is formed on the bit line 18.
  • the inter-layer insulating film 36 is formed between the word lines 20.
  • FIGS. 7A to 12D A method for manufacturing the flash memory according to the first embodiment will be described referring to FIGS. 7A to 12D.
  • FIGS. 7A, 8A, 9A, 1OA, HA and 12A is a sectional view corresponding to the one taken along line A-A shown in FIG 5.
  • HB and 12B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5.
  • FIGS. 7C, 8C, 9C, 1OC, IIC and 12C is a sectional view corresponding to the one taken along line C-C shown in FIG. 5.
  • FIG. 12D is a sectional view corresponding to the one taken along line D-D shown in FIG. 5.
  • a second insulating film 37 formed of a silicon oxide film is formed on the semiconductor substrate 10 as the P-type silicon substrate, through a thermal oxidation method.
  • a mask layer 38 formed of a silicon nitride film is formed on the second insulating film 37 through a CVD (Chemical Vapor Deposition) method.
  • the mask layer 38 includes an opening in regions other than the region where the bit line 18 and the gate electrode 24 are to be formed.
  • the second insulating film 37 and the semiconductor substrate 10 are partially etched through an RIE (Reactive Ion Etching) method using the mask layer 38 as a mask.
  • a first opening 40 is formed in the second insulating film 37 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed, and a groove 28 is formed inside the semiconductor substrate 10 at a lower portion of the first opening 40.
  • the silicon nitride film is applied to the entire surface to form the protection film 32 as the silicon nitride film on the side surfaces of the first opening 40 and the inner surface of the groove 28.
  • the first insulating film 30 as the silicon oxide film is formed through a high density plasma CVD method so as to be embedded in the first opening 40 and the groove 28.
  • the first insulating film 30 is formed such that its upper surface is further away from the surface of the semiconductor substrate 10 than the upper surface of the second insulating film 37. That is, the upper surface of the first insulating film 30 protrudes more than that of the second insulating film 37. Then, the protection film 32 formed on the mask layer 38 and the side surfaces thereof is removed. Thus, portions of the side surfaces of the first insulating film 30 that are embedded in the first opening 40 and the groove 28 is covered with the protection film 32.
  • a conducting layer 42 as a polysilicon film is formed on the first insulating film 30 and the second insulating film 37 through the CVD method.
  • the conducting layer 42, and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched through the RIE method.
  • a second opening 44 piercing through the conducting film 42 and the second insulating film 37 is formed.
  • the one formed on the second insulating film 37 serves as the gate electrode 24.
  • the length of the gate electrode 24 corresponding to the channel length is approximately 90 ran.
  • the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 through a wet etching method using hydrofluoric acid such that the second insulating film 37 below the center of the gate electrode 24 is left.
  • an undercut portion 35 which has the depth, from the side surface of the gate electrode 24, of approximately 30 nm is formed below each end of the gate electrode 24 by removing the second insulating film 37.
  • the gate insulating film 22 which is formed of the second insulating film 37 and has the width of approximately 30 nm is formed below the center of the gate electrode 24.
  • the first insulating film 30 is not etched because it is covered with the protection film 32.
  • the tunnel insulating film 12 and the top insulating film 16 each formed of the silicon oxide film are formed in the undercut portion 35 through the thermal oxidation method.
  • the side surface and the upper surface of the gate electrode 24 and the conducting layer 42 are also oxidized to form a second silicon oxide film 39.
  • a polysilicon film is formed on the semiconductor substrate 10 to cover the gate electrode 24 and the first insulating film 30 through a LP-CVD (Low-Pressure Chemical Vapor Deposition) method. Since the LP-CVD method is excellent in step-coverage characteristic, the polysilicon film is also formed in the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16.
  • LP-CVD Low-Pressure Chemical Vapor Deposition
  • the polysilicon film is oxidized through the thermal oxidation method to be formed as the second silicon oxide film 39.
  • the polysilicon film formed inside the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16 is unlikely to be oxidized because it locates to the back side of the region.
  • the polycilicon film is left to be formed as the charge storage layer 14.
  • the second silicon oxide film 39 formed on the semiconductor substrate 10 in the second opening 44 is removed. Arsenic ion is implanted into the semiconductor substrate 10 from the second opening 44.
  • the bit line 18, which is defined by the second opening 44 as the N-type diffusion region and which extends inside the semiconductor substrate is formed. Referring to FIGS.
  • the first silicon oxide film 34 is formed to be filled in the second opening 44 through the high density plasma CVD method. Then, the conducting layer 42 formed on the first insulating film 30 is polished through a CMP (Chemical Mechanical Polish) method so that the upper surface of the first insulating film 30 is exposed.
  • the word line 20 as the polysilicon film is formed on the gate electrode 24, which is electrically coupled therewith and extends across the bit line 18.
  • the inter-layer insulating film 36 as the silicon oxide film is formed between the word lines 20. The flash memory according to the first embodiment, thus, is produced.
  • the second insulating film 37 is formed on the semiconductor substrate 10 as shown in FIGS. 7A to 7C. Then, the second insulating film 37 formed on the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed is removed to form the first opening 40. As shown in FIGS. 8A to 8C, the first insulating film 30 is formed in the first opening 40. As shown in FIGS. 9A to 9C, the conducting layer 42 is formed on the second insulating film 37. The conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are removed to form the second opening 44. Then, the gate electrode 24 as the conducting layer 42 is formed between the second openings 44.
  • the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44, thereby forming the gate insulating film 22 as the second insulating film 37 below the center of the gate electrode 24.
  • the first insulating film 30 having a larger width and the gate insulating film 22 having a smaller width in the width direction of the bit line 18 are alternately arranged in the extending direction of the bit line 18.
  • the first insulating film 30 having the larger width formed adjacent to the gate insulating film 22 makes it possible to suppress tilting of the gate electrode 24 formed on the gate insulating film 22.
  • the first insulating film 30 in the first opening 40 and the groove 28 such that its upper surface is further away from the surface of the semiconductor substrate 10 than the upper surface of the second insulating film 37.
  • the upper surface of the first insulating film 30 is further away from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22.
  • the gate electrode 24 on the gate insulating film 22 is formed to be interposed between the first insulating films 30. The aforementioned structure is capable of further suppressing tilting of the gate electrode 24 formed on the gate insulating film 22 even when the width of the gate insulating film 22 is small.
  • the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 to form the undercut portion 35 below each end of the gate electrode 24 such that the gate insulating film 22 is formed below the center of the gate electrode 24.
  • the charge storage layer 14 is formed in the undercut portion 35 formed below each end of the gate electrode 24. This makes it possible to form the charge storage layers 14 separated to interpose the gate insulating film 22, thus suppressing the influence of the CBD.
  • the groove 28 is formed in the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. That is, the groove 28 is formed in the semiconductor substrate 10 at the lower portion of the first opening 40.
  • the first insulating film 30 is formed to be embedded in the groove 28. This makes it possible to form the first insulating film 30 in the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. In other words, the first insulating film 30 is formed inside the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. The first insulating film 30 is formed inside the semiconductor substrate 10 around the gate electrode 24 between the bit lines 18.
  • the protection film 32 is formed on the side surfaces of the first opening 40. Thereafter, as shown in FIGS. 8A to 8C, the first insulating film 30 is formed in the first opening 40. As a result, the protection film 32 is formed on the side surfaces of the first insulating film 30.
  • Each of the first insulating film 30 and the second insulating film 37 is formed of a silicon oxide film, and the protection film 32 is formed of a silicon nitride film. Referring to FIGS.
  • the protection film 32 is unlikely to be removed compared with the second insulating film 37. This makes it possible to leave the first insulating film 30 covered with the protection film 32 when the gate insulating film 22 is formed.
  • the first insulating film 30 having a larger width than that of the gate insulating film 22 can be easily formed.
  • the protection film 32 is formed of a material which is unlikely to be removed compared with the second insulating film 37 when the gate insulating film 22 is formed by removing the second insulating film 37 below the gate electrode 24.
  • the first insulating film 30 may be formed of a material which is unlikely to be removed compared with the second insulating film 37 when the gate insulating film 22 is formed by removing the second insulating film 37 below the gate electrode 24. In this case, the first insulating film 30 with the width larger than that of the gate insulating film 22 may be easily formed without forming the protection film 32 on the side surface of the first insulating film 30. This makes it possible to further reduce and simplify the manufacturing steps.
  • FIGS. 1OA to 1OC show, in the step of forming the gate insulating film 22 below the center of the gate electrode 24 by removing the second insulating film 37 formed below the gate electrode 24, it is preferable to remove the second insulating film 37 through the isotropic etching, for example, wet etching using hydrofluoric acid.
  • the gate insulating film 22 formed of the second insulating film 37 can be easily formed below the center of the gate electrode 24.
  • the word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18.
  • it is not limited to the aforementioned structure.
  • the wiring layer which extends across the bit line 18 is formed on the gate electrode 24 via the inter-layer insulating film such that the wiring layer and the gate electrode 24 are electrically coupled using the plug metal and the like provided for the inter-layer insulating film, instead of forming the word line 20.
  • the gate electrode 24 instead of using the gate electrode 24, a dummy film is formed in the region where the gate electrode 24 is to be formed, and the dummy film is removed before forming the word line 20. Then the word line 20 also serving as the gate may be formed so as to be embedded in the region where the dummy film has been removed.
  • the first insulating film 30 covered with the protection film 32 is unlikely to be removed. So the undercut portion 35 is unlikely to be formed below both ends of the first insulating film 30. In other words, the charge storage layer 14 is unlikely to be formed below both ends of the first insulating film 30.
  • the adjacent charge storage layers 14 in the extending direction of the bit line 18 are separated from each other. Even if the charge storage layer 14 is formed of a polysilicon film, charge may be locally stored below the gate electrode 24.
  • the charge storage layer 14 is not necessarily formed of the polysilicon film, but may be formed of a silicon nitride film or any material so long as the charge can be stored.
  • the first opening 40 is formed in the second insulating film 37, and thereafter, the width of the mask layer 38 is reduced before forming the first insulating film 30 in the first opening 40.
  • FIGS. 13A to 15D a method for manufacturing the flash memory according to the second embodiment will be described.
  • FIGS. 13A, 13B, 14A, 14B, 15A and 15B is the sectional view corresponding to the one taken along line A-A shown in FIG 5.
  • FIGS. 13C, 13D, 14C, 14D, 15C and 15D is the sectional view corresponding to the one taken along line B-B shown in FIG. 5.
  • the second insulating film 37 is formed on the semiconductor substrate 10.
  • the mask layer 38 having the opening is formed on the second insulating film 37 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed.
  • the second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer 38 as a mask.
  • the first opening 40 is formed in the second insulating film 37 as well as the groove 28 in the semiconductor substrate 10.
  • the etch back is performed in the mask layer 38 to reduce the width thereof to apply the protection film 32 over the entire surface.
  • the first insulating film 30 is formed to be embedded in the first opening 40 and the groove 28.
  • a width Tl of the upper portion of the first insulating film 30 becomes larger compared with the first embodiment. Then the mask layer 38 is removed.
  • the conducting layer 42 is formed on the first and the second insulating films 30 and 37.
  • the conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44.
  • a width T2 of the conducting layer 42 formed on the side surfaces of the upper portion of the first insulating film 30 after forming the second opening 44 becomes smaller compared with the first embodiment.
  • the conducting layer 42 formed on the second insulating film 37 becomes the gate electrode 24.
  • the second insulating film 37 below the gate electrode 24 is removed from the second opening 44 such that the second insulating film 37 below the center of the gate electrode 24 is left.
  • the undercut portion 35 as the region where the second insulating film 37 has been removed, is formed below both ends of the gate electrode 24, and the gate insulating film 22 as the second insulating film 37 is formed below the center of the gate electrode 24.
  • the tunnel insulating film 12 and the top insulating film 16 are formed in the undercut portion 35 through the thermal oxidation method.
  • the gate electrode 24 and the conducting layer 42 are also oxidized to have the second silicon oxide film 39 formed thereon.
  • the charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16.
  • the bit line 18 defined by the second opening 44 is formed to extend inside the semiconductor substrate 10.
  • the first silicon oxide film 34 is formed to be embedded in the second opening 44. Thereafter, the conducting layer 42 formed on the first insulating film 30 is polished such that the upper surface of the first insulating film 30 is exposed.
  • the word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18.
  • the inter-layer insulating film 36 is formed between the word lines 20. The flash memory according to the second embodiment, thus, is produced.
  • the width of the conducting layer 42 is increased in consideration with the displacement of the second opening 44. That is, there may be a case where the width of the conducting layer 42 formed on the side surfaces of the first insulating film 30 is increased. In such a case, upon oxidation of the side and upper surfaces of the conducting layer 42 as shown in FIGS. HA to HC, the conducting layer 42 formed on the side surfaces of the first insulating film 30 may be partially left rather than being completely oxidized. In the step of forming the word line 20 as shown in FIGS.
  • the time for performing the etching during the patterning of the word line 20 is increased to remove the conducting layer 42 formed on the side surfaces of the first insulating film 30. This prevents the gate electrodes 24 from being connected with each other in the extending direction of the bit line 18.
  • the width Tl of the upper portion of the first insulating film 30 may be increased as shown in FIGS. 13B and 13D by reducing the width of the mask layer 38 after forming the first opening 40 as FIGS. 13A and 13C show. Referring to FIGS. 14A and 14C, the width T2 of the conducting layer 42 formed on the side surface of the upper portion of the first insulating film 30 may be reduced. As FIGS.
  • FIGS. 16A to 17D a method for manufacturing the flash memory according to the third embodiment will be described.
  • FIGS. 16A, 16B, 17A and 17B is the sectional view corresponding to the one taken along line A-A shown in FIG. 5.
  • FIGS. 16C, 16D, 17C and 17D is the sectional view corresponding to the one taken along line B-B shown in FIG. 5.
  • the second insulating film 37 is formed on the semiconductor substrate 10.
  • a mask layer (not shown) is formed on the second insulating film 37, which has an opening in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed.
  • the second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer as a mask.
  • the first opening (not shown) is formed in the second insulating film 37 as well as the groove (not shown) in the semiconductor substrate 10.
  • a protection film 32a is formed on the side surface of the first opening and the inner surface of the groove.
  • the first insulating film 30 is formed to be embedded in the first opening and the groove.
  • a protection film 32b is formed on the exposed portion of the side surface of the first insulating film 30 in contact with the mask layer.
  • the protection film 32b may be formed by depositing the silicon nitride film over the entire surface, and then performing the etch back of the silicon nitride film.
  • the conducting layer 42 is formed on the first and the second insulating films 30 and 37.
  • the conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44.
  • the conducting layer 42 formed on the second insulating film 37 becomes the gate electrode 24.
  • the width T2 of the conducting layer 42 formed on each side of the first insulating film 30 is reduced by the protection film 32b formed on the side surface of the first insulating film 30.
  • the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 such that the second insulating film 37 below the center of the gate electrode 24 is left.
  • the undercut portion 35 is formed below each end of the gate electrode 24, thereby forming the gate insulating film 22 as the second insulating film 37 below the center of the gate electrode 24.
  • the tunnel insulating film 12 and the top insulating film 16 are formed in the undercut portion 35 through the thermal oxidation method.
  • the gate electrode 24 and the conducting layer 42 are also oxidized to have the second silicon oxide film 39 formed thereon.
  • the charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16.
  • the bit line 18 defined by the second opening 44 is formed to extend inside the semiconductor substrate 10.
  • the first silicon oxide film 34 is formed to be embedded in the second opening 44. Thereafter, the conducting layer 42 formed on the first insulating film 30 is polished such that the upper surface of the first insulating film 30 is exposed.
  • the word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18.
  • the inter-layer insulating film 36 is formed between the word lines 20. The flash memory according to the third embodiment is thus produced.
  • the protection film 32b is formed on the exposed portion of the side surface of the first insulating film 30 prior to the formation of the conducting layer 42. Accordingly, the side surface of the first insulating film 30 is completely covered with the protection films 32a and 32b. Referring to FIGS. 16B and 16D, the first insulating film 30 can be prevented from being removed when the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44. Therefore, the first insulating film 30 having a larger width than that of the gate insulating film 22 can be easily formed.
  • FIGS. 16B and 16D show, the width T2 of the conducting layer 42 formed at the side of the first insulating film 30 is small. As a result, the conducting layer 42 formed at the side of the first insulating film 30 is likely to be entirely oxidized as shown in FIGS. 17A and 17C. Likewise the second embodiment, this makes it possible to prevent the conducting layer 42 from being left at the side of the first insulating film 30.

Abstract

A semiconductor device includes a bit line 18 formed to extend inside a semiconductor substrate 10, a gate electrode 24 formed above the semiconductor substrate 10 between the bit lines 18, a gate insulating film 22 formed on the semiconductor substrate 10 below a center of the gate electrode 24, charge storage layers 14 formed on the semiconductor substrate 10 below the gate electrode 24 to interpose the gate insulating film 22 in a width direction of the bit line 18, and a first insulating film formed on the semiconductor substrate 10 between the gate electrodes 24 in an extending direction of the bit line 18. A width of a first insulating film 30 in the width direction of the bit line 18 is larger than that of the gate insulating film 22.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing thereof. More particularly, the present invention relates to a semiconductor device including separated charge storage layers and a method for manufacturing thereof.
Background of the Invention
A non-volatile memory as a semiconductor device capable of rewiring data, and retaining stored data after turning the power OFF has been widely used. In a flash memory as a representative non-volatile memory, a transistor which forms a memory cell includes a floating gate or an insulating film so called a charge storage layer for accumulating charges to store data. A flash memory with a SONOS (Silicon Oxide Nitride Oxide Silicon) structure having charge accumulated in the charge storage layer inside an ONO (Oxide Nitride Oxide) film has been introduced as the one having the insulating film serving as the charge storage layer. United State Patent No. 6011725 discloses the flash memory with a virtual ground type memory cell for symmetrically operating a source and a drain which may be switchable as one of the SONOS type flash memories.
FIG. 1 is a sectional view of the flash memory disclosed in USP No. 6011725. Referring to FIG 1, a tunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially layered on a semiconductor substrate 10. Bit lines 18 each serving as a source and a drain extend inside the semiconductor substrate 10. A gate electrode 24 is formed on the top insulating film 16 between the bit lines 18. A distance L between the bit lines 18 is a channel length.
The source and the drain may be set and operated by switching between the bit lines 18 (BLl) and 18 (BL2) so as to accumulate the charge in charge storage regions Cl and C2, respectively. This makes it possible to store 2-bit data in a single transistor.
For example, Japanese Patent Application Publication NO. JP-A-2005-108915 and Japanese Patent Application Publication NO. JP-A-2004-343014 disclose a process for forming charge storage layers in a separated state. Specifically, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a side wall of the gate electrode, or the side wall of the gate electrode and the gate insulating film are partially removed to form the separated charge storage layers in the thus removed regions.
Summary of the Invention
It is an object of the present invention to provide a semiconductor device and a method for manufacturing thereof capable of suppressing tilting of a gate electrode when a gate insulating film is formed below the center of the gate electrode.
The present invention provides a semiconductor device which includes a bit line formed to extend inside a semiconductor substrate, a gate electrode formed above the semiconductor substrate between the bit lines, a gate insulating film formed on the semiconductor substrate below a center of the gate electrode, charge storage layers each formed on the semiconductor substrate below the gate electrode to interpose the gate insulating film in a width direction of the bit line, and a first insulating film formed on the semiconductor substrate between the gate electrodes in an extending direction of the bit line. A width of the first insulating film in the width direction of the bit line is larger than a width of the gate insulating film. In this structure, the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction are alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode. The charge storage layers are separately formed to interpose the gate insulating film in the bit line width direction, thus suppressing the influence of CBD (Complementary Bit Disturb). In the above-described structure, the first insulating film may be embedded in a groove formed in the semiconductor substrate between the gate electrodes in the extending direction of the bit line. This structure makes it possible to suppress fringe current flowing in the semiconductor substrate around the gate electrode.
The above-described structure may further include a protection film formed on a side surface of the first insulating film. The protection film may be formed of a material which is different from a material for forming the gate insulating film and a material for forming the first insulating film. This structure allows easy formation of the first insulating film having a larger width than that of the gate insulating film.
In the above-described structure, each of the gate insulating film and the first insulating film may be formed of a silicon oxide film, and the protection film may be formed of a silicon nitride film.
In the above-described structure, an upper surface of the first insulating film may be formed further away from a surface of the semiconductor substrate than an upper surface of the gate insulating film. This structure can further suppress tilting of the gate electrode.
The above-described structure may further include a word line which is electrically coupled with the gate electrode to be formed thereon, and extends across the bit line. Further, in the above-described structure, the charge storage layer may be formed of either a polysilicon film or a silicon nitride film.
The present invention provides a method for manufacturing a semiconductor device, which includes the steps of: forming a second insulating film on a semiconductor substrate; forming a first opening in the second insulating film by removing the second insulating film formed on the semiconductor substrate in a region other than a region where a bit line and a gate electrode are to be formed; forming a first insulating film in the first opening; forming a conducting layer on the second insulating film; forming second openings by removing the conducting layer and the second insulating layer formed on the semiconductor substrate in a region where the bit line is to be formed, and forming the gate electrode as the conducting layer between the second openings; forming a gate insulating film as the second insulating film below a center of the gate electrode, by removing the second insulating film formed below the gate electrode from the second opening; forming a charge storage layer in a region where the second insulating film formed below the gate electrode has been removed; and forming the bit line defined by each of the second openings in the semiconductor substrate. In this method, the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction are alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode. Further, the separated charge storage layers can be formed to interpose the gate insulating film in the bit line width direction. Thus, it is possible to suppress the influence of the CBD.
The above-described method may further include the step of forming a groove in the semiconductor substrate at a lower portion of the first opening. The step of forming the first insulating film may include a step of forming the first insulating film in the groove. This method makes it possible to suppress fringe current flowing in the semiconductor substrate around the gate electrode. In the above-described method, the first insulating film may be formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode. This method makes it possible to easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction. The above-described method may further include the step of forming a protection film on a side surface of the first opening prior to the step of forming the first insulating film. The protection film may be formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode. This method makes it possible to easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction.
The above-described method may further include the step of forming the protection film on an exposed portion of a side surface of the first insulating film prior to the step of forming the conducting layer after performing the step of forming the first insulating film. This method makes it possible to further easily form the first insulating film having a larger width than that of the gate insulating film in the bit line width direction. In the above-described method, each of the first and the second insulating films may be formed of a silicon oxide film, and the protection film may be formed of a silicon nitride film.
In the step of forming the first opening in the above-described method, the second insulating film may be removed using a mask layer formed on the second insulating film to form the first opening. A step of reducing a width of the mask layer may be added prior to the step of forming the first insulating film after performing the step of forming the first opening.
In the above-described method, the step of forming the first insulating film may include a step of forming the first insulating film such that an upper surface of the first insulating film is further away from a surface of the semiconductor substrate than an upper surface of the gate insulating film. This method makes it possible to further suppress tilting of the gate electrode.
In the step of forming the gate insulating film in the above-described method, the second insulating film may be etched through an isotropic etching process to form the gate insulating film. This method makes it possible to easily form the gate insulating film below the center of the gate electrode.
The above-described method may further include the step of forming a word line which is electrically coupled with the gate electrode to be formed thereon, and extends across the bit line. Further, in the above-described method, the charge storage layer may be formed of either a polysilicon film or a silicon nitride film.
According to the present invention, the first insulating film having a larger width and the gate insulating film having a smaller width in the bit line width direction can be alternately arranged in the extending direction of the bit line. This makes it possible to suppress tilting of the gate electrode when the gate insulating film having the smaller width in the bit line width direction is formed below the center of the gate electrode.
Brief Description of the Drawings FIG 1 is a sectional view of a flash memory of related art;
FIG. 2 is a sectional view for illustrating a method for suppressing the interference of charge; FIG. 3 shows sectional views each illustrating an example of a method for forming separated charge storage layers:
FIG. 4 is a sectional view for illustrating a problem which occurs when forming the separated charge storage layers;
FIG 5 is a top view of a flash memory according to a first embodiment of the present invention;
FIG. 6A is a sectional view taken along line A-A shown in FIG 5; FIG. 6B is a sectional view taken along line B-B shown in FIG. 5; FIG. 6C is a sectional view taken along line C-C shown in FIG. 5; and FIG 6D is a sectional view taken along line D-D shown in FIG. 5; FIGS. 7A to 7C show a method (part 1) for manufacturing the flash memory according to the first embodiment, wherein FIG. 7A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG 7B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG 7C is a sectional view corresponding to the one taken along line C-C shown in FIG. 5; FIGS. 8A to 8C show the method (part 2) for manufacturing the flash memory according to the first embodiment, wherein FIG. 8A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG 8B is a sectional view corresponding to the one taken along line B-B shown in FIG 5, and FIG. 8C is a sectional view corresponding to the one taken along line C-C shown in FIG. 5;
FIGS. 9A to 9C show the method (part 3) for manufacturing the flash memory according to the first embodiment, wherein FIG. 9A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. 9B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 9C is a sectional view taken along line C-C shown in FIG 5;
FIGS. 1OA to 1OC show the method (part 4) for manufacturing the flash memory according to the first embodiment, wherein FIG 1OA is a sectional view corresponding to the one taken along line A-A shown in FIG 5, FIG. 1OB is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 1OC is a sectional view taken along line C-C shown in FIG. 5;
FIGS. HA to HC show the method (part 5) for manufacturing the flash memory according to the first embodiment, wherein FIG. 1 IA is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. HB is a sectional view corresponding to the one taken along line B-B shown in FIG. 5, and FIG. 11C is a sectional view taken along line C-C shown in FIG 5;
FIGS. 12A to 12D show the method (part 6) for manufacturing the flash memory according to the first embodiment, wherein FIG.12A is a sectional view corresponding to the one taken along line A-A shown in FIG. 5, FIG. 12B is a sectional view corresponding to the one taken along line B-B shown in
FIG. 5, FIG. 12C is a sectional view taken along line C-C shown in FIG. 5, and FIG. 12D is a sectional view taken along line D-D shown in FIG. 5;
FIGS. 13A to 13D show a method (part 1) for manufacturing a flash memory according to a second embodiment of the present invention, wherein FIGS. 13A and 13B are sectional views corresponding to those taken along line A-A shown in FIG 5, and FIGS. 13C and 13D are sectional views corresponding to those taken along line B-B shown in FIG. 5; FIGS. 14A to 14D show the method (part 2) for manufacturing the flash memory according to the second embodiment, wherein FIGS. 14A and 14B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 14C and 14D are sectional views corresponding to those taken along line B-B shown in FIG. 5;
FIGS. 15A to 15D show the method (part 3) for manufacturing the flash memory according to the second embodiment, wherein FIGS. 15A and 15B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 15C and 15D are sectional views corresponding to those taken along line B-B shown in FIG. 5;
FIGS. 16A to 16D show a method (part 1) for manufacturing a flash memory according to a third embodiment of the present invention, wherein FIGS. 16A and 16B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 16C and 16D are sectional views corresponding to those taken along line B-B shown in FIG. 5; and
FIGS. 17Ato 17D show the method (part 2) for manufacturing the flash memory according to the third embodiment, wherein FIGS. 17A and 17B are sectional views corresponding to those taken along line A-A shown in FIG. 5, and FIGS. 17C and 17D are sectional views corresponding to those taken along line B-B shown in FIG. 5.
Detailed Description
An explanation with respect to the problem to be solved will be described hereinafter. When the channel length is reduced for realizing the high integration and miniaturization of a memory cell, the influence resulting from the interference of charges stored in a charge storage region, so called CBD (Complementary Bit Disturb) may be intensified. This makes it difficult to separate the respective charges (that is, to read data separately).
A method for suppressing the influence of the CBD has been proposed by employing the structure as shown in FIG. 2 to suppress the movement of the charge stored in the charge storage region in the channel direction. Referring to FIG. 2, a gate insulating film 22 is disposed on a semiconductor substrate 10 below the center of a gate electrode 24 between the bit lines 18. Charge storage layers 14 are separated to interpose the gate insulating film 22. In the aforementioned structure where the separated charge storage layers 14 interpose the gate insulating film 22, the movement of the charge stored in the charge storage region in the channel direction may be controlled to suppress the influence of the CBD.
If the channel length becomes short, the charge is likely to be stored into the charge storage layer at the center of the channel, thus deteriorating reliability in continuous reading and writing operations. In the structure shown in FIG. 2, the gate insulating film 22 is disposed at the center of the channel, thus suppressing storage of charge in the center of the channel. This makes it possible to simultaneously prevent deterioration in the reliability of the continuous writing and reading operations.
A method for manufacturing the separated charge storage layers 14 will be described referring to FIGS. 3A to 3C. The tunnel insulating film 12 and the top insulating film 16 are not shown, and explanation thereof, thus will be omitted for simplifying the description. Referring to FIG. 3A, the gate electrode 24 is disposed on the semiconductor substrate 10 via the gate insulating film 22. Referring to FIG 3B, the gate insulating film 22 is etched from both side surfaces so as to be left below the center of the gate electrode 24. Referring to FIG. 3C, the charge storage layers 14 are formed in the regions where the gate insulating film 22 is etched. Then the separated charge storage layers 14 which interpose the gate insulating film 22 are formed.
When the gate insulating film 22 is etched from both side surfaces as shown in FIG. 3B, the width of the gate insulating film 22 is reduced. Accordingly, there are some cases where the gate electrode 24 falls as shown in FIG. 4. In order to solve the aforementioned problem, the following embodiments are provided to suppress tilting of the gate electrode when the gate insulating film is formed below the center of the gate electrode. First Embodiment FIG. 5 is a top view of a flash memory according to a first embodiment. FIG. 6A is a sectional view taken along line A-A shown in FIG. 5. FIG. 6B is a sectional view taken along line B-B shown in FIG. 5. FIG. 6C is a sectional view taken along line C-C shown in FIG. 5. FIG. 6D is a sectional view taken along line D-D shown in FIG. 5. Referring to FIG. 5, a bit line 18 is shown through a first silicon oxide film 34 and an inter-layer insulating film 36. Referring to FIG. 5 and FIG. 6B, the bit line 18 with an N-type diffusion region extends inside a semiconductor substrate 10 as a P-type silicon substrate. A gate insulating film 22 as a silicon oxide film is formed on the semiconductor substrate 10 between the bit lines 18. Atunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially layered to interpose the gate insulating film 22. Each of the tunnel insulating film 12 and the top insulating film 16 is formed of a silicon oxide film, and the charge storage layer 14 is formed of a polysilicon film. Those films form an OPO (Oxide Poly-Silicon Oxide) film 26 on the semiconductor substrate 10. A gate electrode 24 formed of a polysilicon film is provided on the gate insulating film 22 and the OPO films 26. Second silicon oxide films 39 are formed on both side surfaces of the gate electrode 24. A word line 20 is disposed on the gate electrode 24 to be electrically coupled therewith, and to extend across the bit lines 18. Referring to FIGS. 6B and 6C, the gate insulating film 22 is disposed on the semiconductor substrate 10 below the center of the gate electrode 24.
Referring to FIGS. 5, 6A, 6C and 6D, a groove (not shown) is formed in the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. That is, the groove is formed in the semiconductor substrate 10 around the gate electrode 24. A first insulating film 30 formed of a silicon oxide film is applied to be embedded in the groove. A protection film 32 formed of a silicon nitride film which is different from the material for forming the gate insulating film 22 and the first insulating film 30 is applied on the side surfaces and the bottom surface of the first insulating film 30. Referring to FIGS. 6A and 6B, the width of the first insulating film 30 in the width direction of the bit line 18 is larger than that of the gate insulating film 22. Referring to FIG 6C, the upper surface of the first insulating film 30 is further away from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22. In other words, the upper surface of the first insulating film 30 protrudes more than the upper surface of the gate insulating film 22. The upper surface of the first insulating film 30 is flush with that of the gate electrode 24.
Referring to FIGS. 6A and 6B, the first silicon oxide film 34 is formed on the bit line 18. Referring to FIGS. 6A, 6C and 6D, the inter-layer insulating film 36 is formed between the word lines 20.
A method for manufacturing the flash memory according to the first embodiment will be described referring to FIGS. 7A to 12D. Each of FIGS. 7A, 8A, 9A, 1OA, HA and 12A is a sectional view corresponding to the one taken along line A-A shown in FIG 5. Each of FIGS. 7B, 8B, 9B, 1OB,
HB and 12B is a sectional view corresponding to the one taken along line B-B shown in FIG. 5. Each of FIGS. 7C, 8C, 9C, 1OC, IIC and 12C is a sectional view corresponding to the one taken along line C-C shown in FIG. 5. FIG. 12D is a sectional view corresponding to the one taken along line D-D shown in FIG. 5.
Referring to FIGS. 7A to 7C, a second insulating film 37 formed of a silicon oxide film is formed on the semiconductor substrate 10 as the P-type silicon substrate, through a thermal oxidation method. A mask layer 38 formed of a silicon nitride film is formed on the second insulating film 37 through a CVD (Chemical Vapor Deposition) method. The mask layer 38 includes an opening in regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. The second insulating film 37 and the semiconductor substrate 10 are partially etched through an RIE (Reactive Ion Etching) method using the mask layer 38 as a mask. As a result, a first opening 40 is formed in the second insulating film 37 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed, and a groove 28 is formed inside the semiconductor substrate 10 at a lower portion of the first opening 40. Thereafter, using the CVD method, the silicon nitride film is applied to the entire surface to form the protection film 32 as the silicon nitride film on the side surfaces of the first opening 40 and the inner surface of the groove 28. Referring to FIGS. 8A to 8C, the first insulating film 30 as the silicon oxide film is formed through a high density plasma CVD method so as to be embedded in the first opening 40 and the groove 28. The first insulating film 30 is formed such that its upper surface is further away from the surface of the semiconductor substrate 10 than the upper surface of the second insulating film 37. That is, the upper surface of the first insulating film 30 protrudes more than that of the second insulating film 37. Then, the protection film 32 formed on the mask layer 38 and the side surfaces thereof is removed. Thus, portions of the side surfaces of the first insulating film 30 that are embedded in the first opening 40 and the groove 28 is covered with the protection film 32.
Referring to FIGS. 9A to 9C, a conducting layer 42 as a polysilicon film is formed on the first insulating film 30 and the second insulating film 37 through the CVD method. The conducting layer 42, and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched through the RIE method. As a result, a second opening 44 piercing through the conducting film 42 and the second insulating film 37 is formed. Among the conducting layers 42 formed between the second openings 44, the one formed on the second insulating film 37 serves as the gate electrode 24. The length of the gate electrode 24 corresponding to the channel length is approximately 90 ran.
Referring to FIGS. 1OA to 1OC, the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 through a wet etching method using hydrofluoric acid such that the second insulating film 37 below the center of the gate electrode 24 is left. As a result, an undercut portion 35 which has the depth, from the side surface of the gate electrode 24, of approximately 30 nm is formed below each end of the gate electrode 24 by removing the second insulating film 37. Accordingly, the gate insulating film 22 which is formed of the second insulating film 37 and has the width of approximately 30 nm is formed below the center of the gate electrode 24. The first insulating film 30 is not etched because it is covered with the protection film 32.
Referring to FIGS. HA to HC, the tunnel insulating film 12 and the top insulating film 16 each formed of the silicon oxide film are formed in the undercut portion 35 through the thermal oxidation method. At this time, the side surface and the upper surface of the gate electrode 24 and the conducting layer 42 are also oxidized to form a second silicon oxide film 39. Thereafter, a polysilicon film is formed on the semiconductor substrate 10 to cover the gate electrode 24 and the first insulating film 30 through a LP-CVD (Low-Pressure Chemical Vapor Deposition) method. Since the LP-CVD method is excellent in step-coverage characteristic, the polysilicon film is also formed in the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16. The polysilicon film is oxidized through the thermal oxidation method to be formed as the second silicon oxide film 39. The polysilicon film formed inside the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16 is unlikely to be oxidized because it locates to the back side of the region. As a result, the polycilicon film is left to be formed as the charge storage layer 14. Then, the second silicon oxide film 39 formed on the semiconductor substrate 10 in the second opening 44 is removed. Arsenic ion is implanted into the semiconductor substrate 10 from the second opening 44. Thus, the bit line 18, which is defined by the second opening 44 as the N-type diffusion region and which extends inside the semiconductor substrate, is formed. Referring to FIGS. 12A to 12D, the first silicon oxide film 34 is formed to be filled in the second opening 44 through the high density plasma CVD method. Then, the conducting layer 42 formed on the first insulating film 30 is polished through a CMP (Chemical Mechanical Polish) method so that the upper surface of the first insulating film 30 is exposed. The word line 20 as the polysilicon film is formed on the gate electrode 24, which is electrically coupled therewith and extends across the bit line 18. The inter-layer insulating film 36 as the silicon oxide film is formed between the word lines 20. The flash memory according to the first embodiment, thus, is produced.
In the first embodiment, the second insulating film 37 is formed on the semiconductor substrate 10 as shown in FIGS. 7A to 7C. Then, the second insulating film 37 formed on the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed is removed to form the first opening 40. As shown in FIGS. 8A to 8C, the first insulating film 30 is formed in the first opening 40. As shown in FIGS. 9A to 9C, the conducting layer 42 is formed on the second insulating film 37. The conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are removed to form the second opening 44. Then, the gate electrode 24 as the conducting layer 42 is formed between the second openings 44. Referring to FIGS. 1OA to 1OC, the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44, thereby forming the gate insulating film 22 as the second insulating film 37 below the center of the gate electrode 24. Through the aforementioned process, the first insulating film 30 having a larger width and the gate insulating film 22 having a smaller width in the width direction of the bit line 18 are alternately arranged in the extending direction of the bit line 18. In the case where the gate insulating film 22 having the smaller width is formed below the center of the gate electrode 24, the first insulating film 30 having the larger width formed adjacent to the gate insulating film 22 makes it possible to suppress tilting of the gate electrode 24 formed on the gate insulating film 22.
As FIGS. 8A to 8C show, it is preferable to form the first insulating film 30 in the first opening 40 and the groove 28 such that its upper surface is further away from the surface of the semiconductor substrate 10 than the upper surface of the second insulating film 37. Preferably, as FIG. 6C shows, the upper surface of the first insulating film 30 is further away from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22. In the aforementioned case, the gate electrode 24 on the gate insulating film 22 is formed to be interposed between the first insulating films 30. The aforementioned structure is capable of further suppressing tilting of the gate electrode 24 formed on the gate insulating film 22 even when the width of the gate insulating film 22 is small.
As FIGS. 1OA to 1OC show, the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 to form the undercut portion 35 below each end of the gate electrode 24 such that the gate insulating film 22 is formed below the center of the gate electrode 24. As FIGS. HA to HC show, the charge storage layer 14 is formed in the undercut portion 35 formed below each end of the gate electrode 24. This makes it possible to form the charge storage layers 14 separated to interpose the gate insulating film 22, thus suppressing the influence of the CBD.
As FIGS. 7A to 7C show, the groove 28 is formed in the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. That is, the groove 28 is formed in the semiconductor substrate 10 at the lower portion of the first opening 40. As FIGS. 8A to 8C show, the first insulating film 30 is formed to be embedded in the groove 28. This makes it possible to form the first insulating film 30 in the semiconductor substrate 10 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. In other words, the first insulating film 30 is formed inside the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. The first insulating film 30 is formed inside the semiconductor substrate 10 around the gate electrode 24 between the bit lines 18. This makes it possible to suppress fringe current flowing in the semiconductor substrate 10 around the gate electrode 24. The fringe current may cause a malfunction while reading data. Accordingly, if the fringe current is suppressed, the data reading characteristic can be further improved. As FIGS. 7A to 7C show, the protection film 32 is formed on the side surfaces of the first opening 40. Thereafter, as shown in FIGS. 8A to 8C, the first insulating film 30 is formed in the first opening 40. As a result, the protection film 32 is formed on the side surfaces of the first insulating film 30. Each of the first insulating film 30 and the second insulating film 37 is formed of a silicon oxide film, and the protection film 32 is formed of a silicon nitride film. Referring to FIGS. 1OA to 1OC, when the gate insulating film 22 is formed by removing the second insulating film 37 formed below the gate electrode 24 from the second opening 44, the protection film 32 is unlikely to be removed compared with the second insulating film 37. This makes it possible to leave the first insulating film 30 covered with the protection film 32 when the gate insulating film 22 is formed. The first insulating film 30 having a larger width than that of the gate insulating film 22 can be easily formed. Preferably, the protection film 32 is formed of a material which is unlikely to be removed compared with the second insulating film 37 when the gate insulating film 22 is formed by removing the second insulating film 37 below the gate electrode 24.
The first insulating film 30 may be formed of a material which is unlikely to be removed compared with the second insulating film 37 when the gate insulating film 22 is formed by removing the second insulating film 37 below the gate electrode 24. In this case, the first insulating film 30 with the width larger than that of the gate insulating film 22 may be easily formed without forming the protection film 32 on the side surface of the first insulating film 30. This makes it possible to further reduce and simplify the manufacturing steps.
As FIGS. 1OA to 1OC show, in the step of forming the gate insulating film 22 below the center of the gate electrode 24 by removing the second insulating film 37 formed below the gate electrode 24, it is preferable to remove the second insulating film 37 through the isotropic etching, for example, wet etching using hydrofluoric acid. In this case, as the second insulating film 37 at both side surfaces is simultaneously removed, the gate insulating film 22 formed of the second insulating film 37 can be easily formed below the center of the gate electrode 24. Referring to FIGS. 12A to 12D, the word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18. However, it is not limited to the aforementioned structure. For example, the wiring layer which extends across the bit line 18 is formed on the gate electrode 24 via the inter-layer insulating film such that the wiring layer and the gate electrode 24 are electrically coupled using the plug metal and the like provided for the inter-layer insulating film, instead of forming the word line 20. Instead of using the gate electrode 24, a dummy film is formed in the region where the gate electrode 24 is to be formed, and the dummy film is removed before forming the word line 20. Then the word line 20 also serving as the gate may be formed so as to be embedded in the region where the dummy film has been removed.
Referring to FIGS. 1OA to 1OC, when the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44, the first insulating film 30 covered with the protection film 32 is unlikely to be removed. So the undercut portion 35 is unlikely to be formed below both ends of the first insulating film 30. In other words, the charge storage layer 14 is unlikely to be formed below both ends of the first insulating film 30. Among the charge storage layers 14 formed below both ends of the gate electrode 24, the adjacent charge storage layers 14 in the extending direction of the bit line 18 are separated from each other. Even if the charge storage layer 14 is formed of a polysilicon film, charge may be locally stored below the gate electrode 24. The charge storage layer 14 is not necessarily formed of the polysilicon film, but may be formed of a silicon nitride film or any material so long as the charge can be stored. Second Embodiment In a second embodiment, the first opening 40 is formed in the second insulating film 37, and thereafter, the width of the mask layer 38 is reduced before forming the first insulating film 30 in the first opening 40. Referring to FIGS. 13A to 15D, a method for manufacturing the flash memory according to the second embodiment will be described. Each of FIGS. 13A, 13B, 14A, 14B, 15A and 15B is the sectional view corresponding to the one taken along line A-A shown in FIG 5. Each of FIGS. 13C, 13D, 14C, 14D, 15C and 15D is the sectional view corresponding to the one taken along line B-B shown in FIG. 5.
Referring to FIGS. 13A and 13C, the second insulating film 37 is formed on the semiconductor substrate 10. The mask layer 38 having the opening is formed on the second insulating film 37 in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. The second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer 38 as a mask. As a result, the first opening 40 is formed in the second insulating film 37 as well as the groove 28 in the semiconductor substrate 10. The etch back is performed in the mask layer 38 to reduce the width thereof to apply the protection film 32 over the entire surface.
Referring to FIGS. 13B and 13D, the first insulating film 30 is formed to be embedded in the first opening 40 and the groove 28. As the width of the mask layer 38 is smaller compared with the first embodiment, a width Tl of the upper portion of the first insulating film 30 becomes larger compared with the first embodiment. Then the mask layer 38 is removed.
Referring to FIGS. 14A to 14C, the conducting layer 42 is formed on the first and the second insulating films 30 and 37. The conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44. As the width Tl of the upper portion of the first insulating film 30 is larger than the one in the first embodiment, a width T2 of the conducting layer 42 formed on the side surfaces of the upper portion of the first insulating film 30 after forming the second opening 44 becomes smaller compared with the first embodiment. Among the conducting layers 42 formed between the second openings 44, the conducting layer 42 formed on the second insulating film 37 becomes the gate electrode 24.
Referring to FIGS. 14B and 14D, the second insulating film 37 below the gate electrode 24 is removed from the second opening 44 such that the second insulating film 37 below the center of the gate electrode 24 is left. As a result, the undercut portion 35, as the region where the second insulating film 37 has been removed, is formed below both ends of the gate electrode 24, and the gate insulating film 22 as the second insulating film 37 is formed below the center of the gate electrode 24.
Referring to FIGS. 15A and 15C, the tunnel insulating film 12 and the top insulating film 16 are formed in the undercut portion 35 through the thermal oxidation method. At this time, the gate electrode 24 and the conducting layer 42 are also oxidized to have the second silicon oxide film 39 formed thereon. The charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16. The bit line 18 defined by the second opening 44 is formed to extend inside the semiconductor substrate 10.
Referring to FIGS. 15B and 15D, the first silicon oxide film 34 is formed to be embedded in the second opening 44. Thereafter, the conducting layer 42 formed on the first insulating film 30 is polished such that the upper surface of the first insulating film 30 is exposed. The word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18. The inter-layer insulating film 36 is formed between the word lines 20. The flash memory according to the second embodiment, thus, is produced.
In the step of forming the second opening 44 shown in FIGS. 9A to 9C according to the first embodiment, the width of the conducting layer 42 is increased in consideration with the displacement of the second opening 44. That is, there may be a case where the width of the conducting layer 42 formed on the side surfaces of the first insulating film 30 is increased. In such a case, upon oxidation of the side and upper surfaces of the conducting layer 42 as shown in FIGS. HA to HC, the conducting layer 42 formed on the side surfaces of the first insulating film 30 may be partially left rather than being completely oxidized. In the step of forming the word line 20 as shown in FIGS. 12A to 12D, the time for performing the etching during the patterning of the word line 20 is increased to remove the conducting layer 42 formed on the side surfaces of the first insulating film 30. This prevents the gate electrodes 24 from being connected with each other in the extending direction of the bit line 18. In the second embodiment, the width Tl of the upper portion of the first insulating film 30 may be increased as shown in FIGS. 13B and 13D by reducing the width of the mask layer 38 after forming the first opening 40 as FIGS. 13A and 13C show. Referring to FIGS. 14A and 14C, the width T2 of the conducting layer 42 formed on the side surface of the upper portion of the first insulating film 30 may be reduced. As FIGS. 15A and 15C show, when the tunnel insulating film 12 and the top insulating film 16 are formed through the thermal oxidation method, the conducting layer 42 formed on the side surfaces of the first insulating film 30 is likely to be entirely oxidized, thus preventing the conducting layer 42 from being left on the side surfaces of the first insulating film 30. Third Embodiment
In a third embodiment, after forming the first insulating film 30, the protection film is formed on the exposed portion of the side surface of the first insulating film 30 prior to formation of the conducting layer 42. Referring to FIGS. 16A to 17D, a method for manufacturing the flash memory according to the third embodiment will be described. Each of FIGS. 16A, 16B, 17A and 17B is the sectional view corresponding to the one taken along line A-A shown in FIG. 5. Each of FIGS. 16C, 16D, 17C and 17D is the sectional view corresponding to the one taken along line B-B shown in FIG. 5.
Referring to FIGS. 16A and 16C, the second insulating film 37 is formed on the semiconductor substrate 10. A mask layer (not shown) is formed on the second insulating film 37, which has an opening in the regions other than the region where the bit line 18 and the gate electrode 24 are to be formed. The second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer as a mask. Then, the first opening (not shown) is formed in the second insulating film 37 as well as the groove (not shown) in the semiconductor substrate 10. A protection film 32a is formed on the side surface of the first opening and the inner surface of the groove. The first insulating film 30 is formed to be embedded in the first opening and the groove. The mask layer is removed, and then, a protection film 32b is formed on the exposed portion of the side surface of the first insulating film 30 in contact with the mask layer. The protection film 32b may be formed by depositing the silicon nitride film over the entire surface, and then performing the etch back of the silicon nitride film. Referring to FIGS. 16B and 16D, the conducting layer 42 is formed on the first and the second insulating films 30 and 37. The conducting layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44. Among the conducting layers 42 formed between the second openings 44, the conducting layer 42 formed on the second insulating film 37 becomes the gate electrode 24. The width T2 of the conducting layer 42 formed on each side of the first insulating film 30 is reduced by the protection film 32b formed on the side surface of the first insulating film 30. The second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44 such that the second insulating film 37 below the center of the gate electrode 24 is left. As a result, the undercut portion 35, as the region where the second insulating film 37 has been removed, is formed below each end of the gate electrode 24, thereby forming the gate insulating film 22 as the second insulating film 37 below the center of the gate electrode 24.
Referring to FIGS. 17A and 17C, the tunnel insulating film 12 and the top insulating film 16 are formed in the undercut portion 35 through the thermal oxidation method. At this time, the gate electrode 24 and the conducting layer 42 are also oxidized to have the second silicon oxide film 39 formed thereon. The charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16. The bit line 18 defined by the second opening 44 is formed to extend inside the semiconductor substrate 10.
Referring to FIGS. 17B and 17D, the first silicon oxide film 34 is formed to be embedded in the second opening 44. Thereafter, the conducting layer 42 formed on the first insulating film 30 is polished such that the upper surface of the first insulating film 30 is exposed. The word line 20 is formed on the gate electrode 24, such that it is electrically coupled with the gate electrode 24 and extends across the bit line 18. The inter-layer insulating film 36 is formed between the word lines 20. The flash memory according to the third embodiment is thus produced.
In the third embodiment, after forming the first insulating film 30 as FIGS. 16A and 16C show, the protection film 32b is formed on the exposed portion of the side surface of the first insulating film 30 prior to the formation of the conducting layer 42. Accordingly, the side surface of the first insulating film 30 is completely covered with the protection films 32a and 32b. Referring to FIGS. 16B and 16D, the first insulating film 30 can be prevented from being removed when the second insulating film 37 formed below the gate electrode 24 is removed from the second opening 44. Therefore, the first insulating film 30 having a larger width than that of the gate insulating film 22 can be easily formed.
As FIGS. 16B and 16D show, the width T2 of the conducting layer 42 formed at the side of the first insulating film 30 is small. As a result, the conducting layer 42 formed at the side of the first insulating film 30 is likely to be entirely oxidized as shown in FIGS. 17A and 17C. Likewise the second embodiment, this makes it possible to prevent the conducting layer 42 from being left at the side of the first insulating film 30.
While the preferred embodiments of the present invention are described in detail above, the present invention is not limited to those specific embodiments and, within the spirit and scope of the invention as defined in the appended claims, various modifications and alternations may be made.
We claim:

Claims

1. A semiconductor device comprising: a bit line formed to extend inside a semiconductor substrate; a gate electrode formed above the semiconductor substrate between the bit lines; a gate insulating film formed on the semiconductor substrate below a center of the gate electrode; charge storage layers each formed on the semiconductor substrate below the gate electrode to interpose the gate insulating film in a width direction of the bit line; and a first insulating film formed on the semiconductor substrate between the gate electrodes in an extending direction of the bit line, wherein a width of the first insulating film in the width direction of the bit line is larger than a width of the gate insulating film.
2. The semiconductor device according to claim 1, wherein the first insulating film is embedded in a groove formed in the semiconductor substrate between the gate electrodes in the extending direction of the bit line.
3. The semiconductor device according to claim 1, further comprising: a protection film formed on a side surface of the first insulating film, wherein the protection film is formed of a material which is different from a material for forming the gate insulating film and a material for forming the first insulating film.
4. The semiconductor device according to claim 1 , wherein an upper surface of the first insulating film is formed further away from a surface of the semiconductor substrate than an upper surface of the gate insulating film.
5. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulating film on a semiconductor substrate; forming a first opening in the second insulating film by removing the second insulating film formed on the semiconductor substrate in a region other than a region where a bit line and a gate electrode are to be formed; forming a first insulating film in the first opening; forming a conducting layer on the second insulating film; forming second openings by removing the conducting layer and the second insulating layer formed on the semiconductor substrate in a region where the bit line is to be formed, and forming the gate electrode as the conducting layer between the second openings; forming a gate insulating film as the second insulating film below a center of the gate electrode, by removing the second insulating film formed below the gate electrode from the second opening; forming a charge storage layer in a region where the second insulating film formed below the gate electrode has been removed; and forming the bit line defined by each of the second openings in the semiconductor substrate.
6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of: forming a groove in the semiconductor substrate at a lower portion of the first opening, wherein the step of forming the first insulating film includes a step of forming the first insulating film in the groove.
7. The method for manufacturing a semiconductor device according to claim 5, wherein the first insulating film is formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode.
8. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of: forming a protection film on a side surface of the first opening prior to the step of forming the first insulating film, wherein the protection film is formed of a material which is unlikely to be removed compared with the second insulating film when the gate insulating film is formed by removing the second insulating film formed below the gate electrode.
9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of: forming the protection film on an exposed portion of a side surface of the first insulating film prior to the step of forming the conducting layer after performing the step of forming the first insulating film.
10. The method for manufacturing a semiconductor device according to claim 5, wherein: in the step of forming the first opening, the second insulating film is removed using a mask layer formed on the second insulating film to form the first opening; and a step of reducing a width of the mask layer is added prior to the step of forming the first insulating film after performing the step of forming the first opening.
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