WO2009075832A1

WO2009075832A1 - Nonvolatile storage device and control method thereof

Info

Publication number: WO2009075832A1
Application number: PCT/US2008/013532
Authority: WO
Inventors: Masahiro Niimi; Takaaki Furuyama; Kenta Kato
Original assignee: Spansion Llc
Priority date: 2007-12-11
Filing date: 2008-12-09
Publication date: 2009-06-18
Also published as: TW200935440A; TWI508097B; JP2009140605A

Abstract

A nonvolatile storage device and control method are capable of supplying a ground potential to the source terminal of a memory cell while avoiding interference from a global bit line. The storage device has a first local bit line to which a first terminal of a memory cell is coupled; a second local bit line to which a second terminal of the memory cell is coupled; a first selector switch for coupling the first local bit line to a first global bit line; a second selector switch for coupling the second local bit line to a second global bit line; a third selector switch for coupling the first local bit line to a grounding line; and a fourth selector switch for coupling the second local bit line to the grounding line. The first and fourth selector switches or the second and third selector switches become conductive when reading a bit.

Description

NONVOLATILE STORAGE DEVICE AND CONTROL METHOD THEREOF

FIELD OF THE INVENTION

[0001] The invention relates to the application of a bias voltage to a bit line when reading a bit from a memory cell. More particularly, the invention relates to a nonvolatile storage device and a control method thereof wherein a nonvolatile storage device carries out a bias voltage application in accordance with a bit to be read out with the current sensing technique and has multi- value memory cells (hereinafter referred to as "dual bit cells") and a hierarchical bit line architecture.

BACKGROUND OF THE INVENTION

[0002] Koichi, JP-A-2000-306394, discloses a technique wherein a metal wiring line ML3 (main bit line) is connected to a sense amplifier circuit in response to an address signal for selecting a memory cell transistor MO. And, a metal wiring line ML2 (virtual main grounding line) is a ground potential. The drain of the memory cell transistor MO is connected to the metal wiring line ML3 (main bit line) through a MOS transistor BQlO. The source of the memory cell transistor MO is connected to the metal wiring line ML2 (virtual main grounding line) through a MOS transistor BQ 12. [0003] Otani Hidenari et al., JP-A-2003- 157689, is associated with a nonvolatile storage device having a main/sub bit line configuration according to which discharge elements (QDOO to QDkm) discharge sub bit lines (LBOO to LBkm) during the period before and after readout operation performed on a nonvolatile memory cell. Since the drain (sub bit line) of the memory cell is kept at the ground potential, the problem of memory disturbing does not occur. [0004] Omoto Kayoko, JP-A-2005-317110, includes transistors MRl , MR2 of an NMOS configuration according to which a plurality of sub bit lines on the drain side of a memory cell are connected to a common source line. These transistors MRl, MR2 become conductive to discharge the plurality of sub bit lines after completion of a read period. [0005] Other techniques related to the invention have also been disclosed by Toshihiro et al., Junichi et al., and Kaoru et al, as included below.

Nomura Koichi, JP-A-2000-306394 (see Fig. 5)

Otani Hidenari et al., JP-A-2003-157689 (see Fig. 1)

Omoto Kayoko, JP-A-2005-317110 (see Fig. 1) Tanaka Toshihiro et al., JP-A-11-191298

Suzuki Junichi et al., JP-A-2001 -14876

Yamamoto Kaoru et al., JP-A-2003-100092

SUMMARY OF THE INVENTION

A nonvolatile storage device having a memory cell with a plurality of bits in which a bit is read through a hierarchical bit line architecture according to the direction of bias voltage applied. The nonvolatile storage device includes a first local bit line to which a first terminal of the memory cell is to be connected, a second local bit line to which a second terminal of the memory cell is to be connected, a first selector switch which connects the first local bit line with a first global bit line, a second selector switch which connects the second local bit line with a second global bit line, a third selector switch which connects the first local bit line with a grounding line, and a fourth selector switch which connects the second local bit line with the grounding line. In reading out the bit , the first selector switch and the fourth selector switch, or the second selector switch and third selector switch are made conductive and connected to a ground potential while avoiding interference from the first global bit line and the second global bit line, respectively.

A control method of a nonvolatile storage device has a memory cell with a plurality of bits in which a bit is read through a hierarchical bit line architecture according to the direction of bias voltage applied. A global bit line is charged to an initialization potential beforehand. When reading from the memory cell, a first local bit line is connected to a drain terminal of the memory cell as a read target with the global bit line, and a second local bit line is connected to a source terminal of the memory cell as a read target to a grounding line while avoiding interference from a second global bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements. [0007] Fig. 1 is the first circuit diagram showing the current configuration and layout of a nonvolatile storage device of an embodiment of the invention.

[0008] Fig. 2 is a flowchart showing a flow of read out operation of a memory cell.

[0009] Fig. 3 is a timing chart showing the operation of the nonvolatile storage device of an embodiment of the invention. [0010] Fig. 4 is the second circuit diagram showing the current configuration and layout of the nonvolatile storage device of an embodiment of the invention.

[0011] Fig. 5 is the third circuit diagram showing the current configuration and layout of the nonvolatile storage device of an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION Problems that the Invention Intends to Solve

[0012] According to Koichi, when reading a bit from a memory cell, the ground potential is applied to the source terminal of the memory cell by connecting the metal wiring line that constitutes a global bit line (main bit line) to the ground potential. That is, the ground potential is supplied to the source terminal of the memory cell through the global bit line (main bit line) and a local bit line (sub bit line).

[0013] Herein, the wire length of the local bit line (sub bit line) can be restricted, by installing wiring for each of the regions into which the memory cell array is divided. In contrast with this, the global bit line (main bit line) is sometimes installed so as to run through the memory cell array, which results in a very long wiring line. Therefore, the parasitic capacitance and parasitic resistance on the wiring line path of particularly the global bit line (main bit line) are likely to increase.

[0014] During a read period, the global bit line (main bit line) connected to the drain terminal of the memory cell is charged to a specified potential, and the adjacent global bit lines

(main bit lines) may cause potential fluctuation. That is, the voltage fluctuation due to charging/discharging of the global bit line involved in readout operation causes fluctuations in the potential of the global bit line (main bit line) through capacitance coupling. If the parasitic capacitance is large enough, the readout operation performed on the memory cell is adversely affected by the voltage fluctuation.

[0015] In addition, large parasitic capacitance may cause an increase in electric power consumption when the route extending from the global bit line (main bit line) to the local bit line (sub bit line) is discharged to a ground potential.

[0016] Further, large parasitic resistance may lift the voltage level as a result of read current flowing in the route, which leads to the degradation of read sensitivity. f0017] Koichi and Hidenari et al. disclose techniques in which the local bit line (sub bit line) connected to the drain side of the memory cell, while avoiding interference with the global bit line (main bit line) is discharged to the ground potential. However, the discharge elements (QDOO to QDkm) (Hidenari et al.) or the transistors MRl and MR2 (Kayoko) are connected to the drain side of the memory cell and the plurality of local bit lines (sub bit lines) are commonly connected to the ground potential. That is, they are associated with techniques for resetting the drain side of a memory cell after readout operations, but not for connecting a local bit line (sub bit line) to a ground potential, the local bit line being on the source side of a selectively virtually grounded memory cell to which a target memory cell for readout operation is connected. Therefore, they do not disclose any configurations nor control for carrying out such readout operations.

[0018] Suppose a case where all global bit lines are set to the ground potential during an idle period and then, the global bit line connected to the drain terminal of a memory cell is precharged. During this time, the precharge of the global bit line connected to the drain terminal of the memory cell from the ground potential causes coupling noise due to capacitance coupling in the global bit line. The global bit line is connected to the source terminal of the adjacent memory cell and is at the ground potential and causes a lift in the voltage level of the source terminal of the memory cell connected to the global bit line having the ground potential. The lift in the voltage level of the source terminal adversely affects the readout of data from the memory cell through the global bit line. The end result is a delay in the time for sensing the current flowing through the global bit line or an error in the readout operation.

[0019] The invention is directed to overcoming the drawbacks described above. Therefore, a primary object of the invention is to provide a nonvolatile storage device and a control method thereof, wherein when reading a bit on a memory cell, a local bit line (sub bit line) connected to the source terminal of a selectively virtually grounded memory cell is directly selected and connected to a ground potential while avoiding interference from the global bit line (main bit line) corresponding to the local bit line, whereby the ground potential can be supplied to the source terminal of the target memory cell without interference from the global bit line (main bit line).

Means for Solving the Problem [0020] In the nonvolatile storage device of the invention, a bit written in a multi-bit memory cell is read through a hierarchical bit line architecture according to the direction of bias voltage applied. The first and second terminals of each memory cell are connected to first and second local bit lines, respectively. Connection between the first local bit line and the first global bit line, between the second local bit line and the second global bit line, between the first local bit line and a grounding line, and between the second local bit line and the grounding line are established by a first selector switch, a second selector switch, a third selector switch and a fourth selector switch, respectively. Readout of a bit from a memory cell is performed by making the first and fourth selector switches conductive or making the second and third selector switches conductive.

[0021] The nonvolatile storage device control method of the invention is a method for controlling the nonvolatile storage device wherein a bit written in a multi-bit memory cell is read through a hierarchical bit line architecture according to the direction of bias voltage applied. The global bit line is charged to an initialization potential prior to the readout operation. When reading a bit from a memory cell, a first local bit line connected to the drain terminal of the target memory cell is connected to the global bit line. Meanwhile, the other local bit line connected to the source terminal of the target memory cell is connected to a ground potential without interference from the other global bit line. The global bit line corresponding to the other local bit line, i.e., the unselected local bit line is kept at the initialization potential.

[0022] Thereby, a bias voltage is applied across the terminals of the memory cell when reading a bit from the memory cell. The local bit line, to which the drain terminal out of the terminals of the memory cell is connected, is connected to the global bit line and supplied with a positive^' read bias voltage. In this case, it is necessary to apply the ground potential to the terminal that becomes the source terminal. The local bit line, to which the source terminal out of the terminals of the memory cell is connected, is connected to the grounding line without interference from the global bit line and supplied with the ground potential.

Effects of the Invention

[0023] In the nonvolatile storage device and its control method according to the invention, when reading a bit from a multi-bit logic memory cell (i.e., dual bit cell) in accordance with each direction of bias voltage application, the local bit line connected to the source line out of the terminals of the memory cell can be directly connected to the grounding line without interference from the global bit line and then supplied with the ground potential.

[0024] Therefore, there is no need to supply the ground potential to the local bit line through the global bit line when applying the ground potential to the source terminal. This enables it to shorten the route for supplying the ground potential. In addition, there is no need to change the global bit line between a read bias voltage and the ground potential by charging and discharging. Regarding the drain terminal, the read bias voltage is applied to the local bit line connected to the drain terminal through the global bit line.

[0025] Accordingly, the global bit line for biasing the source terminal of the memory cell to the ground potential does not lie next to the global bit line to which the read bias voltage is applied. Therefore, there is no voltage fluctuation due to capacitance coupling between adjacent global bit lines (the capacitance coupling being caused by different bias voltages supplied to adjacent global bit lines). As a result, the bias voltages applied to the source terminal and/or drain terminal of the memory cell when reading a bit do not vary and therefore a stable bias voltage application can be ensured while enabling high-speed reading of the sense amplifier with reduced incidents of malfunction. [0026] In addition, the route for supplying the ground potential can be limited to the local bit line. The global bit line corresponding to the aforesaid other local bit line, which has been charged to the initialization potential for readout operation and then connected to the ground potential, does not need to undergo repetitive charging/discharging afterward and therefore consumes less power compared to the prior art techniques.

[0027] In contrast with the conventional route that extends from the global bit line to the local bit line, the present invention can supply the ground potential to the source terminal by way of a route constituted by a local bit line alone. It is necessary for the current corresponding to a bit to flow through the memory cell when reading the bit from the memory cell. The present invention provides a shortened route from the source terminal to the ground potential (total parasitic resistance is lowered) so that the noise of the voltage applied to the source terminal by the electric current for reading the bit can be reduced. As a result, improved read sensitivity can be achieved.

[0028] By virtue of the face-to-face arrangement of the first and fourth selector switches and the second and third selector switches on the end of the local bit line, the parasitic resistance included in the current pass route at the time of sensing current does not vary whichever of the memory cells located on the local bit line is selected. This enables it to obtain the same access time whichever of the memory cells located on the local bit line is selected.

Best Mode for Carrying out the Invention [0029] Next, referring to Figs. 1 to 5, there will be explained an embodiment of a nonvolatile storage device and a control method thereof according to the present invention.

[0030] Fig. 1 is the first diagram showing the circuit configuration and layout of a nonvolatile storage device 1, which is based on the memory array configuration in Fig. 6 of

Japanese Patent Application No. 2007-097578 (filed on April 3, 2007). Each of the memory cells is a dual bit cell capable of storing multi-bit data. By connecting a bias voltage to one source drain terminal of the memory cell and connecting a ground voltage to the other source drain terminal of the memory cell, it is possible to read out a bit value from the terminal connected to the ground voltage.

[0031] The nonvolatile storage device 1 is provided with memory sectors SCTl to SCTk, a current voltage converter 2 for supplying current, a sense amplifier 3 and a column selector switch (not shown). Here, k represents the maximum number of memory sectors.

[0032] The current voltage converter 2 is connected to first global bit lines GBLZi (i = 1 to m) or second global bit lines GBLXi (i = 1 to m) through a column selector switch selected. Also, the current voltage converter 2 is connected to the memory sectors SCTl to SCTk through the first global bit lines GBLZi (i = 1 to m) or the second global bit lines GBLXi (i = 1 to m). In the current voltage converter 2, when reading out one side (the right side of the gate terminal) from among memory cells MCj i (i = 1 to m, j = 1 to n), to be described later, with the current sensing method, the current of the first global bit line GBLZi is converted to voltage, and when reading the other side (the left side of the gate terminal) with the current sensing method, the current of the second global bit line GBLXi is converted to voltage, so that a sense amplifier input voltage SAIN is outputted. It should to be noted that the first global bit line GBLZl and the second global bit line GBLXl, and a first local bit line LBLZl and a second local bit line LBLXl are bit lines of the virtual grounding method for reading dual bit cells, not complimentary bit lines. In other words, seen from the bit at one side (the right side of the gate terminal), the bit, the first local bit line LBLZl, the second local bit line LBLXl, the first global bit line GBLZl and the second global bit line GBLXl respectively correspond to the memory cell CJ6 (the left side of the gate terminal; (circled number 6 in Fig. 6)), the first local bit line MlJ (6), the second local bit line MlJ (5), the first global bit line M3J (2) and the second global bit line M3J (1) of Japanese Patent Application No.2007-097578 (Fig. 6).

[0033] Here, m represents the maximum number of the memory cells MCj i in a column direction and n represents the maximum number of the memory cells MCj i in a row direction. [0034] In the sense amplifier 3, the sense amplifier input voltage SAIN outputted from the current voltage converter 2 and a reference voltage SAREF outputted from a reference voltage generator (not shown) are compared, so that a sense amplifier output voltage SAOUT is outputted.

The sense amplifiers 3 and the current voltage converters 2 are provided corresponding to the number of column selector switches selected.

[0035] Fig. 1 shows an internal configuration of the memory sector SCT3 from among the memory sectors SCTl to SCTk. The memory sector SCT3 has the memory cell MCji, the first local bit lines LBLZi 20 (i = 1 to m), the second local bit lines LBLXi (i — 1 to m), first selector switches SWIi (i — 1 to m), second selector switches SW2i (i = 1 to m), third selector switches SW3i (i 1 to m), fourth selector switches SW4i (i - 1 to m), a switch control line SELZGBL, a switch control line SELXGNIJ, a switch control line SELZGND, a switch control line SELXGBL and word lines WLj (j = 1 to n).

[0036] In the memory sector SCT3, the memory cells MCji are arranged in an n rows and m columns configuration. Each of the memory cells MCji in the column direction has one source drain terminal connected to the first local bit line LBLZi and the other source drain terminal connected to the second local bit line LBLXi.

[0037] Also, each of the memory cells MCji in the row direction has a gate terminal connected to word lines WLj (j = 1 to n). Each of the word lines WLj is connected to a word line decoder and a word line buffer (not shown). [0038] The first local bit line LBLZi is connected to the first global bit line GBLZI through the first selector switch SWIi and connected to a grounding line VSS through the third selector switch SW3i.

[0039] The second local bit line LBLXi is connected to the second global bit line GBLXi through the second selector switch SW2i and connected to the grounding line VSS through the fourth selector switch SW4i. Ϊ0040] The first selector switch SWIi is made conductive when the switch control line SELZGBL is at a high level and made non-conductive at a low level. The second selector switch SW2i made conductive when the switch control line SELXGBL is at a high level and made non- conductive at a low level. The third selector switch SW3i is made conductive when the switch control line SELZGND is at a high level and made non-conductive at a low level. The fourth selector switch SW4i is made conductive when the switch control line SELXGND is at a high level and made non-conductive at a low level.

[0041] As will be described later, when reading out a bit information at the second local bit line LBLXi side (the right side of the gate terminal) of the memory cell MCj i, the switch control line SELZGBL and the switch control line SELXGND are made high level and the switch control line SELXGBL and the switch control line SELZGND are made low level. As a result, the first selector switch SWIi and the fourth selector switch SW4i are made conductive and the second selector switch SW2i and the third selector switch SW3i are made non-conductive.

[0042] Thus, the first local bit line LBLZi is connected to the first global bit line GBLZi and the second local bit line LBLXi is connected to the grounding line VSS.

[0043] In the meantime, when reading out a bit at the first local bit line LBLZi side (the left side of the gate terminal) of the memory cell MCj i, the switch control line SELXGBL and the switch control line SELZGND are made high level and the switch control line SELZGBL and the switch control line SELXGND are made low level. As a result, the second selector switch SW2i and the third selector switch SW3i are made conductive and the first selector switch SWIj and the fourth selector switch SW4i are made non-conductive.

[0044] Thus, the first local bit line LBLZi is connected to the grounding line VSS, whereas the second local bit line LBLXi is connected to the second global bit line GBLXi.

[0045] In this embodiment, the first local bit line LBLZi or the second local bit line LBLXi is connected to the grounding line VSS by the third selector switch SW3i or the fourth selector switch SW4i when grounded. Since the first selector switch SWIi or the second selector switch SW2i is nonconductive, the first global bit line GBLZi and the second global bit line GBLXi do not transition to the ground voltage. Therefore, noise induced from coupling between the adjacent first global bit line GBLZi and second global bit line GBLXi does not occur. Since noise is not generated in the voltage of the source side, adverse effects upon readout of the first global bit line GBLZi or the second global bit line GBLXi can be avoided and the read operation of the sense amplifier, sensing the current flowing to the first global bit line GBLZi or the second global bit line GBLXi can be speeded up.

[0046] The first local bit line LBLZi or the second local bit line LBLXi is directly connected to the grounding line VSS. Therefore, the parasitic resistance of the source side can be reduced compared to the case where the first global bit line GBLZi or the second global bit line GBLXi is grounded, so that lifting of the voltage of the source terminal of the memory cell MCji can be prevented. This increases the sensitivity and speed of readout by the sense amplifier that senses the first global bit line GBLZi or the second global bit line GBLXi. The reason for this is that the parasitic resistance corresponding to the global bit line of the source side can be reduced.

[0047] As shown in Fig. 4, the first selector switch SWIi and the second selector switch S W2i are located on one end of the first local bit line LBLZi and on one end of the second local bit line LBLXi, respectively. The third selector switch SW3i and the fourth selector switch SW4i are located on the other end (opposite to the previously mentioned one end) of the first local bit line LBLZi and the other end (opposite to the previously mentioned one end) of the second local bit line LBLXi, respectively. Thereby, the total parasitic resistance included in the current path of the first local bit line LBLZi and the second local bit line LBLXi when the memory cell MCI l is selected can be made equal to the total parasitic resistance included in the current path of the first local bit line LBLZi and the second local bit line LBLXi when the memory cell MCnI is selected. Thus, uniform access time can be realized. [0048] As shown in Fig. 5, the first selector switch SWIi and the third selector switch SW3i are located on one end of the first local bit line LBLZi. The second selector switch SW2i and the fourth selector switch SW4i are located on the other end (opposite to the previously mentioned one end) of the second local bit line LBLXi. Thereby, the total parasitic resistance included in the current path of the first local bit line LBLZi and the second local bit line LBLXi when the memory cell MCl 1 is selected can be made equal to the total parasitic resistance included in the current path of the first local bit line LBLZi and the second local bit line LBLXi when the memory cell MCnI is selected. Thus, uniform access time can be attained whichever of the memory cells located on the local bit lines is selected. [0049] Further, neither the first global bit line GBLZi nor the second global bit line

GBLXi is not subjected to charging to the bias voltage and discharging to the ground voltage. The first local bit line LBLZi or the second local bit line LBLXi is subjected to charging to the bias voltage and discharging to the ground voltage. The first global bit line GBLZi and the second global bit line GBLXi have larger wiring capacitance than the first local bit line LBLZi or the second local bit line LBLXi have. Since only either of the first local bit line LBLZi and the second local bit line LBLXi, which have small wiring capacitance, is subjected to charging and discharging to vary it between the bias voltage and the ground voltage, the power consumption can be reduced.

[0050] In this embodiment, the grounding line VSS is located between the memory sectors SCT and connected to the end of the first local bit line LBLZi and the end of the second local bit line LBLXi. This enables it to reduce the resistance caused when grounding the first local bit line LBLZi or the second local bit line LBLXi. The reason for this is that the parasitic resistance of the grounding line itself, composed of wiring lines laid in mesh form within the array, is much lower than the parasitic resistance of the only one global bit line connected to the ground potential as disclosed in the prior art techniques. [0051] In this embodiment, the third selector switch SW3i and the 10 fourth selector switch SW4i are located on the ends of the first local bit line LBLZi and the second local bit line LBLXi, respectively. Similarly, the first selector switch SWIi and the second selector switch SW2i are located on the other ends of these bit lines, respectively. With this arrangement, the first selector switch SWIi and the fourth selector switch SW4i are laid adjacent to each other and the second selector switch SW2i and the third selector switch SW3i are laid adjacent to each other in every adjacent memory sector SCT, which leads to an improvement in the layout efficiency. The reason for this is that these switches are each composed of a high voltage-resistant element capable of withstanding high voltage applied to the drain during programming to avoid element breakage and have substantially the same size so that they establish current path routes in which the same electric current flows in the current sensing method.

[0052] The same effect can be expected by the adjacent arrangement of the first selector switch SWIi and the second selector switch SW2i and the adjacent arrangement of the third selector switch SW3i and the fourth selector switch SW4i as shown in Fig. 4. [0053] The same effect can be expected by the adjacent arrangement of the first selector switch SWIi and the third selector switch SW3i and the adjacent arrangement of the second selector switch SW2i and the fourth selector switch SW4i as shown in Fig. 5.

[0054] In this embodiment, the grounding line VSS connected to the first local bit line

LBLZi and the second local bit line LBLXi is located between the memory sectors SCT, being perpendicular to the first global bit line GBLZi and the second global bit line GBLXi. Therefore, the grounding line VSS disposed between the memory sectors SCT enables low resistance irrespective of the pitches of the bit lines and word lines. In addition, since the layout is made such that the ground line VSS does not pass over the memory cell sectors, the wiring layer of the grounding line

VSS can be wired with the same wiring layer as those of the local word lines, local bit lines and global word lines used in the memory cell sectors. Therefore, in this embodiment, the grounding line VSS within the memory array, which is not required by the conventional virtual grounding technique, can be wired independently from the wiring layer used within the memory cell sectors, and therefore the number of additional wiring layers can be reduced.

[0055] Next, a readout process of the nonvolatile storage device 1 will be described according to the embodiment (Figs. 1, 4, 5). Fig. 2 is a flowchart showing a flow from the power activation of the nonvolatile storage device 1 to the readout of the nonvolatile storage device 1. It should be noted that the precharge prior to each erase, program and readout operation is omitted from the flowchart.

[0056] In Step Si, immediately after power activation or release of the power-down mode, the first global bit line GBLZi and the second global bit line GBLXi are precharged to the initialization potential. During this period, the voltage of the precharge is equal to the read voltage of the memory cell MCji. The first local bit line LBLZi and the second local bit line LBLXi are floating. Thereafter, the program proceeds to Step S2.

[0057] In Step S2, a check is made in response to an access from outside the nonvolatile storage device 1 to determine whether a readout operation is to be performed on the memory cell

MCji. If a readout operation is to be performed on the memory cell MCji, the program proceeds to

Step S3. If a readout operation is not to be performed on the memory cell MCji, the program returns to Step S2. Step S2 is equivalent to an active command or read command.

[0058] In Step S3, the first local bit line LBLZi or second local bit line LBLXi to which the drain terminal of the memory cell MCji is to be connected by address selection (or the like), is connected to the first global bit line GBLZi or the second global bit line GBLXi. Then, the program proceeds to Step S4.

[0059] In Step S4, the first local bit line LBLZi or second local bit line LBLXi to which the source terminal of the memory cell MCji is to be connected by address selection (or the like), is connected to the grounding line (VSS within the memory array). Then, the program proceeds to Step S5.

[0060] In Step S5, readout is performed on the memory cell MCji. At that time, the word line WLj selected by the address (or the like) is at a high level. Then, the program proceeds to Step S6.

[0061] In Step S6, the first local bit line LBLZi or second local bit line LBLXi to which the drain terminal of the memory cell MCji is connected is disconnected from the first global bit line GBLZi or the second global bit line GBLXi. Then, the program proceeds to Step S7.

[0062] In Step S7, the first local bit line LBLZi or second local bit line LBLXi to which the source terminal of the memory cell MCji is connected is disconnected from the grounding line. Then, the program returns to Step S2.

[0063] Although the flowchart of Fig. 2 shows a time-series control process in which a shift is made from Step S3 to Step S4, a shift from Step S4 to Step S3 may be made or, alternatively, Step S3 and Step S4 may be executed at the same time in the actual control process. Likewise, although a shift from Step S6 to Step S7 is made in the time-series control process shown in the flowchart of Fig. 2, a shift from Step S7 to S6 or simultaneous execution of Step S6 and Step S7 are possible in the actual control process. Further, Step S5 may be executed simultaneously with Step S3 and/or Step S4.

[0064] In Step S 1 , the nonvolatile storage device 1 of this embodiment charges the first global bit line GBLZi and the second global bit line GBLXi to the initialization potential beforehand. The operation for reading data from the memory cell MCji includes: Step S3 for connecting the first local bit line LBLZi or the second local bit line LBLXi, to which the drain terminal of the target memory cell MCji is connected, to the first global bit line GBLZi or the second global bit line GBLXi; Step S4 for connecting the first local bit line LBLZi or the second local bit line LBLXi, to which the source terminal of the target memory cell MCji is connected, to the grounding line VSS; and Step S 5 for activating the word line WLj.

[0065] When reading a bit from the memory cell MCji, a bias voltage is applied across the terminals of the memory cell MCji. The first local bit line LBLZi or the second local bit line LBLXi, to which the terminal that becomes the drain terminal of the target memory cell MCji is connected, is connected to the first global bit line GBLZi or the second global bit line GBLXi and subjected to positive voltage bias application. In this case, the ground potential should be applied to the terminal that becomes the source terminal. Therefore, the first local bit line LBLZi or the second local bit line LBLXi, to which the terminal that becomes the source terminal of the memory cell MCji is connected to the grounding line VSS and supplied with the ground potential.

[0066] According to the control method of the nonvolatile storage device 1 of this embodiment, when reading a bit from the memory cell MCji (i.e., dual bit cell) in accordance with the application direction of a bias voltage, the first local bit line LBLZi or the second local bit line LBLXi, to which the terminal that becomes the source terminal out of the terminals of the memory cell MCji is connected, can be directly connected to the grounding line VSS and supplied with the ground potential without interference from the first global bit line GBLZi or the second global bit line GBLXi.

[0067] Accordingly, it is no longer necessary to supply the ground potential to the first local bit line LBLZi or the second local bit line LBLXi through the first global bit line GBLZi or the second global bit line GBLXi, when applying the ground potential to the source terminal. This makes it possible to shorten the supply route for the ground potential. In addition, there is no need to charge and discharge the first global bit line GBLZi or the second global bit line GBLXi to vary it between the read bias voltage and the ground potential. Regarding the drain terminal, a read bias voltage is applied to the first local bit line LBLZi or second local bit line LBLXi, to which the drain terminal is connected, through the first global bit line GBLZi or the second global bit line GBLXi. [0068] Unlike the prior art techniques, the second global bit line GBLXi and the first global bit line GBLZi, which bias the source terminal of the memory cell MCj i to the ground potential, are not laid adjacent to the first global bit line GBLZi or the second global bit line GBLXi to which the read bias voltage is applied. Therefore, there occurs no voltage fluctuation due to capacitance coupling etc. between the first global bit line GBLZi and the second global bit line GBLXi. Capacitance coupling occurs in cases where different bias voltages are supplied to adjacently laid first and second global bit lines GBLZi, GBLXi. The bias voltages, applied to the source terminal and drain terminal of the memory cell MCj i during readout of a bit, do not fluctuate so that stable bias voltage application can be ensured. [0069] The route through which the ground potential is supplied may only be the first local bit line LBLZi or the second local bit line LBLXi. Not only owing to the first global bit lines GBLZi and the second global bit lines GBLXi which have been charged to the initialization potential, but also owing to the fact that it is unnecessary to charge and discharge the global bit line corresponding to the local bit line to which the source terminal of the memory cell is connected, lower power consumption as compared to the prior art techniques can be achieved.

[0070] In contrast with the conventional route from the global bit line to the local bit line, the embodiment of the invention makes it possible to supply the ground potential, having low parasitic resistance and laid in mesh form within the array, to the source terminal through the route composed of the first local bit line LBLZi or the second local bit line LBLXi alone. It is necessary for the current corresponding to a bit to flow through the memory cell when reading the bit from the memory cell. MCj i. In the present embodiment, a lift in the applied voltage to the source terminal caused by the bit read current can be restricted because the route from the source terminal to the ground potential is shortened. As a result, improved read sensitivity can be achieved.

[0071] Next, the readout operation of the nonvolatile storage device 1 will be described. Fig. 3 is a timing chart showing the operation of the nonvolatile storage device 1. iO072] Immediately after power activation or release of the power-down mode, a precharge voltage Vpre, which is the read bias voltage, is applied to the first global bit lines GBLZl to GBLZm, GBLXl to GBLXm.

[0073] The phases (1) to (8) of Fig. 3 are associated with the operation for reading data from the right side of the gate terminal of the memory cell. In phase (1) after completion of a read judgment, the switch control line SELZGBL, that controls the first selector switch SWIi connected between the first global bit line GBLZi and the first local bit line LBLZi, goes to a high level so that the first selector switch SWIi becomes conductive to apply the precharge voltage Vpre to the first local bit line LBLZi. Note that phase (1) may be omitted (in this case, the first selector switch SWIi remains non. conductive).

[0074] In phase (2), the switch control line SELXGBL, that controls the second selector switch SW2i connected between the second global bit line GBLXi and the second local bit line

LBLXi, goes to a high level so that the second selector switch SW2i becomes conductive to apply the precharge voltage Vpre to the second local bit line LBLXZi. Note that phase (2) may be omitted (in this case, the second selector switch SW2i remains non-conductive).

[0075] In phase (3), the first selector switch SWIi becomes conductive because of the transition of the switch control line SELZGBL to a high level, and the first global bit line GBLZi and the first local bit line LBLZi are connected. The second global bit line GBLXi comes into a floating state, so that it keeps the precharge voltage Vpre, by parasitic capacitance or it is kept at the potential equal to the precharge voltage Vpre by a bit line driver (not shown) provided in the current voltage converter 2.

[0076] In phase (4), the switch control line SELXGND that controls the fourth selector switch SW4i, connected between the second global bit line GBLXi and the grounding line VSS, goes to a high level so that the fourth selector switch SW4i becomes conductive to connect the second local bit line LBLXi to the ground voltage. £θO77] In phase (5), the global bit line GBLZl is set as a read bit line and the word line WLl goes to a high level. The first local bit line LBLZl side of the memory cell MCI l is supplied with the precharge voltage Vpre, becoming a drain terminal, whereas the second local bit line LBLXl side is supplied with the ground voltage, becoming a source terminal. Thereby, the bit stored on the source side of the memory cell MC 11, that is, the second local bit line LBLXl side is read out. This bit is data in an erase state, that is, data having value "1".

[0078] In phase (6), a voltage lower than a reference voltage SAREF is output to the sense amplifier input voltage SAIN so that a sense amplifier output voltage SAOUT of the sense amplifier 3 outputs a low level indicative of erase information. [0079] In phase (7), the word line WLl goes to a low level, so that no current flows in the target memory cell MCI l and therefore the voltage of the sense amplifier input voltage SAIN exceeds the reference voltage SAREF.

[0080] In phase (8), since the voltage exceeding the reference voltage SAREF is output to the sense amplifier input voltage SAIN, the sense amplifier output voltage SAOUT of the sense amplifier 3 is at a high level.

[0081] The phases (9) to (14) are associated with the operation for reading a bit from the left side of the gate terminal of the memory cell. In phase (9) after completion of a read judgment, the precharge voltage Vpre, which is the read bias voltage, is applied to the first global bit line GBLZi. Concurrently, the switch control line SELZGBL, that controls the first selector switch SWIi, connected between the first global bit line GBLZi and the first local bit line LBLZi, goes to a high level so that the first selector switch SWIi becomes conductive to apply the precharge voltage Vpre to the first local bit line LBLZi. Note that phase (1) may be omitted (In this case, the first selector switch SWIi remains non-conductive).

[0082] In phase (10), the precharge voltage Vpre, which is the read bias voltage, is applied to the second global bit line GBLXi. Concurrently, the switch control line SELXGBL, that controls the second selector switch SW2i, connected between the second global bit line GBLXi and the second local bit line LBLXi, goes to a high level so that the second selector switch SW2i becomes conductive to apply the precharge voltage Vpre to the second local bit line LBLXZi. Note that phase (2) may be omitted (In this case, the second selector switch SW2i remains non- conductive).

[0083] In phase (11), the second selector switch SW2i becomes conductive because of the transition of the switch control line SELXGBL to a high level, and the second global bit line GBLXi and the second local bit line LBLXi are connected. The first global bit line GBLZi comes into a floating state so that it keeps the precharge voltage Vpre by parasitic capacitance, or it is kept at the potential equal to the precharge voltage Vpre by the bit line driver (not shown) provided in the current voltage converter 2.

[0084] In phase (12), the switch control line SELZGND, that controls the third selector switch SW3i, connected between the first global bit line GBLZi and the grounding line VSS, goes to a high level so that the third selector switch SW3i becomes conductive to connect the first local bit line LBLZi to the ground voltage.

[0085] In phase (13), the second global bit line GBLXl is set as a read bit line and the word line WL2 goes to a high level. The second local bit line LBLXl side of the memory cell MC21 is supplied with the precharge voltage Vpre, becoming a drain terminal, whereas the first local bit line LBLZl side is supplied with the ground voltage, becoming a source terminal. Thereby, the data stored on the source side of the memory cell MC21, that is, the first local bit line LBLZl side is read out. This data is data in a program state, that is, data having value "0".

[0086] In phase (14), a voltage exceeding the reference voltage SAREF is output to the sense amplifier input voltage SAIN so that the sense amplifier output voltage SAOUT of the sense amplifier 3 outputs a high level indicative of program information. [0087] According to the control method of the nonvolatile storage device 1 of this embodiment, the first local bit line LBLZi or second local bit line LBLXi, which is connected to the first global bit line GBLZi or the second global bit line GBLXi, is supplied with the precharge voltage Vpre during readout operation. Thereby, the bias voltage can be applied to the drain terminal of the memory cell MCj i and the contents of the memory cell MCj i read out without fail.

[0088] According to the control method of the nonvolatile storage device 1 of this embodiment, in cases where the first local bit line LBLZi whose column address has been selected is used for readout, other first global bit lines and second global bit lines which are not connected to the first local bit lines LBLZi whose column addresses have not been selected are maintained at the same potential as the precharge voltage Vpre during the readout operation. On the other hand, in cases where the second local bit line LBLXi whose column address has been selected is used for readout, other first global bit lines and second global bit lines which are not connected to the second local bit lines LBLXi whose column addresses have not been selected, are maintained at the same potential as the precharge voltage Vpre during the readout operation. This prevents the adverse effect of possible capacitance coupling occurring between adjacent first and second global bit lines GBLZi, GBLXi.

[0089] According to the control method of the nonvolatile storage device 1 of this embodiment, the initialization potential is the precharge voltage Vpre having the same potential as the read bias voltage. Therefore, it can be the precharge voltage Vpre during readout operation and precharge operation, so that the potential fluctuation of the first global bit line GBLZi and the second global bit line GBLXi can be prevented.

[0090] According to the control method of the nonvolatile storage device 1 of this embodiment, in cases where the first local bit line LBLZi whose column address has been selected is used for readout, other first global bit lines and second global bit lines which are not connected to the first local bit lines LBLZi whose column addresses have not been selected are kept in a floating state during the readout operation. On the other hand, in cases where the second local bit line LBLXi whose column address has been selected is used for readout, other first global bit lines and second global bit lines which are not connected to the second local bit lines LBLXi whose column addresses have not been selected are kept in a floating state during the readout operation. Because of this arrangement, the unselected first global bit lines and unselected second global bit lines are not actuated and therefore the power consumption of the bit line driver (not shown) provided in the current voltage converter 2 can be restricted.

[0091] Next, the circuit configuration and layout of the nonvolatile storage device will be described in detail with reference to the third circuit diagram (Fig. 5) of the drawings. In the following description, the primary points of difference between an embodiment of the invention and the first and second circuit diagrams will be explained.

[0092] The nonvolatile storage device 1 has the first global bit line GBLZl and the second global bit line GBLXl ; a plurality of local bit lines LBLl to LBLk; a first selector switch SWIk and second selector switch SW2k connected between the first global bit line GBLZl, the second global bit line GBLXl and the local bit lines LBLl to LBLk; VSS arranged in mesh form between the memory sectors; a third selector switch SW3k and fourth selector switch SW4k connected between the local bit lines LBLl to LBLk and VSS; and a plurality of dual bit cells.

[0093] The plurality of memory cells, which are duel bit cells, are connected to one another by a common word line and connected to the local bit lines LBLl to LBLk, respectively, with the virtual grounding method. Odd-numbered local bit lines LBLl, LBL3, LBL5 etc., are connected to the first global bit line GBLZl through the first selector switch SWIk and to VSS through the third selector switch SW3k. Even-numbered local bit lines LBL2, LBL4, LBL6 etc., are connected to the second global bit line GBLXl through the second selector switch SW2k and to VSS through the fourth selector switch SW4k. The first selector switch SWIk and the third selector switch SW3k are located at one end of each of the odd-numbered local bit lines LBLl, LBL3, LBL5 etc'. The second selector switch SW2k and the fourth selector switch SW4k are located at the other end of each of the even-numbered local bit lines LBL2, LBL4, LBL6 etc., the other end being located on the side opposite to the previously mentioned one end. Input to the first selector switch SWIk and the second selector switch SW2k are control signals SELGBLl to SELGBL8 into which memory sector selection information, selection information on the memory cells aligned in the column direction, and column address information as to which side of a duel bit cell is to be selected are encoded. Input to the third selector switch SW3k and the fourth selector switch SW4k are control signals SELGND 1 to SELGND8 into which memory sector selection information, selection information on the memory cells aligned in the column direction, and column address information as to which side of a duel bit cell is to be selected are combined.

[0094] When reading a bit from the other side (i.e., the left side of the gate terminal indicated by hatching lines that extend diagonally down to the left) of the memory cell MC 1.1 with the current sensing method, connection to the second global bit line GBLXi is established through the second selector switch SW21 that has been made conductive by the control signal SELGBL2 having a high level. Also, connection to VSS is established through the third selector switch SW31 that has been made conductive by the control signal SELGND2 having a high level. When reading a bit from one side (i.e., the right side of the gate terminal indicated by hatching lines that extend diagonally down to the right) of the memory cell MC 12 with the current sensing method, connection to the second global bit line GBLXi is established through the second selector switch SW21 that has been made conductive by the control signal SELGB L2 having a high level. Also, connection to VSS is established through the third selector switch SW32 that has been made conductive by the control signal SELGND4 having a high level. When reading a bit from the other side (i.e., the left side of the gate terminal indicated by hatching lines that extend diagonally down to the left) of the memory cell MC 15 with the current sensing method, connection to the second global bit line GBLXi is established through the second selector switch SW23 that has been made conductive by the control signal SELGBL6 having a high level. Also, connection to VSS is established through the third selector switch SW33 that has been made conductive by the control signal SELGND6 having a high level. When reading a bit from one side (i.e., the right side of the gate terminal indicated by hatching lines that extend diagonally down to the right) of the memory cell MC 15 with the current sensing method, connection to the first global bit line GBLZl is established through the first selector switch SWl 3 that has been made conductive by the control signal SELGBL5 having a high level. Also, connection to VSS is established through the third selector switch SW43 that has been made conductive by the control signal SELGND5 having a high level. It should be noted that when reading a bit from the other side (i.e., the left side of the gate terminal indicated by hatching lines that extend diagonally down to the left) of the memory cell MCl 1 with the current sensing method, the same precharge voltage Vpre (i.e., read bias voltage) as of the selected local bit line LBL2 is applied to the local bit lines LBL3, LB L4 from the global bit line (not shown) so that that the potential of LB L4 is not affected by the storage condition of the memory cells located on the right of MCl 1. The subsequent local bit line LBL5 is in a floating state. The configuration shown in the third circuit diagram has the same effect as of the configurations of the first and second circuit diagrams.

[0095] It is apparent that the invention is not necessarily limited to the particular embodiment shown herein and various changes and modifications are made to the disclosed embodiment without departing from the spirit and scope of the invention. For instance, in the foregoing embodiment, the application of the read bias voltage to a global bit line is performed just after power activation or release of the power-down mode or during a precharge period (i.e., during phases (9) and (10) in Fig. 3). However, after completion of initialization at the time of power activation, the application of the read bias voltage to a global bit line may be performed according to need. That is, the application may be executed in accordance with readout operation. For instance, it may be executed after readout operation (i.e., during phase (7) in Fig. 3 or during Steps S6 and S7). fθO96] In the foregoing embodiment, the application of the read bias voltage to a local bit line (phases (1), (2); (9), and (10) in Fig. 3) may be included in Steps S3 and S4. In Fig. 5, it can be realized by inactivating the first/second selector switches corresponding to the third/fourth selector switches of the local bit line to be connected to VSS. This leads to improved access time reduction. In addition, the invention is applicable to quad bit cells having multi-value function on the right and left sides of the gate terminal respectively.

Claims

WHAT IS CLAIMED IS:

1. A nonvolatile storage device having a memory cell with a plurality of bits wherein a bit is read through a hierarchical bit line architecture according to a polarity of a bias voltage applied, the nonvolatile storage device comprising: a first local bit line to which a first terminal of the memory cell is to be coupled; a second local bit line to which a second terminal of the memory cell is to be coupled; a first selector switch which couples the first local bit line with a first global bit line; a second selector switch which couples the second local bit line with a second global bit line; a third selector switch which couples the first local bit line with a grounding line; and a fourth selector switch which couples the second local bit line with the grounding line, wherein, in reading out a bit, the first selector switch and the fourth selector switch, or the second selector switch and third selector switch are made conductive and connected to a ground potential while avoiding interference from the first global bit line and the second global bit line, respectively.

2. The nonvolatile storage device according to claim 1, wherein the grounding line is located in accordance with the first local bit line and the second local bit line, respectively.

3. The nonvolatile storage device according to at least any one of claims 1 and 2, wherein the third selector switch and the fourth selector switch are located on an end of the first local bit line and the second local bit line, respectively.

4. The nonvolatile storage device according to at least any one of claims 1 and 2, wherein the first selector switch and the third selector switch are located on an end of the first local bit line, and the second selector switch and the fourth selector switch are located on an end of the second local bit line.

5. The nonvolatile storage device according to at least any one of claims 3 and 4, wherein the end of the first local bit line and the end of the second local bit line are located opposite to each other.

6. The nonvolatile storage device according to at least any one of claims 1 to 5, wherein the grounding line is located perpendicular to the first global bit line and the second global bit line.

7. A control method of a nonvolatile storage device having a memory cell with a plurality of bits which is read through a hierarchical bit line architecture according to a polarity of a bias voltage applied, comprising the steps of: charging a global bit line to an initialization potential beforehand; and reading out from the memory cell, wherein the step of reading out comprises the steps of: coupling a first local bit line which is coupled to a drain terminal of the memory cell as a read target with the global bit line; and coupling a second local bit line which is coupled to a source terminal of the memory cell as a read target to a grounding line while avoiding interference from a second global bit line.

8. The control method of the nonvolatile storage device according to claim 7, wherein the global bit line which is coupled to the first local bit line is maintained at a readout bias voltage during readout operation.

9. The control method of the nonvolatile storage device according to claim 8, wherein the second global bit line, which is not coupled to the first local bit line, is maintained at the same potential as the readout bias voltage during readout operation.

10. The control method of the nonvolatile storage device according to at least any one of claims 7 and 8, wherein the second global bit line which is not coupled to the first local bit line is brought into a floating state in the readout operation.

11. The control method of the nonvolatile memory device according to at least any one of claims 8 to 10, wherein the initialization potential is the same voltage as the readout bias voltage.