WO2009079517A3 - Methods for isolating portions of a loop of pitch-multiplied material and related structures - Google Patents
Methods for isolating portions of a loop of pitch-multiplied material and related structures Download PDFInfo
- Publication number
- WO2009079517A3 WO2009079517A3 PCT/US2008/087029 US2008087029W WO2009079517A3 WO 2009079517 A3 WO2009079517 A3 WO 2009079517A3 US 2008087029 W US2008087029 W US 2008087029W WO 2009079517 A3 WO2009079517 A3 WO 2009079517A3
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- Prior art keywords
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- 239000000463 material Substances 0.000 title abstract 6
- 125000006850 spacer group Chemical group 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 3
- 230000000873 masking effect Effects 0.000 abstract 2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/528—Geometry or layout of the interconnection structure
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08861157.9A EP2232539B1 (en) | 2007-12-18 | 2008-12-16 | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
CN200880121431.6A CN101903991B (en) | 2007-12-18 | 2008-12-16 | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
JP2010539709A JP5561485B2 (en) | 2007-12-18 | 2008-12-16 | Method and related structure for isolating a portion of a pitch-multiplied material loop |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/959,409 | 2007-12-18 | ||
US11/959,409 US7790531B2 (en) | 2007-12-18 | 2007-12-18 | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009079517A2 WO2009079517A2 (en) | 2009-06-25 |
WO2009079517A3 true WO2009079517A3 (en) | 2009-10-01 |
Family
ID=40752074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2008/087029 WO2009079517A2 (en) | 2007-12-18 | 2008-12-16 | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
Country Status (7)
Country | Link |
---|---|
US (6) | US7790531B2 (en) |
EP (1) | EP2232539B1 (en) |
JP (3) | JP5561485B2 (en) |
KR (1) | KR101603800B1 (en) |
CN (2) | CN101903991B (en) |
TW (1) | TWI503924B (en) |
WO (1) | WO2009079517A2 (en) |
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US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
JP2009295785A (en) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | Method of manufacturing semiconductor device |
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JP5665289B2 (en) | 2008-10-29 | 2015-02-04 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus |
KR101045090B1 (en) * | 2008-11-13 | 2011-06-29 | 주식회사 하이닉스반도체 | Method for forming micro-pattern of semiconductor device |
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US9324619B2 (en) * | 2014-08-25 | 2016-04-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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US9882028B2 (en) * | 2016-06-29 | 2018-01-30 | International Business Machines Corporation | Pitch split patterning for semiconductor devices |
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US20180211868A1 (en) | 2018-07-26 |
US9941155B2 (en) | 2018-04-10 |
US20170250110A1 (en) | 2017-08-31 |
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US8932960B2 (en) | 2015-01-13 |
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US10497611B2 (en) | 2019-12-03 |
US20130171784A1 (en) | 2013-07-04 |
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US7790531B2 (en) | 2010-09-07 |
US20100289070A1 (en) | 2010-11-18 |
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EP2232539B1 (en) | 2016-02-17 |
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US20090152645A1 (en) | 2009-06-18 |
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