WO2009090812A1 - Power supply circuit and method for controlling the same - Google Patents
Power supply circuit and method for controlling the same Download PDFInfo
- Publication number
- WO2009090812A1 WO2009090812A1 PCT/JP2008/072597 JP2008072597W WO2009090812A1 WO 2009090812 A1 WO2009090812 A1 WO 2009090812A1 JP 2008072597 W JP2008072597 W JP 2008072597W WO 2009090812 A1 WO2009090812 A1 WO 2009090812A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- output
- transistor
- charge pump
- circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
Definitions
- the present invention relates to a power supply circuit configured to supply power to a load for stably driving the load and to a method for controlling an operation of the power supply circuit.
- a DC-DC converter using an inductor has been conventionally used as a power supply circuit.
- DC-DC converters have been used for many applications since a voltage at a desired level can be generated and power can be efficiently supplied to a load which consumes a large amount of current.
- components such as a transformer and a coil are required. Therefore, it has been impossible to include all components of the DC-DC converter in a semiconductor integrated circuit
- a charge pump circuit has been sometimes used as a power supply circuit since the charge pump circuit can be downsized and is capable of high efficiencies.
- the charge pump circuit raises an output voltage by adding a voltage of a capacitor charged by a voltage of a DC power source, the output voltage of the charge pump circuit is largely dependent on the power source voltage. Further, when a battery is used as the DC power source, the output voltage of the charge pump circuit decreases in accordance with a drop of a battery voltage, by a voltage level obtained by multiplying the drop in the battery voltage with a raising ratio of the voltage. As a result, the output voltage of the charge pump circuit rapidly decreases.
- a power source voltage VCC is controlled to be a constant voltage by a voltage regulator 101 and inputted to a charge pump circuit 102 to be raised. The raised voltage is then supplied to a load 110 (for example, see Patent Document 1) .
- a second method as shown in FIG. 6, an input power source voltage VCC is inputted to the charge pump circuit 102 to be raised. The raised voltage is then inputted to the voltage regulator 101 and controlled as a constant voltage, and supplied to the load 110.
- a third method as shown in FIG.
- each on-period of a transistor MlOl which connects a flyback capacitor Cl in the charge pump circuit and a catch-back capacitor Cout provided outside the charge pump circuit, is forcibly shortened to obtain a constant output voltage.
- Patent Document 1 Japanese Patent Application Publication No. 2006-320158
- An output voltage can be stabilized with stable ripple amplitude by the first and second methods.
- a voltage regulator which has a large output driver through which a maximum output current of the charge pump circuit can flow. Therefore, there is a problem in that chip size is increased.
- a constant voltage can be stably outputted by only monitoring an output voltage of the charge pump circuit and when the output voltage of the charge pump circuit becomes a predetermined level or higher, feeding back a detected signal to a clock unit which controls ON/OFF of the charge pump circuit.
- a clock unit which controls ON/OFF of the charge pump circuit.
- the present invention has been made in view of the above problems and it is an object of at least one embodiment of the present invention to provide a power supply circuit which can output a constant voltage required for stably driving a load regardless of a variation of a power source voltage, by optimally controlling a gate voltage of a transistor included in a charge pump circuit, and to provide a method for controlling an operation of the power supply circuit.
- a power supply circuit includes a charge pump circuit configured to raise a voltage inputted from an input terminal and supply the raised voltage from an output terminal to a given load and a control circuit unit.
- the charge pump circuit includes a fly-back capacitor configured to store a charge of the voltage inputted from the input terminal and an output transistor connected between one terminal of the fly-back capacitor and the output terminal of the charge pump circuit.
- the control circuit unit receives a reference voltage and the voltage outputted from the charge pump circuit and is configured to generate a proportional voltage proportional to the voltage outputted from the charge pump circuit and output a voltage to control the output transistor depending on a difference between the proportional voltage and the reference voltage so that the proportional voltage has the same voltage level as the reference voltage.
- a method for controlling an operation of a power supply circuit including a charge pump circuit configured to raise a voltage inputted from an input terminal and supply the raised voltage from an output terminal to a given load.
- the charge pump circuit includes a fly-back capacitor configured to store a charge of the voltage inputted from the input terminal and a transistor connected between one terminal of the fly-back capacitor and the output terminal of the charge pump circuit.
- the method includes steps of controlling the transistor so that a voltage proportional to the raised voltage becomes the same level as a reference voltage and keeping the raised voltage constant based on said controlling of the transistor for provision to the load.
- FIG. 1 is a diagram showing an example of a power supply circuit and an example of clock signals of a first embodiment of the present invention.
- FIG. 2 is a timing chart showing an example of a relationship between an output signal AMPOUT and an output voltage Vout of the power supply circuit shown in FIG. 1.
- FIG. 3 is a diagram showing another example of a power supply circuit and an example of clock signals of the first embodiment of the present invention.
- FIG. 4 is a timing chart showing an example of a relationship between an output signal AMPOUT and an output voltage Vout of the power supply circuit shown in FIG. 3.
- FIG. 5 is a diagram showing an example of a conventional power supply circuit.
- FIG. 6 is a diagram showing another example of a conventional power supply circuit.
- FIG. 7 is 'a timing chart showing an example of a relationship between an operation of a transistor MlOl and an output voltage Vout in a conventional power supply circuit.
- FIG. 1 is a diagram showing an example of a power supply circuit of a first embodiment of the present invention.
- a power source voltage VCC inputted to an input terminal IN is raised and a predetermined constant voltage is generated.
- the generated constant voltage is outputted as an output voltage Vout from an output terminal OUT to a load 10. In this manner, power is supplied to the load 10.
- the power supply circuit 1 includes a charge pump circuit 2; a reference voltage generating circuit 3 capable of generating and outputting a predetermined reference voltage Vref; resistors Rl and R2 for detecting an output voltage, which are capable of dividing the output voltage Vout and generating and outputting a divided voltage Vfb; an error amplifier circuit 4, and a catch-back capacitor Cout .
- the charge pump circuit 2 includes PMOS transistors Ml through M3, an NMOS transistor M4, and a flyback capacitor Cl.
- the error amplifier circuit 4 includes an operational amplifier circuit 11, a constant current source 12, and an NMOS transistor Mil.
- the PMOS transistor M3 serves as an output transistor
- the resistors Rl and R2 serve as a proportional voltage generating circuit unit
- the error amplifier circuit 4 serves as an error amplifier circuit unit
- the NMOS transistor Mil serves as a first transistor
- the constant current source 12 and the NMOS transistor Mil serve as an output circuit.
- FIG. 1 shows an example in which the PMOS transistors Ml through M3, the NMOS transistor M4, the reference voltage generating circuit 3, the error amplifier circuit 4, and the resistors Rl and R2 are integrated in one IC.
- the IC includes the input terminal IN, an output terminal OUT, and connecting terminals ClP and ClM.
- the PMOS transistor Ml is connected between the input terminal IN and the connecting terminal ClP.
- the PMOS transistor M2 is connected between the input terminal IN and the connecting terminal ClM.
- the flyback capacitor Cl is connected between the connecting terminals ClP and ClM.
- the PMOS transistor M3 is connected between the connecting terminal ClP and the output terminal OUT.
- the NMOS transistor M4 is connected between the connecting terminal ClM and ground potential.
- the catch-back capacitor Cout is connected between the output terminal OUT and ground potential.
- the resistors Rl and R2 are connected in series between the output terminal OUT and ground potential.
- the divided voltage Vfb is outputted from a connection between the resistors Rl and R2 and inputted to an inverting input terminal of the operational amplifier circuit 11.
- the reference voltage Vref is inputted to a non-inverting input terminal of the operational amplifier circuit 11.
- An output terminal of the operational amplifier circuit 11 is connected to a gate of the NMOS transistor Mil.
- the constant current source 12 and the NMOS transistor Mil are connected in series between the power source voltage VCC and ground potential.
- a connection between the constant current source 12 and the NMOS transistor Mil, which serves as an output terminal of the error amplifier circuit 4 is connected to a gate of the PMOS transistor M3.
- a clock signal ⁇ l, a clock signal ⁇ 2, and an inverted signal ⁇ lB which is an inverted clock signal ⁇ l are inputted to a gate of the PMOS transistor Ml, a gate of the PMOS transistor M2, and a gate of the NMOS transistor M4 , respectively.
- the clock signals ⁇ l and ⁇ 2 are expressed by rectangular waveforms with timings as shown in a lower diagram of FIG. 1.
- the PMOS transistors Ml, M2, and the NMOS transistor M4 are turned ON/OFF in accordance with the clock signals ⁇ l and ⁇ 2.
- the error amplifier circuit 4 controls an operation of the PMOS transistor M3 so that the divided voltage Vfb has the same level as the reference voltage Vref. In this manner, the error amplifier circuit 4 controls on-resistance of the PMOS transistor M3 so that the output voltage Vout becomes constant at a predetermined level.
- FIG. 2 is a timing chart showing an example of a relationship between an output signal AMPOUT of the error amplifier circuit 4, which is inputted to the gate of the PMOS transistor M3, and the output voltage Vout.
- the operation of the power supply circuit 1 shown in FIG. 1 is described in more detail with reference to FIG. 2.
- the clock signal ⁇ l is at a low level, -li ⁇
- the PMOS transistor Ml and the NMOS transistor M4 are turned on and become conductive. Since the clock signal ⁇ 2 is at a high level at this time, the PMOS transistor M2 is turned off and becomes non- conductive. In this case, the output voltage Vout is higher than a set voltage as shown in FIG. 2. Therefore, the operational amplifier circuit 11 turns off the NMOS transistor Mil to be non-conductive in order to drop the output voltage Vout to the set voltage. Thus, the output signal AMPOUT of the error amplifier circuit 4 has a voltage capable of turning off the PMOS transistor M3 to be non-conductive. In view of these, the flyback capacitor Cl is charged by the power source voltage VCC.
- the operational amplifier circuit 11 turns on the NMOS transistor Mil and controls on-resistance of the NMOS transistor Mil in order to raise the output voltage Vout to the set voltage.
- the output signal AMPOUT of the error amplifier circuit 4 has a voltage capable of turning on the PMOS transistor M3.
- the error amplifier circuit 4 controls a gate voltage of the PMOS transistor M3 and controls on-resistance of the PMOS transistor M3 so that the output voltage Vout becomes a predetermined voltage .
- the gate voltage of the PMOS transistor M3 is controlled and the on-resistance of the PMOS transistor M3 is optimized. In this manner, the output voltage Vout can be stabilized without making a ripple amplitude of the output voltage Vout larger.
- FIG. 3 is a diagram showing another example of a power supply circuit of the first embodiment of the invention.
- components that are the same or similar to those in FIG. 1 are denoted by the same reference numerals and their descriptions are omitted here. Only the differences between FIGS. 1 and 3 are described below.
- FIG. 3 is different from FIG. 1 in that an NMOS transistor M12 and a PMOS transistor M13 are additionally provided.
- the NMOS transistor M12 serves as a second transistor and the PMOS transistor M13 serves as a third transistor.
- the PMOS transistors Ml through M3 and M13, the NMOS transistors M4 and M12, the reference voltage generating circuit 3, the error amplifier circuit 4, and the resistors Rl and R2 are integrated in one IC in this example.
- the NMOS transistor M12 is connected between the output terminal of the operational amplifier circuit 11 and ground potential.
- the clock signal ⁇ 2 is inputted to a gate of the NMOS transistor M12.
- the PMOS transistor M13 is connected in parallel to the constant current source 12.
- An inversion signal ⁇ 2B which is an inverted clock signal ⁇ 2 is inputted to a gate of the PMOS transistor M13.
- the output signal AMPOUT of the error amplifier circuit 4 can be rapidly raised or dropped and the output signal AMPOUT in FIG. 2 can have a waveform as shown in FIG. 4.
- FIG. 3 only one of the NMOS transistor M12 and the PMOS transistor M13 may be provided.
- a charge stored in the flyback capacitor Cl is pumped into the catch- back capacitor Cout by the PMOS transistor M3 which connects the connecting terminal ClP connected to one terminal of the flyback capacitor Cl and the output terminal OUT connected to one terminal of the catch- back capacitor Cout, thereby the power source voltage VCC is raised.
- the raised output voltage Vout is fed back through a feed-back circuit, which is formed of the resistors Rl and R2 and connected to the output terminal OUT, to the error amplifier circuit 4 which controls the gate voltage of the PMOS transistor M3, thereby the on-resistance of the PMOS transistor M3 is controlled.
- the operation of the output transistor which is included in the charge pump circuit and connected between one terminal of the flyback capacitor included in the charge pump circuit and the output terminal of the charge pump circuit is controlled so that the proportional voltage which is in proportion to the output voltage outputted from the output terminal becomes the same level as a predetermined reference voltage.
- the output voltage of the charge pump circuit is controlled to be a constant voltage and supplied to the load. In this manner, a constant voltage required for stably driving the load can be outputted regardless of the change of the power source voltage.
- a regulator circuit having an output driver served by a transistor which connects one terminal of the flyback capacitor and the output terminal of the charge pump circuit is used among transistors included in the charge pump circuit. As a result, the increase of the chip size can be prevented.
- a gate voltage of a transistor which transmits a charge stored in the flyback capacitor to the catch-back capacitor is controlled in accordance with the level of the output voltage.
- the on-resistance of the transistor is controlled. In this manner, a stable output voltage can be obtained without increasing the ripple amplitude.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020107014773A KR101164348B1 (en) | 2008-01-15 | 2008-12-05 | Power supply circuit |
US12/811,924 US8278991B2 (en) | 2008-01-15 | 2008-12-05 | Power supply circuit and method for controlling the same |
CN200880124533.3A CN101911456B (en) | 2008-01-15 | 2008-12-05 | Power supply circuit and method for controlling the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008005844A JP4997122B2 (en) | 2008-01-15 | 2008-01-15 | Power supply circuit and operation control method thereof |
JP2008-005844 | 2008-01-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009090812A1 true WO2009090812A1 (en) | 2009-07-23 |
Family
ID=40885212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/072597 WO2009090812A1 (en) | 2008-01-15 | 2008-12-05 | Power supply circuit and method for controlling the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US8278991B2 (en) |
JP (1) | JP4997122B2 (en) |
KR (1) | KR101164348B1 (en) |
CN (1) | CN101911456B (en) |
WO (1) | WO2009090812A1 (en) |
Cited By (1)
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CN104615053A (en) * | 2015-01-19 | 2015-05-13 | 深圳市中科源电子有限公司 | Transistor-controlled electronic load control circuit |
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TW201105015A (en) * | 2009-07-22 | 2011-02-01 | Green Solution Tech Co Ltd | Charge pump circuit |
JP5560682B2 (en) | 2009-12-08 | 2014-07-30 | 株式会社リコー | Switching regulator |
JP2014050308A (en) | 2012-09-04 | 2014-03-17 | Ricoh Co Ltd | Switching regulator, and method of controlling the same |
JP5767660B2 (en) * | 2013-02-20 | 2015-08-19 | 株式会社東芝 | DC-DC converter |
CN103368383B (en) * | 2013-07-24 | 2015-09-02 | 苏州加古尔微电子科技有限公司 | For the ON-OFF control circuit of DC-DC boost converter |
JP6166619B2 (en) | 2013-08-23 | 2017-07-19 | リコー電子デバイス株式会社 | Switching regulator control circuit and switching regulator |
CN106849644B (en) * | 2017-02-08 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | The stabilizing circuit of charge pump output voltage |
US10003337B1 (en) * | 2017-05-17 | 2018-06-19 | International Business Machines Corporation | Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor |
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- 2008-12-05 WO PCT/JP2008/072597 patent/WO2009090812A1/en active Application Filing
- 2008-12-05 CN CN200880124533.3A patent/CN101911456B/en not_active Expired - Fee Related
- 2008-12-05 US US12/811,924 patent/US8278991B2/en not_active Expired - Fee Related
- 2008-12-05 KR KR1020107014773A patent/KR101164348B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
JP4997122B2 (en) | 2012-08-08 |
KR20100084582A (en) | 2010-07-26 |
US20100277227A1 (en) | 2010-11-04 |
CN101911456A (en) | 2010-12-08 |
CN101911456B (en) | 2014-02-19 |
KR101164348B1 (en) | 2012-07-09 |
US8278991B2 (en) | 2012-10-02 |
JP2009171710A (en) | 2009-07-30 |
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