WO2009097722A1 - Semiconductor epitaxial thin film package with vertical structure and the fabricating method thereof - Google Patents

Semiconductor epitaxial thin film package with vertical structure and the fabricating method thereof Download PDF

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Publication number
WO2009097722A1
WO2009097722A1 PCT/CN2008/073031 CN2008073031W WO2009097722A1 WO 2009097722 A1 WO2009097722 A1 WO 2009097722A1 CN 2008073031 W CN2008073031 W CN 2008073031W WO 2009097722 A1 WO2009097722 A1 WO 2009097722A1
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semiconductor epitaxial
layer
main surface
metal base
package
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PCT/CN2008/073031
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French (fr)
Chinese (zh)
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Hui Peng
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Jin, Peng
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Publication of WO2009097722A1 publication Critical patent/WO2009097722A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Definitions

  • the present invention discloses a semiconductor epitaxial thin film package that does not require a gold wire vertical structure, including a vertical structure of a gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based epitaxial thin film package (including , vertical structure of GaN-based, gallium phosphide-based, gallium phosphide-based and zinc oxide-based light-emitting diode (LED) epitaxial film packages), and low-cost production techniques and processes. It belongs to the field of semiconductor electronic technology.
  • the basic structure of the vertical structure semiconductor chip is as follows: The epitaxial film of the vertical structure semiconductor chip is bonded to the conductive support substrate through a reflective/ohmic layer/bonding layer to form a vertical structure semiconductor chip.
  • a semiconductor chip manufacturing a vertical structure of the basic process is as follows: the bonded semiconductor wafer (wafer bonding) on the conductive support substrate, peeling the growth substrate, forming an electrode, the semiconductor wafer (the wafer) is divided into semiconductor chips (chip).
  • the wafer bonding process for manufacturing a vertical structure chip and the process of peeling off the support substrate are complicated, resulting in damage of the epitaxial film, so that the yield is low and the cost is high.
  • the vertical structure semiconductor chip needs to hit at least one gold wire ( wire
  • the gold wire will cause reliability problems, and the space occupied by the gold wire increases the vertical structure of the semiconductor.
  • the thickness of the packaged socket of the chip, the gold wire will cause the packaging process to be complicated.
  • the present invention discloses a semiconductor epitaxial thin film package (including a gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based epitaxial film) that does not require a gold wire vertical structure.
  • the manufacturing method that does not require the wafer bonding process improves the yield and reduces the cost.
  • the present invention discloses a semiconductor thin film package that does not require a gold wire vertical structure and a low cost manufacturing method that does not require a wafer bonding process.
  • the structure of a specific embodiment of a vertically structured semiconductor epitaxial film package includes (Figs. 2 and 6) [9] (1) A packaged envelope; the packaged envelope includes one (Fig. 2a and Fig. 6a) or multiple (Fig. 6b) first metal base, one (Fig. 2a and Fig. 6b) or multiple (Fig. 6a) a second metal base and an insulating bracket.
  • the first metal base and the second metal base are electrically insulated from each other, and the first metal base and the second metal base each include a first major surface and a second major surface. The first major surface and the second major surface are in mutually opposite positions.
  • the insulating bracket fixes the first and second metal bases at predetermined positions, and the first main surface and the second main surface of the insulating bracket respectively correspond to the first main surface and the second main surface of the first metal base and the second metal base
  • the main surfaces have the same direction.
  • the package can include a first major surface and a second major surface, the first major surface and the second major surface of the package can respectively be the first major surface and the second major surface of the first metal base, and the second metal base
  • the first major surface and the second major surface and the first major surface and the second major surface of the insulating support are formed.
  • Figure 3 shows a specific embodiment: The first major surface of the insulating support is substantially flush with the first major surface of the first and second metal bases.
  • Figure 3a (a) shows a first embodiment of the electrode position: the second main surface of the first metal base and the second metal base will be electrically coupled to the two electrodes of the external power source, respectively; in this particular embodiment The second main surfaces of the first metal base and the second metal base may also be referred to as first and second electrodes, respectively.
  • Figure 3a (b) shows a first embodiment of the electrode position: the second main surface of the first metal base and the second metal base will be electrically coupled to the two electrodes of the external power source, respectively; in this particular embodiment The second main surfaces of the first metal base and the second metal base may also be referred to as first and second electrodes, respectively.
  • a second embodiment showing the position of the electrode the second main surface of the first metal base and the second metal base are enclosed in the insulating bracket, and the sides of the first metal base and the second metal base will respectively The two electrodes of the external power source are electrically coupled; in this embodiment, the sides of the first metal base and the second metal base are referred to as first and second electrodes, respectively.
  • Figure 3a (c) shows a third embodiment of the electrode position: the second main surface and the side of the first metal base and the second metal base can be electrically coupled to the two electrodes of the external power source, respectively.
  • the sides of the first metal base and the second metal base are referred to as first and second electrodes, respectively.
  • first and second electrodes the surfaces of the first metal base and the second metal base electrically coupled to the two electrodes of the external power source are referred to as first and second electrodes, respectively.
  • the active layer is laminated between the first type of confinement layer and the second type of confinement layer.
  • a passivation layer is laminated to cover the first main surface of the packaged envelope and the semiconductor epitaxial film.
  • the passivation layer is etched to have an opening at a predetermined position above the first type of confinement layer of the semiconductor epitaxial film and above the first main surface of the second metal pedestal.
  • the patterned electrode is laminated on the first type of confinement layer of the semiconductor epitaxial film through a window of a passivation layer over the surface of the first type of confinement layer of the semiconductor epitaxial film, and a direction extending from the second metal pedestal, laminated on the first major surface of the second metal pedestal through a window of the passivation layer over the first major surface of the second metal pedestal, such that the first type of semiconductor epitaxial film
  • the confinement layer is electrically coupled to the first major surface of the second metal base by the patterned electrode. Therefore, it is not necessary to electrically couple the first type of confinement layer of the semiconductor epitaxial film to the first main surface of the second metal pedestal by the gold wire in the encapsulation process.
  • each packaged package array (Fig. 1) includes at least one packaged envelope, each packaged envelope comprising: at least one first metal pedestal, At least one second metal base, and an insulating bracket.
  • the insulating bracket holds the first and second metal bases in a predetermined position.
  • a packaged package array includes a plurality of ordered packaged packages for automated production.
  • the shape of the packaged tube array can be a polygon (eg, Figure 138 ), a circle (eg, a figure), and the like.
  • the material of the insulating bracket includes: insulating injection molding material (molding
  • Insulating ceramics include aluminum nitride, aluminum oxide, and the like.
  • each semiconductor chip onto a first major surface of a corresponding first metal pedestal on the package can.
  • a conductive reflective/ohmic/bonding layer is laminated on the second type of confinement layer of the semiconductor chip.
  • a second type of confinement layer of the semiconductor chip is bonded to the first major surface of the first metal pedestal of the package via a conductive reflective/ohmic/bonding layer to electrically couple with the first electrode.
  • the stacked passivation layer is on the first major surface of the packaged tube array, gP, on the first major surface of each packaged package of the packaged package array.
  • the structure of the passivation layer includes a single layer or a plurality of layers, and the material of each layer may be selected from a group of materials including: a transparent insulating oxide and a transparent insulating nitride; the oxide includes: silicon oxide , aluminum oxide, zinc oxide; nitrides include: silicon nitride.
  • a passivation layer is etched to form a window at a predetermined position above the first type of confinement layer of each of the semiconductor epitaxial films and above the first main surface of the corresponding second metal pedestal.
  • the split package array is a single vertical structure semiconductor epitaxial film package, and the method of segmentation includes laser cutting or mechanical saw segmentation.
  • the present invention provides a vertical structure semiconductor (including gallium nitride-based, gallium phosphide-based, gallium phosphide-based, zinc oxide-based) epitaxial thin film package (including, gallium nitride based, gallium phosphide) Base, gallium phosphide-based, zinc oxide-based LED epitaxial film package) solves the above problems of low yield, high cost, complicated process, low reliability, large thickness of packaged stem caused by gold wire, and the like.
  • the present invention provides a low-cost semiconductor epitaxial film manufacturing process and a packaging process to produce a vertical structure semiconductor epitaxial film package process, the advantages of which are: (1) avoiding the wafer bonding process; (2) Simplifies the packaging process; as shown below:
  • the semiconductor epitaxial film and the second metal base of the corresponding package tube are directly electrically connected by using a patterned electrode instead of using a gold wire method to laminate the semiconductor epitaxial film in the process of packaging And electrically coupled to the second metal base of the corresponding packaged package.
  • the fabrication of a gold-plated vertical structure semiconductor chip package requires bonding twice, once to bond the semiconductor epitaxial wafer to the support wafer, and secondly to bond the vertical structure semiconductor chip to the package via.
  • the semiconductor epitaxial film package of the present invention which does not require a gold wire, requires only one bonding, gp, to flip-chip the chip directly onto the package.
  • the present invention provides a low-cost manufacturing process of a semiconductor epitaxial thin film package that does not require a gold wire. Since it is not necessary to etch any light-emitting layer material, the use of the light-emitting layer material is 100%, simplifying from chip to package. The manufacturing process has improved the yield. To date, any other vertical structure semiconductor chip that does not require a gold wire needs to etch away part of the luminescent layer material.
  • the present invention provides a low thermal resistance vertical structure semiconductor epitaxial film package: since the semiconductor epitaxial film is directly bonded to the metal pedestal, there is no supporting substrate and its thermal resistance.
  • the small-sized, lightweight, and thin vertical-structure semiconductor epitaxial thin film package provided by the present invention is particularly suitable for a backlight and a side view.
  • the present invention provides a maximum ratio of epitaxial film area to packaged envelope area.
  • the area of the epitaxial film is the same magnitude as the area of the packaged envelope, for example,
  • Epitaxial film area Package case area ⁇ 1 : 10.
  • the patterned electrode of the vertical structure semiconductor epitaxial thin film package provided by the present invention has the smallest light-shielding area, and has no light-shielding wire-bonding pad, and therefore, the light-emitting efficiency is high.
  • the present invention provides a vertical structure semiconductor epitaxial thin film package having high light extraction efficiency: surface roughening of a semiconductor epitaxial film and/or a passivation layer or a photonic crystal structure and a trench in a surface layer.
  • the vertical structure semiconductor epitaxial thin film package provided by the present invention has all the advantages of a vertical structure semiconductor chip, for example, no current crowding, high current, high heat transfer efficiency, and improved antistatic capability.
  • the vertical structure semiconductor epitaxial thin film package provided by the present invention is an SMD package.
  • Figures la and lb of Figure 1 show two specific embodiments of a packaged envelope array.
  • Figure 2a, Figure 2b, A-A cross-sectional view, and Figure 2c show a specific embodiment of a vertical structure semiconductor epitaxial film package.
  • FIG. 3 a ( a ), FIG. 3 a ( b ), FIG. 3 a ( c ), FIG. 3 b, FIG. 3 c, FIG. 3 d, FIG. 3 e, FIG. 3 f show the fabrication of a vertical structure semiconductor epitaxial film A specific embodiment of the method of packaging.
  • 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 1b, 4n, 4p, 4q show a vertical structure semiconductor epitaxial film A number of specific embodiments of packaged patterned electrodes.
  • Figure 5 shows a specific embodiment of a vertically structured semiconductor epitaxial film package with trenches.
  • Figure 6a, Figure 6b of Figure 6 shows a specific embodiment of a vertical semiconductor epitaxial film package with a plurality of semiconductor epitaxial films.
  • the material of the epitaxial film of the vertical structure semiconductor epitaxial film package provided by the present invention includes a gallium nitride-based, a gallium phosphide-based, a gallium phosphide-based, and a zinc oxide-based material.
  • the gallium nitride-based material includes: binary, ternary, and quaternary materials of gallium, aluminum, indium, and nitrogen.
  • the binary, ternary, and quaternary materials of gallium, aluminum, indium, and nitrogen include GaN, GalnN, AlGalnN, AlGalnN, and the like.
  • Gallium-based materials include: binary, ternary, and quaternary materials of gallium, aluminum, indium, and phosphorus. gallium
  • the binary, ternary, and quaternary materials of aluminum, indium, and phosphorus include GaP, GalnPs AlGalnP, In P, and the like.
  • Gallium phosphide-based materials include: binary, ternary, quaternary, and quaternary materials of gallium, aluminum, indium, nitrogen, and phosphorus.
  • the binary, ternary, quaternary, and pentary materials of gallium, aluminum, indium, nitrogen, and phosphorus include GaNP, AlGaNP, GalnNP, AlGalnNP, and the like.
  • the zinc oxide-based material includes, ZnO, and the like.
  • Gallium nitride-based, gallium phosphide-based, gallium-phosphorus-based, and zinc oxide-based epitaxial films include: gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based LED epitaxial films.
  • the crystal plane of the gallium nitride based epitaxial layer includes: a C-plane, an a-plane, and an m-plane.
  • each packaged housing includes: an insulative bracket, at least one first metal base, and at least one second metal base. To simplify the drawing, in Figure 1-5 (except Figure 6), each packaged case contains only one first metal base and one second metal base.
  • a roughened structure or a photonic crystal structure may be formed, or a roughened structure or a photonic crystal structure may be formed only on the surface of one of the semiconductor epitaxial film and the passivation layer.
  • a roughened structure or a photonic crystal structure may be formed only on the surface of one of the semiconductor epitaxial film and the passivation layer.
  • there is no roughening or photonic crystal structure Fig. 2, Fig. 3a-3c, Fig. 3g-3h, Fig. 4-6).
  • a trench structure may be formed in both the semiconductor epitaxial film and the passivation layer, or a trench structure may be formed only in one of the semiconductor epitaxial film and the passivation layer. To simplify the drawing, in some of the figures, there is no groove structure (Fig. 2, Fig. 3, Fig. 4h-4p, Fig. 6).
  • the trenches may be formed only in the passivation layer; the trenches may be formed only in the first type of confinement layer; the trenches may be formed in the passivation layer And the majority of the first type of confinement layer of the semiconductor epitaxial film; the trench can also The surface of the first metal pedestal is exposed through the passivation layer and the semiconductor epitaxial film.
  • the passivation layer has a window above the semiconductor epitaxial film and at a predetermined position above the first main surface of the corresponding second metal pedestal. In order to simplify the drawing, there is no window shown in Figure 4.
  • Insulation bracket materials include, insulating injection molding materials (molding
  • Insulating ceramics include aluminum nitride, aluminum oxide, and the like.
  • FIGS. 1a and 1b show two specific embodiments of polygonal and circular packaged tube arrays 100 and 110, respectively.
  • the packaged package array 100 (110) includes a plurality of packaged packages, each of the packaged cases including: an insulating support 101 (111), at least one first metal base 102 (112), and at least one second metal base 103 (113).
  • the polygonal and circular packaged tube arrays 100 and 110 in FIGS. 1a and 1b include 9 and 4 packaged housings, respectively, and each packaged housing includes only one first metal base 102. (112) and a second metal base 103 (113).
  • the packaged tube array can also be of other shapes.
  • FIG 2a shows a top view of one embodiment of a semiconductor epitaxial film package.
  • the semiconductor epitaxial thin film package 200 includes: an insulating holder 201, a first metal base 202, a second metal base 203, a semiconductor epitaxial film 204, a window 205 at a predetermined position above the semiconductor epitaxial film, and a second metal base.
  • a window 206 at a predetermined position above the first major surface of the seat 203, a patterned electrode 207.
  • a passivation layer is not shown in Figure 2a.
  • the patterned electrode 207 electrically couples the surface of the semiconductor epitaxial film 204 to the second metal base 203.
  • the other surface of the semiconductor epitaxial film 204 is electrically coupled to the first metal pedestal 202. Therefore, the semiconductor epitaxial film 204 does not need to be electrically connected to an external power source through a gold wire.
  • Figure 2b shows a cross-sectional view of the semiconductor epitaxial film package 200 of Figure 2a.
  • a semiconductor epitaxial film 204 is laminated on the first main surface of the first metal pedestal 202.
  • the semiconductor epitaxial film 204 includes: a first type of confinement layer 2 04a, an active layer 204b, and a second type of confinement layer 204c.
  • the passivation layer 208 has a window 205 above the semiconductor epitaxial film 204a, and a window 206 above the first main surface of the second metal pedestal 203.
  • the patterned electrode 207 includes: a portion 207a laminated on the exposed surface of the first type confinement layer 204a in the window 205, a portion 207b laminated on the surface of the passivation layer 208, and a second metal laminated in the window 206 A portion 207c of the exposed first major surface of the pedestal 203.
  • the first main surface of the insulating bracket 201 is substantially in the same plane as the first main surface of the first metal base 202 and the second metal base 203, which has the advantage of facilitating the chip manufacturing process. .
  • the first major surface of the insulating bracket 201 and the first major surface of the first metal base 202 and the second metal base 203 are also Can not be in the same plane.
  • Figure 2c shows another embodiment of a semiconductor epitaxial film package 200.
  • the first type restriction layer 204a includes: an N type restriction layer and an N+/N++ type restriction layer. Wherein, the N+/N++ type restriction layer is laminated between the active layer and the N type restriction layer.
  • a window 215 having the same position and shape as the window in the passivation layer 208 is formed in the N-type confinement layer until the N+/N++ type confinement layer is exposed.
  • the stacked patterned electrodes 217a are on the N+/N++ type confinement layer in the window 215 to reduce the resistance and improve the luminous efficiency.
  • the patterned electrodes can have different shapes, as shown in Figure 4.
  • the width ratio of the portion 207b of the patterned electrode 207 laminated on the passivation layer 208 and the portion 207c laminated on the second metal base 203 is laminated on the semiconductor.
  • the portion 207a on the epitaxial film 204 is large, which has the advantages that the reliability of the patterned electrode is improved, the resistance is reduced, and the heat dissipation efficiency is high.
  • FIG. 3 shows a specific embodiment of a process for fabricating a vertical structure semiconductor epitaxial film package.
  • Figure 3a shows the process flow step 1: manufacturing an ordered packaged package array (for example, the packaged tube array shown in Figure 1).
  • Each packaged envelope array includes at least one packaged envelope.
  • a packaged tube array includes a plurality of packaged tubes for automated production.
  • 3a(a), 3a(b) and 3a(c) respectively show cross-sectional views of three specific embodiments of a packaged envelope, the packaged envelope comprising: first metal bases 302a, 302b and 302c, second Metal bases 303a, 303b and 303c and insulating brackets 301a, 301b and 301c.
  • the first metal bases 302a, 302b, and 302c have first major surfaces 33a, 33b and 331c and second major surfaces 332a, 332b, and 332c, respectively.
  • the second metal bases 303a, 303b, and 303c have first main surfaces 341a, 341b, and 341c and second main surfaces 342a, 342b, and 342c, respectively.
  • the insulating brackets 301a, 301b, and 301c have first main surfaces 321a, 321b, and 321c and second main surfaces 322a, 322b, and 322c, respectively.
  • the insulating bracket 301 fixes the first and second metal bases at predetermined positions.
  • the sides 352b and 352c of the first metal pedestals 302b and 3020 can also serve as first electrodes, respectively; second metal pedestals 303b and 3030
  • the side faces 353b and 353c may also serve as the second electrodes, respectively.
  • the packaged envelope includes a first major surface and a second major surface, and the first major surface and the second major surface of the packaged envelope shown in Figures 3a(a), 3a(b), and 3a(c) are respectively First main surfaces 331a, 331b and 331c and second main surfaces 332a, 332b and 332c of the metal base, first main surfaces 341a, 341b and 341c and second main surfaces 342a, 342b and 342c of the second metal base and First main surfaces 321a, 321b and 321c of the insulating support and The two main surfaces 322a, 322b and 322c are formed.
  • a specific embodiment of the insulating bracket the first main surfaces 321a, 321b and 321c of the insulating bracket shown in Figures 3a(a), 3a(b) and 3a(c) and the first main body of the first metal base, respectively
  • the surfaces 33 la, 33 lb and 331c and the first major surfaces 341a, 341b and 341c of the second metal base are substantially in the same plane.
  • the second major surfaces 332a and 342a of the first and second metal bases shown in Fig. 3a (a) are on the bottom surface (second main surface 322a) of the insulating holder.
  • the 32b and 342b are enclosed in an insulating bracket.
  • the side surfaces 352b and 353b of the first and second metal bases are electrically coupled to the two electrodes of the external power source as the first and second electrodes, respectively.
  • the second main surfaces 332c and 342c of the first and second metal bases shown in Fig. 3a (c) are on the bottom surface of the insulating holder (the second main surface 322c, the side surfaces 352c and 353c of the first and second metal bases, respectively As the first and second electrodes, the two electrodes of the external power source are electrically coupled.
  • the second main surfaces of the first and second metal bases are on the bottom surface of the insulating holder, it should be understood that in other figures, the side surfaces of the first and second metal bases may also be the first and second electrodes respectively on the side of the insulating bracket. Alternatively, the side surface of one metal base may be on the side of the insulating bracket. The second major surface of the other metal base is on the bottom surface of the insulating bracket.
  • FIG. 3b shows the process steps 2: Flip-chip soldering (flip)
  • each semiconductor chip onto a first major surface of a first metal pedestal on a corresponding packaged package.
  • the semiconductor chip includes: a growth substrate 310 and an epitaxial film 304.
  • a conductive reflective/ohmic/bonding layer (not shown) is laminated on the epitaxial film 304 of the semiconductor chip.
  • the epitaxial film 304 of the semiconductor chip is bonded to the first major surface of the first metal pedestal 302 of the package via a conductive reflective/ohmic/bonding layer.
  • the conductive reflective/ohmic/bonding layer has a multilayer structure; the material of each layer is selected from a group of materials including: distributed Bragg reflective layer, metallic aluminum, silver, gold, tin, nickel, chromium , titanium, tantalum, and alloys of the above metals, alloys of metals including gold tin, silver tin, gold ruthenium, and the like.
  • Conductive reflection / ohmic / bonding layer functions include reflection, ohmic contact and bonding.
  • Figure 3c shows a process flow step 3: Peeling the growth substrate 310 of the semiconductor chip until the first type of confinement layer 304a of the semiconductor epitaxial film is exposed.
  • the method of peeling off the growth substrate of the semiconductor chip differs depending on the material of the semiconductor chip.
  • the method comprises: stripping the sapphire growth substrate and the GaAs growth substrate; or stripping the GaAs growth substrate of the gallium phosphide-based chip by ion implantation; or a combination of the above methods, for example, first reducing the phosphorus by a precision grinding/polishing method
  • a gallium-based chip is grown on the GaAs substrate, and then the remaining portion of the GaAs growth substrate of the gallium phosphide-based chip is stripped by a dry/wet etching method;
  • a roughened (or photonic crystal) structure 361 is formed on the surface of the first type of confinement layer 304a.
  • a trench structure 362 is formed in the first type of confinement layer 304a
  • Figure 3d shows the process flow step 4: laminating the passivation layer 308 on the packaged tube array.
  • the structure of the passivation layer includes a single layer or a plurality of layers, and the material of each layer may be selected from a group of materials including: a transparent insulating oxide and a transparent insulating nitride; the oxide includes : silicon oxide, aluminum oxide, zinc oxide; the nitride includes: silicon nitride.
  • a roughened (or photonic crystal) structure 311 is formed on the surface of the passivation layer 308.
  • a trench structure 312 is formed in the passivation layer 308 and the first type of confinement layer 304a. To simplify the drawing, FIG.
  • the same; the rough (or photonic crystal) structure and the trench structure are no longer shown in the following figures.
  • Figure 3e shows a process flow step 5: etching a passivation layer 308 at a predetermined location of each packaged package, forming a window 305 over the first type of confinement layer of the semiconductor epitaxial film 304 , at the second metal pedestal 303 A window 306 is formed at a predetermined position above the first major surface.
  • Methods of etching include: dry and wet etching.
  • FIG. 3f shows a process flow step 6: stacking the patterned electrodes to the first type of confinement layer of semiconductor epitaxial film 304 and the corresponding second metal pedestal 303 through windows 305 and 306 on passivation layer 308 On a major surface, a first type of confinement layer of semiconductor epitaxial film 304 is electrically coupled to a first major surface of a second metal pedestal 303 of a corresponding packaged package.
  • the patterned electrode includes: a portion 307a laminated on the exposed surface of the first type of confinement layer 304 in the window 305, a portion 30 7b laminated on the surface of the passivation layer 308, and a second metal laminated in the window 306 A portion 307c of the exposed first major surface of the pedestal 303.
  • the split package array is a single vertical structure semiconductor epitaxial film package, and the segmentation method includes laser cutting or mechanical saw segmentation, and the like.
  • FIG. 4 shows various embodiments of the shape of the patterned electrode, including: single lines, multiple lines, grids, rings, spirals, multiple forks, etc., to make the current distribution more uniform and less occluded light .
  • Figure 4a shows the single line shape of the patterned electrode: a single line shaped patterned electrode 407 is layered along the half
  • the conductor epitaxial film 404 is electrically coupled to the first main surface of the second metal pedestal 403 in the long-axis direction, and the semiconductor epitaxial film 404 is laminated on the first metal pedestal 402.
  • This type of semiconductor epitaxial film and single-line shaped patterned electrode are particularly suitable for side-emitting light sources.
  • FIG. 4b shows another embodiment of the single line shape of the patterned electrode: a single line shaped patterned electrode 417 is laminated along the long axis direction of the semiconductor epitaxial film 414 and extends to both ends to the second metal.
  • the first major surface of the pedestal 413 is electrically coupled at two locations, and a semiconductor epitaxial film 414 is laminated on the first metal pedestal 412.
  • the second metal base 413 has a gate shape.
  • FIG. 4c shows a multi-line shape in which the patterned electrodes are coupled to each other: the interconnected multi-line shaped patterned electrodes 427 are laminated on the long axis direction of the semiconductor epitaxial film 424 and the second metal base 423 A main surface is electrically coupled, and a semiconductor epitaxial film 424 is laminated on the first metal base 422.
  • Figures 4a, 4b, and 4c include patterned trenches 4013, 4113, and 4213.
  • Figure 2a shows another embodiment of a multi-line shape in which the patterned electrodes are not coupled to each other.
  • 4d, 4e, 4f, and 4g show the grid shape of the patterned electrode: grid-shaped patterned electrodes 437, 447, 457, and 467 are laminated on the semiconductor epitaxial films 434, 444, 454, and 464, respectively. And electrically coupled to the first main surfaces of the second metal pedestals 433, 443, 453, and 463, respectively, and the semiconductor epitaxial films 434, 444, 454, and 464 are laminated on the first metal pedestals 432, 442, 452, and 462, respectively. On the first major surface. Patterned trenches 4313, 4413, 4513, and 4613 are formed between the parallel portions of patterned electrodes 437, 447, 457, and 467, respectively.
  • 4h and 4j show the ring shape of the patterned electrode: ring-shaped patterned electrodes 477 and 487 are laminated on the semiconductor epitaxial films 474 and 484 , respectively, and the first mains of the second metal pedestals 473 and 483 , respectively. Surface electrical connections, semiconductor epitaxial films 474 and 484 are laminated on the first major surfaces of first metal pedestals 472 and 482, respectively.
  • the ring-shaped patterned electrodes may be single-ring or multi-rings that are coupled to each other.
  • the spiral shaped patterned electrodes 497 and 4107 are laminated on the semiconductor epitaxial films 494 and 4104, respectively, and respectively associated with the first mains of the second metal pedestals 493 and 4103. Surface electrical connections, semiconductor epitaxial films 494 and 4104 are laminated on the first major surfaces of the first metal pedestals 492 and 4102, respectively.
  • FIG. 4n and FIG. 4p show the fork shape of the patterned electrode: the fork-shaped patterned electrodes 4207 and 4307 are respectively layered Overlying the semiconductor epitaxial films 4204 and 4304 and electrically coupled to the first major surfaces of the second metal pedestals 4203 and 4303, respectively, the semiconductor epitaxial films 4204 and 4304 are laminated on the first major surfaces of the first metal pedestals 4202 and 4302, respectively. on.
  • the fork-shaped patterned electrode includes: a single fork or a multi-fork that is coupled to each other.
  • Figure 4k, Figure 4m, Figure 4n and Figure 4p do not show graphical grooves.
  • Figure 4q shows another multi-line shape of the patterned electrode: a multi-line shaped patterned electrode 4407 is laminated on the semiconductor epitaxial film 4404 and electrically coupled to the first major surface of the second metal pedestal 4403, the semiconductor epitaxial film 4404 is laminated on the first metal base 4402. A trench 4413 is formed between the parallel portions of the patterned electrode 4407.
  • Figure 5 shows a top view of one embodiment of a trench of a semiconductor epitaxial film package.
  • the semiconductor epitaxial film package comprises: an insulating holder 501, a first metal base 502, a second metal base 503, a semiconductor epitaxial film 504 laminated on the first metal base 502, and a patterned electrode 507 laminated on the semiconductor epitaxial film
  • the predetermined position is on the window 505 and the window 506 on the predetermined position above the first major surface of the second metal base.
  • a passivation layer is not shown in FIG.
  • a trench 513 is formed between the patterned electrodes 4407.
  • Figure 6a shows a top view of one embodiment of a semiconductor epitaxial film package.
  • the semiconductor epitaxial film package comprises: an insulating bracket 601, a first metal base 602, eight second metal bases 603a to 603h, and eight semiconductor epitaxial films 604 are stacked on the first metal base 602, eight patterned
  • the electrodes 607 are laminated on the eight semiconductor epitaxial films and the first major surfaces of the corresponding eight second metal pedestals, respectively. Passivation layers and windows are not shown in Figure 6a.
  • the first type of confinement layer of the surface of the semiconductor epitaxial film 604 is an N type confinement layer
  • the eight semiconductor epitaxial films 604 are powered by the common anode control circuit.
  • Figure 6b shows a top view of one embodiment of a semiconductor epitaxial film package.
  • the semiconductor epitaxial film package comprises: an insulating holder 611, six first metal bases 612a to 612f, a gate-shaped second metal base 6 13, and six semiconductor epitaxial films 614 stacked on the six first metal bases 612, respectively.
  • Six patterned electrodes 617 are stacked on the six semiconductor epitaxial films 614 and on the first major surface of a second metal pedestal 613, respectively. Passivation layers and windows are not shown in Figure 6b.
  • the first type of confinement layer of the surface of the semiconductor epitaxial film 614 is an N type confinement layer
  • the six semiconductor epitaxial films 614 are powered by the common cathode control circuit.
  • a trench may be formed in the passivation layer and/or the first type of confinement layer.

Abstract

A vertical semiconductor epitaxial thin film package and the fabricating method thereof are provided. The thin film package comprises:a package tube shell with a first metal substrate (202), a second metal substrate (203) and an insulating bracket (201), a semiconductor epitaxial thin film (204) stacked on the first metal substrate, a passivation layer (208) covering the package tube shell and the semiconductor epitaxial thin film, and a patterned electrode (207). The first and second metal substrates connect with two electrodes of an external power source,respectively. The insulating bracket holds the first and second metal substrates in predetermined positions.The passivation layer has windows (205,206) above the semiconductor epitaxial thin film and the second metal substrate. The patterned electrode is on the passivation layer,and connects with the semiconductor epitaxial thin film and the second metal substrate via the windows.

Description

垂直结构的半导体外延薄膜封装及其制造方法  Vertical structure semiconductor epitaxial film package and manufacturing method thereof
技术领域 Technical field
[ 1] 本发明揭示一种不需要打金线的垂直结构的半导体外延薄膜封装， 包括， 垂直 结构的氮化镓基、 磷化镓基、 镓氮磷基和氧化锌基外延薄膜封装 （包括， 垂直 结构的氮化镓基、 磷化镓基、 镓氮磷基和氧化锌基发光二极管 (LED)外延薄膜封 装） ， 及低成本的生产技术和工艺。 属于半导体电子技术领域。  [1] The present invention discloses a semiconductor epitaxial thin film package that does not require a gold wire vertical structure, including a vertical structure of a gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based epitaxial thin film package (including , vertical structure of GaN-based, gallium phosphide-based, gallium phosphide-based and zinc oxide-based light-emitting diode (LED) epitaxial film packages), and low-cost production techniques and processes. It belongs to the field of semiconductor electronic technology.
[2] 背景技术 [2] Background Art
[3] 大功率半导体发光二极管具有巨大前途， 但是， 技术和生产需要不断改进。 垂 直结构半导体芯片的基本结构如下： 垂直结构半导体芯片的外延薄膜通过反射 / 欧姆层 /键合层键合在导电支持衬底上， 形成垂直结构半导体芯片。 制造垂直结 构半导体芯片的基本工艺如下： 键合半导体晶片 （wafer bonding) 在导电支持衬底上， 剥离生长衬底， 形成电极， 把半导体晶片 （wafer ) 分割成半导体芯片 （chip) 。 但是， 制造垂直结构芯片的晶片键合工艺和剥离 支持衬底工艺复杂， 造成外延薄膜损伤， 因此良品率低， 成本高。 另外， 垂直 结构半导体芯片需要打至少一根金线 （wire [3] High-power semiconductor light-emitting diodes have great promise, but technology and production need to be continuously improved. The basic structure of the vertical structure semiconductor chip is as follows: The epitaxial film of the vertical structure semiconductor chip is bonded to the conductive support substrate through a reflective/ohmic layer/bonding layer to form a vertical structure semiconductor chip. A semiconductor chip manufacturing a vertical structure of the basic process is as follows: the bonded semiconductor wafer (wafer bonding) on the conductive support substrate, peeling the growth substrate, forming an electrode, the semiconductor wafer (the wafer) is divided into semiconductor chips (chip). However, the wafer bonding process for manufacturing a vertical structure chip and the process of peeling off the support substrate are complicated, resulting in damage of the epitaxial film, so that the yield is low and the cost is high. In addition, the vertical structure semiconductor chip needs to hit at least one gold wire ( wire
bonding) ， 从而与外界电源相连接， 金线会造成可靠性问题， 金线所占用的空 间增大了垂直结构半导 ί本芯片的封装管座的厚度， 金线会造成封装工艺复杂。  Bonding, thus connecting with the external power supply, the gold wire will cause reliability problems, and the space occupied by the gold wire increases the vertical structure of the semiconductor. The thickness of the packaged socket of the chip, the gold wire will cause the packaging process to be complicated.
[4] 为解决上述金线造成的问题， 不需要打金线的 3维垂直结构半导体芯片及生产 技术和工艺被提出 [中国专利申请， 申请号： 200610145039.8]。 [4] In order to solve the problems caused by the above gold wire, a 3-dimensional vertical structure semiconductor chip that does not require gold wire and a production technique and process are proposed [Chinese Patent Application, Application No.: 200610145039.8].
[5] 本发明公幵一种不需要打金线的垂直结构的半导体外延薄膜封装 （包括， 氮化 镓基、 磷化镓基、 镓氮磷基和氧化锌基外延薄膜.） 及低成本的不需要晶片键合 工艺的制造方法， 提高良品率， 降低成本。 [5] The present invention discloses a semiconductor epitaxial thin film package (including a gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based epitaxial film) that does not require a gold wire vertical structure. The manufacturing method that does not require the wafer bonding process improves the yield and reduces the cost.
[6] 发明内容 [6] Summary of the invention
本发明揭示不需要打金线的垂直结构的半导体外延薄膜封装 （thin film package) 及低成本的不需要晶片键合工艺的制造方法。  The present invention discloses a semiconductor thin film package that does not require a gold wire vertical structure and a low cost manufacturing method that does not require a wafer bonding process.
垂直结构的半导体外延薄膜封装的具体实施例的结构包括 （图 2和图 6) [9] (1) 一个封装管壳； 封装管壳包括一个 （图 2a和图 6a) 或多个 （图 6b) 第一 金属基座， 一个 （图 2a和图 6b) 或多个 (图 6a) 第二金属基座和绝缘支架。 第一 金属基座和第二金属基座互相电绝缘， 第一金属基座和第二金属基座各自包括 第一主表面和第二主表面。 第一主表面和第二主表面处于互相相对的位置。 绝 缘支架把第一和第二金属基座固定在预定的位置， 绝缘支架的第一主表面和第 二主表面分别与第一金属基座和第二金属基座的第一主表面和第二主表面有相 同的方向。 封装管壳包括第一主表面和第二主表面， 封装管壳的第一主表面和 第二主表面分别由第一金属基座的第一主表面和第二主表面、 第二金属基座的 第一主表面和第二主表面和绝缘支架的第一主表面和第二主表面构成。 图 3展示 一个具体实施例： 绝缘支架的第一主表面与第一和第二金属基座的第一主表面 基本相平。 图 3a(a)展示电极位置的第一个具体实施例： 第一金属基座和第二金 属基座的第二主表面将分别与外界电源的两个电极电联接； 在这个具体实施例 中， 也可以把第一金属基座和第二金属基座的第二主表面分别称为第一和第二 电极。 图 3a(b) The structure of a specific embodiment of a vertically structured semiconductor epitaxial film package includes (Figs. 2 and 6) [9] (1) A packaged envelope; the packaged envelope includes one (Fig. 2a and Fig. 6a) or multiple (Fig. 6b) first metal base, one (Fig. 2a and Fig. 6b) or multiple (Fig. 6a) a second metal base and an insulating bracket. The first metal base and the second metal base are electrically insulated from each other, and the first metal base and the second metal base each include a first major surface and a second major surface. The first major surface and the second major surface are in mutually opposite positions. The insulating bracket fixes the first and second metal bases at predetermined positions, and the first main surface and the second main surface of the insulating bracket respectively correspond to the first main surface and the second main surface of the first metal base and the second metal base The main surfaces have the same direction. The package can include a first major surface and a second major surface, the first major surface and the second major surface of the package can respectively be the first major surface and the second major surface of the first metal base, and the second metal base The first major surface and the second major surface and the first major surface and the second major surface of the insulating support are formed. Figure 3 shows a specific embodiment: The first major surface of the insulating support is substantially flush with the first major surface of the first and second metal bases. Figure 3a (a) shows a first embodiment of the electrode position: the second main surface of the first metal base and the second metal base will be electrically coupled to the two electrodes of the external power source, respectively; in this particular embodiment The second main surfaces of the first metal base and the second metal base may also be referred to as first and second electrodes, respectively. Figure 3a (b)
展示电极位置的第二个具体实施例： 第一金属基座和第二金属基座的第二主表 面被封闭在绝缘支架中， 第一金属基座和第二金属基座的侧面将分别与外界电 源的两个电极电联接； 在这个具体实施例中， 把第一金属基座和第二金属基座 的侧面分别称为第一和第二电极。 图 3a(c)展示电极位置的第三个具体实施例： 第一金属基座和第二金属基座的第二主表面和侧面都可以分别与外界电源的两 个电极电联接， 在这个具体实施例中， 把第一金属基座和第二金属基座的侧面 分别称为第一和第二电极。  A second embodiment showing the position of the electrode: the second main surface of the first metal base and the second metal base are enclosed in the insulating bracket, and the sides of the first metal base and the second metal base will respectively The two electrodes of the external power source are electrically coupled; in this embodiment, the sides of the first metal base and the second metal base are referred to as first and second electrodes, respectively. Figure 3a (c) shows a third embodiment of the electrode position: the second main surface and the side of the first metal base and the second metal base can be electrically coupled to the two electrodes of the external power source, respectively. In the embodiment, the sides of the first metal base and the second metal base are referred to as first and second electrodes, respectively.
[10] 总之， 把第一金属基座和第二金属基座的与外界电源的两个电极电联接的表面 分别称为第一和第二电极。  [10] In summary, the surfaces of the first metal base and the second metal base electrically coupled to the two electrodes of the external power source are referred to as first and second electrodes, respectively.
[11] (2) 一个 （图 2) 或多个 (图 6) 半导体外延薄膜。 半导体外延薄膜的结构包括 [11] (2) One (Fig. 2) or multiple (Fig. 6) semiconductor epitaxial films. The structure of the semiconductor epitaxial film includes
， 第一类型限制层， 活化层， 第二类型限制层。 活化层层叠在第一类型限制层 和第二类型限制层之间。 , a first type of limiting layer, an active layer, and a second type of limiting layer. The active layer is laminated between the first type of confinement layer and the second type of confinement layer.
[12] (3) 导电反射 /欧姆 /键合层。 导电反射 /欧姆 /键合层层叠在半导体外延薄膜的 第二类型限制层和第一金属基座的第一主表面之间， 把半导体外延薄膜的第二 类型限制层键合在第一金属基座的第一主表面上。 [12] (3) Conductive reflection / ohmic / bonding layer. A conductive reflective/ohmic/bonding layer is laminated between the second type of confinement layer of the semiconductor epitaxial film and the first main surface of the first metal pedestal, and the second of the semiconductor epitaxial film A type limiting layer is bonded to the first major surface of the first metal base.
[ 13] (4) 钝化层； 层叠钝化层， 使其覆盖封装管壳的第一主表面和半导体外延薄 膜。 蚀刻钝化层， 使其在半导体外延薄膜的第一类型限制层的上方和第二金属 基座的第一主表面的上方的预定的位置上具有窗口 （opening) 。  [13] (4) A passivation layer; a passivation layer is laminated to cover the first main surface of the packaged envelope and the semiconductor epitaxial film. The passivation layer is etched to have an opening at a predetermined position above the first type of confinement layer of the semiconductor epitaxial film and above the first main surface of the second metal pedestal.
[ 14] (5) 图形化的电极： 图形化的电极通过钝化层在半导体外延薄膜的第一类型 限制层的表面上方的窗口， 层叠在半导体外延薄膜的第一类型限制层上， 并向 第二金属基座的方向延伸， 通过钝化层在第二金属基座的第一主表面上方的窗 口， 层叠在第二金属基座的第一主表面上， 使得半导体外延薄膜的第一类型限 制层通过图形化电极与第二金属基座的第一主表面电联接。 因此， 不需要通过 封装工艺中的打金线把半导体外延薄膜的第一类型限制层与第二金属基座的第 一主表面电联接。  [14] (5) patterned electrode: the patterned electrode is laminated on the first type of confinement layer of the semiconductor epitaxial film through a window of a passivation layer over the surface of the first type of confinement layer of the semiconductor epitaxial film, and a direction extending from the second metal pedestal, laminated on the first major surface of the second metal pedestal through a window of the passivation layer over the first major surface of the second metal pedestal, such that the first type of semiconductor epitaxial film The confinement layer is electrically coupled to the first major surface of the second metal base by the patterned electrode. Therefore, it is not necessary to electrically couple the first type of confinement layer of the semiconductor epitaxial film to the first main surface of the second metal pedestal by the gold wire in the encapsulation process.
[ 15] 制造垂直结构的半导体外延薄膜封装的工艺步骤的一个具体实施例如下：  [15] A specific implementation of the process steps for fabricating a vertical structure semiconductor epitaxial thin film package is as follows:
[ 16] ( 1 ) 制造排列有序的封装管壳列阵； 每个封装管壳列阵 （图 1 ) 包括至少一个 封装管壳， 每个封装管壳包括： 至少一个第一金属基座， 至少一个第二金属基 座， 和绝缘支架。 绝缘支架把第一和第二金属基座固定在预定的位置。 通常， 一个封装管壳列阵包括多个排列有序的封装管壳， 以便于自动化生产。 封装管 壳列阵的形状可以是多边形 （例如， 图1¾) ， 圆形 （例如， 图 ） ， 等。 绝缘支 架的材料包括， 绝缘注塑材料 （molding [16] (1) Manufacture of an ordered array of packaged envelopes; each packaged package array (Fig. 1) includes at least one packaged envelope, each packaged envelope comprising: at least one first metal pedestal, At least one second metal base, and an insulating bracket. The insulating bracket holds the first and second metal bases in a predetermined position. Typically, a packaged package array includes a plurality of ordered packaged packages for automated production. The shape of the packaged tube array can be a polygon (eg, Figure 138 ), a circle (eg, a figure), and the like. The material of the insulating bracket includes: insulating injection molding material (molding
compound) ， 绝缘陶瓷， 等。 绝缘陶瓷包括氮化铝， 氧化铝， 等。  Compound), insulating ceramics, etc. Insulating ceramics include aluminum nitride, aluminum oxide, and the like.
[ 17] (2) 倒装焊 （flip [17] (2) Flip-chip soldering (flip
chip) 每一个半导体芯片到封装管壳上的对应的第一金属基座的第一主表面上。 半导体芯片的第二类型限制层上层叠着导电反射 /欧姆 /键合层。 半导体芯片的第 二类型限制层通过导电反射 /欧姆 /键合层键合在封装管壳的第一金属基座的第一 主表面上， 从而与第一电极电联接。 本发明的制造垂直结构的半导体外延薄膜 封装的方法不需要晶片键合工艺， 而芯片的倒装焊工艺很成熟， 因此， 提高了 良品率。  Chip) each semiconductor chip onto a first major surface of a corresponding first metal pedestal on the package can. A conductive reflective/ohmic/bonding layer is laminated on the second type of confinement layer of the semiconductor chip. A second type of confinement layer of the semiconductor chip is bonded to the first major surface of the first metal pedestal of the package via a conductive reflective/ohmic/bonding layer to electrically couple with the first electrode. The method for fabricating a vertical structure semiconductor epitaxial film package of the present invention does not require a wafer bonding process, and the flip chip soldering process of the chip is mature, thereby improving the yield.
[ 18] (3) 剥离半导体芯片的生长衬底和缓冲层， 直到半导体外延薄膜的第一类型 限制层暴露。 剥离半导体芯片的生长衬底和缓冲层的方法随半导体芯片的材料 的不同而不同。 [18] (3) The growth substrate and the buffer layer of the semiconductor chip are peeled off until the first type of confinement layer of the semiconductor epitaxial film is exposed. A method of stripping a growth substrate and a buffer layer of a semiconductor chip with a material of the semiconductor chip The difference is different.
[19] (4) 层叠钝化层在封装管壳列阵的第一主表面上， gP， 封装管壳列阵的每一 个封装管壳的第一主表面上。 钝化层的结构包括单层或多层， 每层的材料可从 一组材料中选出， 该组材料包括： 透明的绝缘的氧化物和透明的绝缘的氮化物 ； 氧化物包括： 氧化硅， 氧化铝， 氧化锌； 氮化物包括： 氮化硅。 蚀刻钝化层 ， 在每一个半导体外延薄膜的第一类型限制层的上方和对应的第二金属基座的 第一主表面的上方的预定的位置上形成窗口。  [19] (4) The stacked passivation layer is on the first major surface of the packaged tube array, gP, on the first major surface of each packaged package of the packaged package array. The structure of the passivation layer includes a single layer or a plurality of layers, and the material of each layer may be selected from a group of materials including: a transparent insulating oxide and a transparent insulating nitride; the oxide includes: silicon oxide , aluminum oxide, zinc oxide; nitrides include: silicon nitride. A passivation layer is etched to form a window at a predetermined position above the first type of confinement layer of each of the semiconductor epitaxial films and above the first main surface of the corresponding second metal pedestal.
[20] (5) 通过钝化层上的窗口， 层叠图形化的电极到每一个半导体外延薄膜的第 一类型限制层和对应的第二金属基座的第一主表面上， 使的半导体外延薄膜的 第一类型限制层和对应的封装管壳的第二金属基座的第一主表面电联接， 从而 与第二电极电联接。 [20] (5) by patterning the electrodes on the passivation layer, onto the first main type of the first type of confinement layer of the semiconductor epitaxial film and the first main surface of the corresponding second metal pedestal, so that the semiconductor epitaxial A first type of confinement layer of the film is electrically coupled to a first major surface of the second metal pedestal of the corresponding packaged tube to electrically couple with the second electrode.
[21] (6) 分割封装管壳列阵为单个垂直结构半导体外延薄膜封装， 分割的方法包 括釆用激光切割或机械锯分割， 等。  [21] (6) The split package array is a single vertical structure semiconductor epitaxial film package, and the method of segmentation includes laser cutting or mechanical saw segmentation.
[22] 本发明的目的和能达到的各项效果如下： [22] The objects and effects of the present invention are as follows:
[23] ( 1) 本发明提供一种垂直结构半导体 （包括， 氮化镓基、 磷化镓基、 镓氮磷 基、 氧化锌基） 外延薄膜封装 （包括， 氮化镓基、 磷化镓基、 镓氮磷基、 氧化 锌基 LED外延薄膜封装） ， 解决了上述的良品率低、 成本高、 工艺复杂、 可靠性 低、 金线造成的封装管座的厚度大， 等问题。  [23] (1) The present invention provides a vertical structure semiconductor (including gallium nitride-based, gallium phosphide-based, gallium phosphide-based, zinc oxide-based) epitaxial thin film package (including, gallium nitride based, gallium phosphide) Base, gallium phosphide-based, zinc oxide-based LED epitaxial film package) solves the above problems of low yield, high cost, complicated process, low reliability, large thickness of packaged stem caused by gold wire, and the like.
[24] (2) 本发明提供低成本的半导体外延薄膜制造工艺和封装工艺混和的生产垂 直结构半导体外延薄膜封装的工艺方法， 其优势是： （1) 避免了晶片键合工艺 ； (2) 简化了封装工艺； 如下图所示： [24] (2) The present invention provides a low-cost semiconductor epitaxial film manufacturing process and a packaging process to produce a vertical structure semiconductor epitaxial film package process, the advantages of which are: (1) avoiding the wafer bonding process; (2) Simplifies the packaging process; as shown below:
从制造芯片到封装的 打金线的垂直 本发明的无需打金线的 工艺步骤 结构半导体芯片 垂直结构半导体芯片 封装 Vertical from the manufacture of the chip to the gold wire of the package. The process steps of the present invention without gold wire. Structure semiconductor chip Vertical structure semiconductor chip Package
1.分割晶片为芯片 无 有  1. Split the chip into a chip.
2a.晶片键合 有 （第一次键合） 无  2a. Wafer bonding Yes (first bonding) None
2b.芯片倒装焊键合 无 有 （只需一次键合）  2b. Chip flip-chip bonding None Yes (just one bond)
3.剥离衬底 有 有 3. Stripping the substrate
4.层叠钝化层 有 有  4. Laminated passivation layer
5.层叠图形化电极 有 有  5. Stacked patterned electrodes
6.分割复合晶片为芯片 有 有  6. Split the composite chip into a chip.
7.键合芯片到封装管壳 有 （第二次键合） 无  7. Bond the chip to the package tube. (Second bonding) None
8.打金线 有 无  8. Playing gold line
[25] 釆用芯片工艺流程 （wafer [25] 芯片 Chip Process (wafer
process) 中的形成图形化电极的方法， 用图形化电极直接把半导体外延薄膜和 对应的封装管壳的第二金属基座电联接， 代替在封装的工艺中用打金线方法把 半导体外延薄膜和对应的封装管壳的第二金属基座电联接。 制造打金线的垂直 结构半导体芯片封装需要键合两次， 一次是把半导体外延晶片键合到支持晶片 上， 第二次是把垂直结构半导体芯片键合到封装管壳。 而本发明的无需打金线 的半导体外延薄膜封装只需一次键合， gp， 把芯片直接倒装焊键合到封装管壳 上。  In the method of forming a patterned electrode, the semiconductor epitaxial film and the second metal base of the corresponding package tube are directly electrically connected by using a patterned electrode instead of using a gold wire method to laminate the semiconductor epitaxial film in the process of packaging And electrically coupled to the second metal base of the corresponding packaged package. The fabrication of a gold-plated vertical structure semiconductor chip package requires bonding twice, once to bond the semiconductor epitaxial wafer to the support wafer, and secondly to bond the vertical structure semiconductor chip to the package via. The semiconductor epitaxial film package of the present invention, which does not require a gold wire, requires only one bonding, gp, to flip-chip the chip directly onto the package.
[26] (3) 本发明提供低成本的不需要打金线的半导体外延薄膜封装的制造工艺， 因为不需要蚀刻任何发光层材料， 所以， 百分之百地利用发光层材料， 简化了 从芯片到封装的制造工艺， 提高了良品率。 至今， 任何其它的不需要打金线的 垂直结构半导体芯片都需要蚀刻掉部分的发光层材料。  [26] (3) The present invention provides a low-cost manufacturing process of a semiconductor epitaxial thin film package that does not require a gold wire. Since it is not necessary to etch any light-emitting layer material, the use of the light-emitting layer material is 100%, simplifying from chip to package. The manufacturing process has improved the yield. To date, any other vertical structure semiconductor chip that does not require a gold wire needs to etch away part of the luminescent layer material.
[27] (4) 本发明提供低热阻的垂直结构半导体外延薄膜封装： 由于半导体外延薄 膜直接键合到金属基座上， 没有支持衬底及其热阻。 (5) 本发明提供的体积小、 重量轻、 厚度薄的垂直结构半导体外延薄膜封装 特别适用于背光源 （backlight ) 和侧面光源 （side view) 。 本发明提供最大 的外延薄膜面积对封装管壳面积的比例。 一个具体实施例： 外延薄膜面积与封 装管壳面积是同一量级， 例如， [27] (4) The present invention provides a low thermal resistance vertical structure semiconductor epitaxial film package: since the semiconductor epitaxial film is directly bonded to the metal pedestal, there is no supporting substrate and its thermal resistance. (5) The small-sized, lightweight, and thin vertical-structure semiconductor epitaxial thin film package provided by the present invention is particularly suitable for a backlight and a side view. The present invention provides a maximum ratio of epitaxial film area to packaged envelope area. A specific embodiment: the area of the epitaxial film is the same magnitude as the area of the packaged envelope, for example,
外延薄膜面积： 封装管壳面积 ^ 1 : 10。  Epitaxial film area: Package case area ^ 1 : 10.
(6) 本发明提供的垂直结构半导体外延薄膜封装的图形化的电极的遮光面积 最小， 没有遮光的打线焊盘， 因此， 出光效率较高。  (6) The patterned electrode of the vertical structure semiconductor epitaxial thin film package provided by the present invention has the smallest light-shielding area, and has no light-shielding wire-bonding pad, and therefore, the light-emitting efficiency is high.
(7) 本发明提供高光取出效率的垂直结构半导体外延薄膜封装： 由于半导体 外延薄膜和 /或钝化层的表面粗化或光子晶体结构以及表面层中的沟槽。  (7) The present invention provides a vertical structure semiconductor epitaxial thin film package having high light extraction efficiency: surface roughening of a semiconductor epitaxial film and/or a passivation layer or a photonic crystal structure and a trench in a surface layer.
(8)本发明提供的垂直结构半导体外延薄膜封装具有垂直结构半导体芯片的 全部优点， 例如， 没有电流拥塞（crowding)， 可通过大电流， 热传导效率高， 抗静电能力提高， 等。  (8) The vertical structure semiconductor epitaxial thin film package provided by the present invention has all the advantages of a vertical structure semiconductor chip, for example, no current crowding, high current, high heat transfer efficiency, and improved antistatic capability.
(9)本发明提供的垂直结构半导体外延薄膜封装是 SMD封装。  (9) The vertical structure semiconductor epitaxial thin film package provided by the present invention is an SMD package.
本发明和它的特征及效益将在下面的详细描述中更好的展示。  The invention and its features and advantages will be better illustrated in the following detailed description.
附图说明 DRAWINGS
图 1中图 la、 图 lb展示封装管壳列阵的二个具体实施例。  Figures la and lb of Figure 1 show two specific embodiments of a packaged envelope array.
图 2中图 2 a、 图 2 b A— A截面图、 图 2 c展示垂直结构半导体外延薄膜 封装的一个具体实施例。  Figure 2a, Figure 2b, A-A cross-sectional view, and Figure 2c show a specific embodiment of a vertical structure semiconductor epitaxial film package.
图 3中图 3 a ( a )、 图 3 a ( b )、 图 3 a ( c )、 图 3 b、 图 3 c、 图 3 d、 图 3 e、 图 3 f 展示制造垂直结构半导体外延薄膜封装的方法的一个具体实施 例。  3 a ( a ), FIG. 3 a ( b ), FIG. 3 a ( c ), FIG. 3 b, FIG. 3 c, FIG. 3 d, FIG. 3 e, FIG. 3 f show the fabrication of a vertical structure semiconductor epitaxial film A specific embodiment of the method of packaging.
图 4中图 4a、 图 4b、 图 4c、 图 4d、 图 4e、 图 4f、 图 4g、 图 4h、 图 4j、 图 4k、 图½、 图 4n、 图 4p、 图 4q展示垂直结构半导体外延薄膜封装的图形化电 极的多个具体实施例。  4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 1b, 4n, 4p, 4q show a vertical structure semiconductor epitaxial film A number of specific embodiments of packaged patterned electrodes.
图 5展示带有沟槽的垂直结构半导体外延薄膜封装的一个具体实施例。  Figure 5 shows a specific embodiment of a vertically structured semiconductor epitaxial film package with trenches.
图 6中图 6 a、图 6 b展示带有多个半导体外延薄膜的垂直半导体外延薄膜 封装的具体实施例。 具体实施例和发明的详细描述  Figure 6a, Figure 6b of Figure 6 shows a specific embodiment of a vertical semiconductor epitaxial film package with a plurality of semiconductor epitaxial films. Detailed Description of the Specific Embodiments and Invention
虽然本发明的具体实施例将会在下面被描述，但下列各项描述只是说明本 发明的原¾, 而不是局限本发明于下列各项具体化实施实例的描述。  Although the specific embodiments of the present invention are described below, the following description is merely illustrative of the present invention, and is not intended to limit the invention to the description of the embodiments.
注意下列各项：  Note the following:
( 1 )图中各部分的比例不代表真实产品的比例。例如， 图 2a、 图 2b、 图 3f和图 5 中， 为了展示窗口， 把电极的尺寸画得比窗口小， 而实际上， 电极的尺寸和形状与窗口的 尺寸和形状完全相同。 [46] (2) 本发明提供的垂直结构半导体外延薄膜封装的外延薄膜的材料包括， 氮 化镓基、 磷化镓基、 镓氮磷基、 和氧化锌基材料。 其中， 氮化镓基材料包括： 镓、 铝、 铟、 氮的二元系、 三元系、 四元系材料。 镓、 铝、 铟、 氮的二元系、 三元系、 四元系材料包括， GaN, GalnN, AlGalnN, AlGalnN,等。 磷 (1) The proportion of each part in the figure does not represent the proportion of real products. For example, in Figures 2a, 2b, 3f, and 5, in order to show the window, the size of the electrode is drawn smaller than the window, and in fact, the size and shape of the electrode are exactly the same as the size and shape of the window. [46] (2) The material of the epitaxial film of the vertical structure semiconductor epitaxial film package provided by the present invention includes a gallium nitride-based, a gallium phosphide-based, a gallium phosphide-based, and a zinc oxide-based material. Among them, the gallium nitride-based material includes: binary, ternary, and quaternary materials of gallium, aluminum, indium, and nitrogen. The binary, ternary, and quaternary materials of gallium, aluminum, indium, and nitrogen include GaN, GalnN, AlGalnN, AlGalnN, and the like. phosphorus
[47] (3) 化镓基材料包括： 镓、 铝、 铟、 磷的二元系、 三元系、 四元系材料。 镓 [47] (3) Gallium-based materials include: binary, ternary, and quaternary materials of gallium, aluminum, indium, and phosphorus. gallium
、 铝、 铟、 磷的二元系、 三元系、 四元系材料包括， GaP、 GalnPs AlGalnP, In P， 等。 镓氮磷基材料包括： 镓、 铝、 铟、 氮、 磷的二元系、 三元系、 四元系和 五元系材料。 镓、 铝、 铟、 氮、 磷的二元系、 三元系、 四元系和五元系材料包 括， GaNP, AlGaNP, GalnNP, AlGalnNP,等。 氧化锌基材料包括， ZnO, 等。 氮化镓基、 磷化镓基、 镓氮磷基、 和氧化锌基外延薄膜包括： 氮化镓基、 磷化镓基、 镓氮磷基、 和氧化锌基 LED外延薄膜。 氮化镓基外延层的晶体平面包 括： C-平面， a-平面， m-平面。 The binary, ternary, and quaternary materials of aluminum, indium, and phosphorus include GaP, GalnPs AlGalnP, In P, and the like. Gallium phosphide-based materials include: binary, ternary, quaternary, and quaternary materials of gallium, aluminum, indium, nitrogen, and phosphorus. The binary, ternary, quaternary, and pentary materials of gallium, aluminum, indium, nitrogen, and phosphorus include GaNP, AlGaNP, GalnNP, AlGalnNP, and the like. The zinc oxide-based material includes, ZnO, and the like. Gallium nitride-based, gallium phosphide-based, gallium-phosphorus-based, and zinc oxide-based epitaxial films include: gallium nitride-based, gallium phosphide-based, gallium phosphide-based, and zinc oxide-based LED epitaxial films. The crystal plane of the gallium nitride based epitaxial layer includes: a C-plane, an a-plane, and an m-plane.
[48] (4) 本发明提供的制造垂直结构半导体外延薄膜封装的生产工艺的最后一道 工艺步骤是把带有半导体外延薄膜的封装管壳列阵分割为单个垂直结构半导体 外延薄膜封装。 所以， 为了简化画图， 在图 3展示的工艺的具体实施例的示意图 中， 以一个封装管壳和一个半导体外延薄膜， 展示生产工艺步骤。 每个封装管 壳包括： 绝缘支架， 至少一个第一金属基座， 至少一个第二金属基座。 为简化 画图， 在图 1-5中 （除图 6外） ， 每个封装管壳只包括一个第一金属基座和一个第 二金属基座。  [48] (4) The final process of the manufacturing process for fabricating a vertical structure semiconductor epitaxial thin film package provided by the present invention is to divide the packaged package array with the semiconductor epitaxial film into a single vertical structure semiconductor epitaxial film package. Therefore, in order to simplify the drawing, in the schematic diagram of a specific embodiment of the process shown in Fig. 3, the production process steps are shown in a packaged package and a semiconductor epitaxial film. Each packaged housing includes: an insulative bracket, at least one first metal base, and at least one second metal base. To simplify the drawing, in Figure 1-5 (except Figure 6), each packaged case contains only one first metal base and one second metal base.
[49] (5) 在垂直结构半导体外延薄膜封装中的半导体外延薄膜和钝化层的表面上 [49] (5) On the surface of the semiconductor epitaxial film and the passivation layer in the vertical structure semiconductor epitaxial film package
， 都可以形成粗化结构或光子晶体结构， 也可以只在半导体外延薄膜和钝化层 之一的表面上形成粗化结构或光子晶体结构。 为简化画图， 在有些图中， 没有 画粗化或光子晶体结构 （图 2， 图 3a-3c， 图 3g-3h， 图 4-6) 。 A roughened structure or a photonic crystal structure may be formed, or a roughened structure or a photonic crystal structure may be formed only on the surface of one of the semiconductor epitaxial film and the passivation layer. To simplify the drawing, in some of the figures, there is no roughening or photonic crystal structure (Fig. 2, Fig. 3a-3c, Fig. 3g-3h, Fig. 4-6).
[50] (6) 在半导体外延薄膜和钝化层中都可以形成沟槽结构， 也可以只在半导体 外延薄膜和钝化层之一中形成沟槽结构。 为简化画图， 在有些图中， 没有画沟 槽结构 （图 2， 图 3， 图 4h-4p， 图 6) 。 在钝化层和 /或第一类型限制层上形成沟 槽吋： 沟槽可以只形成在钝化层中； 沟槽可以只形成在第一类型限制层中； 沟 槽可以形成在钝化层和半导体外延薄膜的第一类型限制层的大部分； 沟槽也可 以穿过钝化层和半导体外延薄膜直到第一金属基座的表面暴露。 [50] (6) A trench structure may be formed in both the semiconductor epitaxial film and the passivation layer, or a trench structure may be formed only in one of the semiconductor epitaxial film and the passivation layer. To simplify the drawing, in some of the figures, there is no groove structure (Fig. 2, Fig. 3, Fig. 4h-4p, Fig. 6). Forming trenches on the passivation layer and/or the first type of confinement layer: the trenches may be formed only in the passivation layer; the trenches may be formed only in the first type of confinement layer; the trenches may be formed in the passivation layer And the majority of the first type of confinement layer of the semiconductor epitaxial film; the trench can also The surface of the first metal pedestal is exposed through the passivation layer and the semiconductor epitaxial film.
[51] (7) 钝化层在半导体外延薄膜的上方和在对应的第二金属基座的第一主表面 的上方的预定的位置上都有窗口。 为了简化画图， 图 4中没有展示窗口。  (7) The passivation layer has a window above the semiconductor epitaxial film and at a predetermined position above the first main surface of the corresponding second metal pedestal. In order to simplify the drawing, there is no window shown in Figure 4.
[52] (8) 绝缘支架的材料包括， 绝缘注塑材料 （molding  [52] (8) Insulation bracket materials include, insulating injection molding materials (molding
compound) ， 绝缘陶瓷， 等。 绝缘陶瓷包括氮化铝， 氧化铝， 等。  Compound), insulating ceramics, etc. Insulating ceramics include aluminum nitride, aluminum oxide, and the like.
[53] 图 la和图 lb分别展示多边形和圆形封装管壳列阵 100和 110两个具体实施例。 封 装管壳列阵 100 (110) 包括多个封装管壳， 每个封装管壳包括： 绝缘支架 101 ( 111) ， 至少一个第一金属基座 102 (112) ， 至少一个第二金属基座 103 (113) 。 为简化画图， 图 la和图 lb中的多边形和圆形封装管壳列阵 100和 110分别包括 9 个和 4个封装管壳， 并且， 每个封装管壳只包括一个第一金属基座 102 (112) 和 一个第二金属基座 103 (113) 。 封装管壳列阵也可以是其它形状。  [53] Figures la and lb show two specific embodiments of polygonal and circular packaged tube arrays 100 and 110, respectively. The packaged package array 100 (110) includes a plurality of packaged packages, each of the packaged cases including: an insulating support 101 (111), at least one first metal base 102 (112), and at least one second metal base 103 (113). To simplify the drawing, the polygonal and circular packaged tube arrays 100 and 110 in FIGS. 1a and 1b include 9 and 4 packaged housings, respectively, and each packaged housing includes only one first metal base 102. (112) and a second metal base 103 (113). The packaged tube array can also be of other shapes.
[54] 图 2a展示半导体外延薄膜封装的一个具体实施例的顶视图。 半导体外延薄膜封 装 200包括： 绝缘支架 201， 第一金属基座 202， 第二金属基座 203， 半导体外延 薄膜 204， 在半导体外延薄膜的上方的预定的位置上的窗口 205， 在第二金属基 座 203的第一主表面的上方的预定位置上的窗口 206， 图形化的电极 207。 图 2a中 没有画出钝化层。 图形化的电极 207把半导体外延薄膜 204的表面与第二金属基 座 203电联接。 半导体外延薄膜 204的另一个表面与第一金属基座 202电联接。 因 此， 半导体外延薄膜 204无需通过打金线与外界电源电联接。  Figure 2a shows a top view of one embodiment of a semiconductor epitaxial film package. The semiconductor epitaxial thin film package 200 includes: an insulating holder 201, a first metal base 202, a second metal base 203, a semiconductor epitaxial film 204, a window 205 at a predetermined position above the semiconductor epitaxial film, and a second metal base. A window 206 at a predetermined position above the first major surface of the seat 203, a patterned electrode 207. A passivation layer is not shown in Figure 2a. The patterned electrode 207 electrically couples the surface of the semiconductor epitaxial film 204 to the second metal base 203. The other surface of the semiconductor epitaxial film 204 is electrically coupled to the first metal pedestal 202. Therefore, the semiconductor epitaxial film 204 does not need to be electrically connected to an external power source through a gold wire.
[55] 图 2b展示图 2a的半导体外延薄膜封装 200的截面图。 半导体外延薄膜 204层叠在 第一金属基座 202的第一主表面上。 半导体外延薄膜 204包括： 第一类型限制层 2 04a, 活化层 204b， 第二类型限制层 204c。 钝化层 208在半导体外延薄膜 204a的上 方有窗口 205， 在第二金属基座 203的第一主表面的上方有窗口 206。 图形化的电 极 207包括： 层叠在窗口 205中的第一类型限制层 204a的暴露的表面上的部分 207a ， 层叠在钝化层 208的表面上的部分 207b， 层叠在窗口 206中的第二金属基座 203 的暴露的第一主表面上的部分 207c。  Figure 2b shows a cross-sectional view of the semiconductor epitaxial film package 200 of Figure 2a. A semiconductor epitaxial film 204 is laminated on the first main surface of the first metal pedestal 202. The semiconductor epitaxial film 204 includes: a first type of confinement layer 2 04a, an active layer 204b, and a second type of confinement layer 204c. The passivation layer 208 has a window 205 above the semiconductor epitaxial film 204a, and a window 206 above the first main surface of the second metal pedestal 203. The patterned electrode 207 includes: a portion 207a laminated on the exposed surface of the first type confinement layer 204a in the window 205, a portion 207b laminated on the surface of the passivation layer 208, and a second metal laminated in the window 206 A portion 207c of the exposed first major surface of the pedestal 203.
[56] 一个具体实施例： 绝缘支架 201的第一主表面与第一金属基座 202和第二金属基 座 203的第一主表面基本上在同一平面， 其优势是， 便于进行芯片制造工艺。 绝 缘支架 201的第一主表面与第一金属基座 202和第二金属基座 203的第一主表面也 可以不在同一平面。 A specific embodiment: the first main surface of the insulating bracket 201 is substantially in the same plane as the first main surface of the first metal base 202 and the second metal base 203, which has the advantage of facilitating the chip manufacturing process. . The first major surface of the insulating bracket 201 and the first major surface of the first metal base 202 and the second metal base 203 are also Can not be in the same plane.
[57] 图 2c展示半导体外延薄膜封装 200的另一个具体实施例。 第一类型限制层 204a 包括： N类型限制层和 N+/N++类型限制层。 其中， N+/N++类型限制层层叠在活 化层与 N类型限制层之间。 在形成钝化层 208中的窗口吋， 在 N类型限制层中形成 位置与形状与钝化层 208中的窗口相同的窗口 215， 直到 N+/N++类型限制层暴露 。 层叠图形化的电极 217a在窗口 215中的 N+/N++类型限制层上， 以便减小电阻， 提高发光效率。 图形化的电极可以有不同的形状， 如图 4所示。  Figure 2c shows another embodiment of a semiconductor epitaxial film package 200. The first type restriction layer 204a includes: an N type restriction layer and an N+/N++ type restriction layer. Wherein, the N+/N++ type restriction layer is laminated between the active layer and the N type restriction layer. In forming a window 钝化 in the passivation layer 208, a window 215 having the same position and shape as the window in the passivation layer 208 is formed in the N-type confinement layer until the N+/N++ type confinement layer is exposed. The stacked patterned electrodes 217a are on the N+/N++ type confinement layer in the window 215 to reduce the resistance and improve the luminous efficiency. The patterned electrodes can have different shapes, as shown in Figure 4.
[58] 在图 2展示的半导体外延薄膜封装 200中， 图形化的电极 207的层叠在钝化层 208 上的部分 207b和层叠在第二金属基座 203上的部分 207c的宽度比层叠在半导体外 延薄膜 204上的部分 207a大， 其优点是， 图形化的电极的可靠性提高， 电阻减低 ， 散热效率较高。  In the semiconductor epitaxial thin film package 200 shown in FIG. 2, the width ratio of the portion 207b of the patterned electrode 207 laminated on the passivation layer 208 and the portion 207c laminated on the second metal base 203 is laminated on the semiconductor. The portion 207a on the epitaxial film 204 is large, which has the advantages that the reliability of the patterned electrode is improved, the resistance is reduced, and the heat dissipation efficiency is high.
[59] 图 3展示制造垂直结构半导体外延薄膜封装的工艺的一个具体实施例。  [59] FIG. 3 shows a specific embodiment of a process for fabricating a vertical structure semiconductor epitaxial film package.
图 3a展示工艺流程步骤 1 : 制造排列有序的封装管壳列阵 （例如， 图 1所示的封 装管壳列阵） 。 每个封装管壳列阵包括至少一个封装管壳。 通常， 一个封装管 壳列阵包括多个封装管壳， 以便于自动化生产。 图 3a(a)、 图 3a(b)和图 3a (c)分别展示封装管壳的三个具体实施例的截面图， 封装管壳包括： 第一金属基 座 302a、 302b和 302c， 第二金属基座 303a、 303b和 303c和绝缘支架 301a、 301b和 301c。 第一金属基座 302a、 302b和 302c分别有第一主表面 33 la、 33 lb和 331c和第 二主表面 332a、 332b和 332c。 第二金属基座 303a、 303b和 303c分别有第一主表面 341a、 341b和 341c和第二主表面 342a、 342b和 342c。 绝缘支架 301a、 301b和 301c 分别有第一主表面 321a、 321b和 321c和第二主表面 322a、 322b和 322c。 绝缘支架 301把第一和第二金属基座固定在预定的位置。 图 3a(b)和图 3a(c)展示的封装管壳 的截面图中， 第一金属基座 302b和 3020的侧面 352b和 352c也可以分别作为第一电 极； 第二金属基座 303b和 3030的侧面 353b和 353c也可以分别作为第二电极。 封装 管壳包括第一主表面和第二主表面， 图 3a(a)、 图 3a(b)和图 3a(c)展示的封装管壳 的第一主表面和第二主表面分别由第一金属基座的第一主表面 331a、 331b和 331c 和第二主表面 332a、 332b和 332c、 第二金属基座的第一主表面 341a、 341b和 341c 和第二主表面 342a、 342b和 342c和绝缘支架的第一主表面 321a、 321b和 321c和第 二主表面 322a、 322b和 322c构成。 Figure 3a shows the process flow step 1: manufacturing an ordered packaged package array (for example, the packaged tube array shown in Figure 1). Each packaged envelope array includes at least one packaged envelope. Typically, a packaged tube array includes a plurality of packaged tubes for automated production. 3a(a), 3a(b) and 3a(c) respectively show cross-sectional views of three specific embodiments of a packaged envelope, the packaged envelope comprising: first metal bases 302a, 302b and 302c, second Metal bases 303a, 303b and 303c and insulating brackets 301a, 301b and 301c. The first metal bases 302a, 302b, and 302c have first major surfaces 33a, 33b and 331c and second major surfaces 332a, 332b, and 332c, respectively. The second metal bases 303a, 303b, and 303c have first main surfaces 341a, 341b, and 341c and second main surfaces 342a, 342b, and 342c, respectively. The insulating brackets 301a, 301b, and 301c have first main surfaces 321a, 321b, and 321c and second main surfaces 322a, 322b, and 322c, respectively. The insulating bracket 301 fixes the first and second metal bases at predetermined positions. 3a(b) and 3a(c), in a cross-sectional view of the package can, the sides 352b and 352c of the first metal pedestals 302b and 3020 can also serve as first electrodes, respectively; second metal pedestals 303b and 3030 The side faces 353b and 353c may also serve as the second electrodes, respectively. The packaged envelope includes a first major surface and a second major surface, and the first major surface and the second major surface of the packaged envelope shown in Figures 3a(a), 3a(b), and 3a(c) are respectively First main surfaces 331a, 331b and 331c and second main surfaces 332a, 332b and 332c of the metal base, first main surfaces 341a, 341b and 341c and second main surfaces 342a, 342b and 342c of the second metal base and First main surfaces 321a, 321b and 321c of the insulating support and The two main surfaces 322a, 322b and 322c are formed.
绝缘支架的一个具体实施例： 图 3a(a)、 图 3a(b)和图 3a(c)展示的绝缘支架的第一 主表面 321a、 321b和 321c分别与第一金属基座的第一主表面 33 la、 33 lb和 331c和 第二金属基座的第一主表面 341a、 341b和 341c基本上在同一平面。  A specific embodiment of the insulating bracket: the first main surfaces 321a, 321b and 321c of the insulating bracket shown in Figures 3a(a), 3a(b) and 3a(c) and the first main body of the first metal base, respectively The surfaces 33 la, 33 lb and 331c and the first major surfaces 341a, 341b and 341c of the second metal base are substantially in the same plane.
图 3a (a) 所示的第一和第二金属基座的第二主表面 332a和 342a在绝缘支架的 底面 （第二主表面 322a) 。 图 3a (b) 所示的第一和第二金属基座的第二主: The second major surfaces 332a and 342a of the first and second metal bases shown in Fig. 3a (a) are on the bottom surface (second main surface 322a) of the insulating holder. The second master of the first and second metal bases shown in Figure 3a (b):
32b和 342b被封闭在绝缘支架内。 第一和第二金属基座的侧表面 352b和 353b分别 作为第一和第二电极而与外界电源的两个电极电联接。 图 3a (c) 所示的第一和 第二金属基座的第二主表面 332c和 342c在绝缘支架的底面 （第二主表面 322c 第一和第二金属基座的侧表面 352c和 353c分别作为第一和第二电极而与外界电源 的两个电极电联接。 虽然在其它图中， 第一和第二金属基座的第二主表面都在 绝缘支架的底面， 但是， 应当理解为， 在其它图中， 第一和第二金属基座的侧 表面也可以在绝缘支架的侧面而分别作为第一和第二电极。 也可以是， 一个金 属基座的侧表面在绝缘支架的侧面， 另一个金属基座的第二主表面在绝缘支架 的底面。 32b and 342b are enclosed in an insulating bracket. The side surfaces 352b and 353b of the first and second metal bases are electrically coupled to the two electrodes of the external power source as the first and second electrodes, respectively. The second main surfaces 332c and 342c of the first and second metal bases shown in Fig. 3a (c) are on the bottom surface of the insulating holder (the second main surface 322c, the side surfaces 352c and 353c of the first and second metal bases, respectively As the first and second electrodes, the two electrodes of the external power source are electrically coupled. Although in other figures, the second main surfaces of the first and second metal bases are on the bottom surface of the insulating holder, it should be understood that In other figures, the side surfaces of the first and second metal bases may also be the first and second electrodes respectively on the side of the insulating bracket. Alternatively, the side surface of one metal base may be on the side of the insulating bracket. The second major surface of the other metal base is on the bottom surface of the insulating bracket.
[63] 图 3b展示工艺流程步骤 2: 倒装焊 （flip  [63] Figure 3b shows the process steps 2: Flip-chip soldering (flip)
chip) 每个半导体芯片到对应的封装管壳上的第一金属基座的第一主表面上。 半 导体芯片包括： 生长衬底 310和外延薄膜 304。 半导体芯片的外延薄膜 304上层叠 着导电反射 /欧姆 /键合层 （图中未画出） 。 半导体芯片的外延薄膜 304通过导电 反射 /欧姆 /键合层键合在封装管壳的第一金属基座 302的第一主表面上。 导电反 射 /欧姆 /键合层具有多层结构； 每层的材料是从一组材料中选出， 该组材料包括 ： 分布布喇格反射层， 金属铝， 银， 金， 锡， 镍， 铬， 钛， 铍， 及上述的金属 的合金， 金属的合金包括金锡， 银锡， 金铍， 等。 导电反射 /欧姆 /键合层的功能 包括反射、 欧姆接触和键合。  Chip) each semiconductor chip onto a first major surface of a first metal pedestal on a corresponding packaged package. The semiconductor chip includes: a growth substrate 310 and an epitaxial film 304. A conductive reflective/ohmic/bonding layer (not shown) is laminated on the epitaxial film 304 of the semiconductor chip. The epitaxial film 304 of the semiconductor chip is bonded to the first major surface of the first metal pedestal 302 of the package via a conductive reflective/ohmic/bonding layer. The conductive reflective/ohmic/bonding layer has a multilayer structure; the material of each layer is selected from a group of materials including: distributed Bragg reflective layer, metallic aluminum, silver, gold, tin, nickel, chromium , titanium, tantalum, and alloys of the above metals, alloys of metals including gold tin, silver tin, gold ruthenium, and the like. Conductive reflection / ohmic / bonding layer functions include reflection, ohmic contact and bonding.
[64] 图 3c展示工艺流程步骤 3: 剥离半导体芯片的生长衬底 310， 直到半导体外延薄 膜的第一类型限制层 304a暴露。 剥离半导体芯片的生长衬底的方法随半导体芯片 的材料的不同而不同。 例如， 釆用激光方法剥离氮化镓基芯片的蓝宝石生长衬 底； 釆用干 /湿蚀刻方法剥离磷化镓基芯片的 GaAs生长衬底； 釆用精密研磨 /抛光 方法剥离蓝宝石生长衬底和 GaAs生长衬底； 也可以釆用离子注入方法剥离磷化 镓基芯片的 GaAs生长衬底； 或上述方法的组合， 例如， 先釆用精密研磨 /抛光方 法减薄磷化镓基芯片的 GaAs生长衬底， 然后， 再釆用干 /湿蚀刻方法剥离磷化镓 基芯片的 GaAs生长衬底的剩余部分； 等。 在第一类型限制层 304a的表面上形成 粗化 （或光子晶体） 结构 361。 在第一类型限制层 304a中形成沟槽结构 362。 Figure 3c shows a process flow step 3: Peeling the growth substrate 310 of the semiconductor chip until the first type of confinement layer 304a of the semiconductor epitaxial film is exposed. The method of peeling off the growth substrate of the semiconductor chip differs depending on the material of the semiconductor chip. For example, a sapphire growth substrate in which a gallium nitride-based chip is stripped by a laser method; a GaAs growth substrate in which a gallium phosphide-based chip is stripped by a dry/wet etching method; and precision polishing/polishing The method comprises: stripping the sapphire growth substrate and the GaAs growth substrate; or stripping the GaAs growth substrate of the gallium phosphide-based chip by ion implantation; or a combination of the above methods, for example, first reducing the phosphorus by a precision grinding/polishing method A gallium-based chip is grown on the GaAs substrate, and then the remaining portion of the GaAs growth substrate of the gallium phosphide-based chip is stripped by a dry/wet etching method; A roughened (or photonic crystal) structure 361 is formed on the surface of the first type of confinement layer 304a. A trench structure 362 is formed in the first type of confinement layer 304a.
图 3d展示工艺流程步骤 4: 层叠钝化层 308在封装管壳列阵上。 钝化层的结构包 括单层或多层， 每层的材料可从一组材料中选出， 该组材料包括： 透明的绝缘 的氧化物和透明的绝缘的氮化物； 所述的氧化物包括： 氧化硅， 氧化铝， 氧化 锌； 所述的氮化物包括： 氮化硅。 在钝化层 308的表面上形成粗化 （或光子晶体 ) 结构 311。 在钝化层 308和第一类型限制层 304a中形成沟槽结构 312。 为简化画 图， 图 3d没有展示第一类型限制层 304a的表面粗化 （或光子晶体） 结构 361 ; 第 一类型限制层 304a中的沟槽结构 362与钝化层 308中的沟槽结构 312位置相同； 下 面的图中不再展示粗化 （或光子晶体） 结构和沟槽结构。  Figure 3d shows the process flow step 4: laminating the passivation layer 308 on the packaged tube array. The structure of the passivation layer includes a single layer or a plurality of layers, and the material of each layer may be selected from a group of materials including: a transparent insulating oxide and a transparent insulating nitride; the oxide includes : silicon oxide, aluminum oxide, zinc oxide; the nitride includes: silicon nitride. A roughened (or photonic crystal) structure 311 is formed on the surface of the passivation layer 308. A trench structure 312 is formed in the passivation layer 308 and the first type of confinement layer 304a. To simplify the drawing, FIG. 3d does not show the surface roughening (or photonic crystal) structure 361 of the first type of confinement layer 304a; the trench structure 362 in the first type confinement layer 304a and the trench structure 312 in the passivation layer 308. The same; the rough (or photonic crystal) structure and the trench structure are no longer shown in the following figures.
图 3e展示工艺流程步骤 5: 在每个封装管壳的预定的位置， 蚀刻钝化层 308， 在 半导体外延薄膜 304的第一类型限制层的上方形成窗口 305，在第二金属基座 303的 第一主表面的上方的预定的位置上形成窗口 306。 蚀刻的方法包括： 干法 (dry)和 湿法 （wet) 蚀刻。 Figure 3e shows a process flow step 5: etching a passivation layer 308 at a predetermined location of each packaged package, forming a window 305 over the first type of confinement layer of the semiconductor epitaxial film 304 , at the second metal pedestal 303 A window 306 is formed at a predetermined position above the first major surface. Methods of etching include: dry and wet etching.
[67] 图 3f展示工艺流程步骤 6: 通过钝化层 308上的窗口 305和 306， 层叠图形化的电 极到半导体外延薄膜 304的第一类型限制层和对应的第二金属基座 303的第一主 表面上， 使的半导体外延薄膜 304的第一类型限制层和对应的封装管壳的第二金 属基座 303的第一主表面电联接。 图形化的电极包括： 层叠在窗口 305中的第一 类型限制层 304的暴露的表面上的部分 307a， 层叠在钝化层 308的表面上的部分 30 7b , 层叠在窗口 306中的第二金属基座 303的暴露的第一主表面上的部分 307c。  [67] FIG. 3f shows a process flow step 6: stacking the patterned electrodes to the first type of confinement layer of semiconductor epitaxial film 304 and the corresponding second metal pedestal 303 through windows 305 and 306 on passivation layer 308 On a major surface, a first type of confinement layer of semiconductor epitaxial film 304 is electrically coupled to a first major surface of a second metal pedestal 303 of a corresponding packaged package. The patterned electrode includes: a portion 307a laminated on the exposed surface of the first type of confinement layer 304 in the window 305, a portion 30 7b laminated on the surface of the passivation layer 308, and a second metal laminated in the window 306 A portion 307c of the exposed first major surface of the pedestal 303.
[68] 然后， 分割封装管壳列阵为单个垂直结构半导体外延薄膜封装， 分割的方法包 括釆用激光切割或机械锯分割， 等。  [68] Then, the split package array is a single vertical structure semiconductor epitaxial film package, and the segmentation method includes laser cutting or mechanical saw segmentation, and the like.
[69] 图 4展示图形化电极的形状的多个具体实施例， 包括： 单线条， 多线条， 网格 ， 环， 螺旋， 多叉， 等， 使电流分布更均匀和遮档更少的光。  4 shows various embodiments of the shape of the patterned electrode, including: single lines, multiple lines, grids, rings, spirals, multiple forks, etc., to make the current distribution more uniform and less occluded light .
[70] 图 4a展示图形化电极的单线条形状： 单线条形状的图形化电极 407层叠在沿半 导体外延薄膜 404的长轴方向上并与第二金属基座 403的第一主表面电联接， 半 导体外延薄膜 404层叠在第一金属基座 402上。 [70] Figure 4a shows the single line shape of the patterned electrode: a single line shaped patterned electrode 407 is layered along the half The conductor epitaxial film 404 is electrically coupled to the first main surface of the second metal pedestal 403 in the long-axis direction, and the semiconductor epitaxial film 404 is laminated on the first metal pedestal 402.
[71] 注意： 这种形状的半导体外延薄膜和单线条形状的图形化电极特别适合于侧发 光光源。 [71] Note: This type of semiconductor epitaxial film and single-line shaped patterned electrode are particularly suitable for side-emitting light sources.
[72] 图 4b展示图形化电极的单线条形状的另一具体实施例： 单线条形状的图形化电 极 417层叠在沿半导体外延薄膜 414的长轴方向上并向两端延伸而与第二金属基 座 413的第一主表面在两处电联接， 半导体外延薄膜 414层叠在第一金属基座 412 上。 第二金属基座 413呈门形。  [72] FIG. 4b shows another embodiment of the single line shape of the patterned electrode: a single line shaped patterned electrode 417 is laminated along the long axis direction of the semiconductor epitaxial film 414 and extends to both ends to the second metal. The first major surface of the pedestal 413 is electrically coupled at two locations, and a semiconductor epitaxial film 414 is laminated on the first metal pedestal 412. The second metal base 413 has a gate shape.
[73] 图 4c展示图形化电极的互相联接的多线条形状： 互相联接的多线条形状的图形 化电极 427层叠在沿半导体外延薄膜 424的长轴方向上并与第二金属基座 423的第 一主表面电联接， 半导体外延薄膜 424层叠在第一金属基座 422上。 4c shows a multi-line shape in which the patterned electrodes are coupled to each other: the interconnected multi-line shaped patterned electrodes 427 are laminated on the long axis direction of the semiconductor epitaxial film 424 and the second metal base 423 A main surface is electrically coupled, and a semiconductor epitaxial film 424 is laminated on the first metal base 422.
[74] 图 4a、 图 4b和图 4c包括图形化沟槽 4013、 4113和 4213。 [74] Figures 4a, 4b, and 4c include patterned trenches 4013, 4113, and 4213.
[75] 图 2a展示图形化电极的互相不联接的多线条形状的另一具体实施例。 Figure 2a shows another embodiment of a multi-line shape in which the patterned electrodes are not coupled to each other.
[76] 图 4d、 图 4e、 图 4f和图 4g展示图形化电极的网格形状： 网格形状的图形化电极 437、 447、 457和 467分别层叠在半导体外延薄膜 434、 444、 454和 464上并分别 与第二金属基座 433、 443、 453和 463的第一主表面电联接， 半导体外延薄膜 434 、 444、 454和 464分别层叠在第一金属基座 432、 442、 452和 462的第一主表面上 。 图形化沟槽 4313、 4413、 4513和 4613分别形成在图形化电极 437、 447、 457和 467的平行部分之间。 4d, 4e, 4f, and 4g show the grid shape of the patterned electrode: grid-shaped patterned electrodes 437, 447, 457, and 467 are laminated on the semiconductor epitaxial films 434, 444, 454, and 464, respectively. And electrically coupled to the first main surfaces of the second metal pedestals 433, 443, 453, and 463, respectively, and the semiconductor epitaxial films 434, 444, 454, and 464 are laminated on the first metal pedestals 432, 442, 452, and 462, respectively. On the first major surface. Patterned trenches 4313, 4413, 4513, and 4613 are formed between the parallel portions of patterned electrodes 437, 447, 457, and 467, respectively.
[77] 图 4h和图 4j展示图形化电极的环形状： 环形状的图形化电极 477和 487分别层叠 在半导体外延薄膜 474和 484上并分别与第二金属基座 473和 483的第一主表面电 联接， 半导体外延薄膜 474和 484分别层叠在第一金属基座 472和 482的第一主表 面上。 环形状的图形化电极可以是单环或互相联接的多环。 4h and 4j show the ring shape of the patterned electrode: ring-shaped patterned electrodes 477 and 487 are laminated on the semiconductor epitaxial films 474 and 484 , respectively, and the first mains of the second metal pedestals 473 and 483 , respectively. Surface electrical connections, semiconductor epitaxial films 474 and 484 are laminated on the first major surfaces of first metal pedestals 472 and 482, respectively. The ring-shaped patterned electrodes may be single-ring or multi-rings that are coupled to each other.
[78] 图 4k和图 4m展示图形化电极的螺旋形状： 螺旋形状的图形化电极 497和 4107分 别层叠在半导体外延薄膜 494和 4104上并分别与第二金属基座 493和 4103的第一 主表面电联接， 半导体外延薄膜 494和 4104分别层叠在第一金属基座 492和 4102 的第一主表面上。 4k and 4m show the spiral shape of the patterned electrode: The spiral shaped patterned electrodes 497 and 4107 are laminated on the semiconductor epitaxial films 494 and 4104, respectively, and respectively associated with the first mains of the second metal pedestals 493 and 4103. Surface electrical connections, semiconductor epitaxial films 494 and 4104 are laminated on the first major surfaces of the first metal pedestals 492 and 4102, respectively.
[79] 图 4η和图 4p展示图形化电极的叉形状： 叉形状的图形化电极 4207和 4307分别层 叠在半导体外延薄膜 4204和 4304上并分别与第二金属基座 4203和 4303的第一主 表面电联接， 半导体外延薄膜 4204和 4304分别层叠在第一金属基座 4202和 4302 的第一主表面上。 叉形状的图形化电极包括： 单叉或互相联接的多叉。 [79] FIG. 4n and FIG. 4p show the fork shape of the patterned electrode: the fork-shaped patterned electrodes 4207 and 4307 are respectively layered Overlying the semiconductor epitaxial films 4204 and 4304 and electrically coupled to the first major surfaces of the second metal pedestals 4203 and 4303, respectively, the semiconductor epitaxial films 4204 and 4304 are laminated on the first major surfaces of the first metal pedestals 4202 and 4302, respectively. on. The fork-shaped patterned electrode includes: a single fork or a multi-fork that is coupled to each other.
[80] 为简化画图， 图 4k、 图 4m、 图 4η和图 4p没有展示图形化沟槽。 [80] To simplify the drawing, Figure 4k, Figure 4m, Figure 4n and Figure 4p do not show graphical grooves.
[81] 图 4q展示图形化电极的另一多线条形状： 多线条形状的图形化电极 4407层叠在 半导体外延薄膜 4404上并与第二金属基座 4403的第一主表面电联接， 半导体外 延薄膜 4404层叠在第一金属基座 4402上。 沟槽 4413形成在图形化电极 4407的平 行部分之间。 Figure 4q shows another multi-line shape of the patterned electrode: a multi-line shaped patterned electrode 4407 is laminated on the semiconductor epitaxial film 4404 and electrically coupled to the first major surface of the second metal pedestal 4403, the semiconductor epitaxial film 4404 is laminated on the first metal base 4402. A trench 4413 is formed between the parallel portions of the patterned electrode 4407.
[82] 图 5展示一半导体外延薄膜封装的沟槽的一个具体实施例的顶视图。 半导体外 延薄膜封装包括： 绝缘支架 501， 第一金属基座 502， 第二金属基座 503， 半导体 外延薄膜 504层叠在第一金属基座 502上， 图形化的电极 507层叠在半导体外延薄 膜的上方的预定的位置上的窗口 505和第二金属基座的第一主表面的上方的预定 的位置上的窗口 506中。 图 5中没有画出钝化层。 沟槽 513形成在图形化电极 4407 的之间。 Figure 5 shows a top view of one embodiment of a trench of a semiconductor epitaxial film package. The semiconductor epitaxial film package comprises: an insulating holder 501, a first metal base 502, a second metal base 503, a semiconductor epitaxial film 504 laminated on the first metal base 502, and a patterned electrode 507 laminated on the semiconductor epitaxial film The predetermined position is on the window 505 and the window 506 on the predetermined position above the first major surface of the second metal base. A passivation layer is not shown in FIG. A trench 513 is formed between the patterned electrodes 4407.
[83] 图 6a展示半导体外延薄膜封装的一个具体实施例的顶视图。 半导体外延薄膜封 装包括： 绝缘支架 601， 一个第一金属基座 602， 八个第二金属基座 603a到 603h， 八个半导体外延薄膜 604共同层叠在第一金属基座 602上， 八个图形化的电极 607 分别层叠在八个半导体外延薄膜上和对应的八个第二金属基座的第一主表面上 。 图 6a中没有画出钝化层和窗口。 当半导体外延薄膜 604的表面的第一类型限制 层是 N类型限制层吋， 八个半导体外延薄膜 604被共阳极控制电路供电。 Figure 6a shows a top view of one embodiment of a semiconductor epitaxial film package. The semiconductor epitaxial film package comprises: an insulating bracket 601, a first metal base 602, eight second metal bases 603a to 603h, and eight semiconductor epitaxial films 604 are stacked on the first metal base 602, eight patterned The electrodes 607 are laminated on the eight semiconductor epitaxial films and the first major surfaces of the corresponding eight second metal pedestals, respectively. Passivation layers and windows are not shown in Figure 6a. When the first type of confinement layer of the surface of the semiconductor epitaxial film 604 is an N type confinement layer, the eight semiconductor epitaxial films 604 are powered by the common anode control circuit.
[84] 图 6b展示半导体外延薄膜封装的一个具体实施例的顶视图。 半导体外延薄膜封 装包括： 绝缘支架 611， 六个第一金属基座 612a到 612f， 一个门形第二金属基座 6 13， 六个半导体外延薄膜 614分别层叠在六个第一金属基座 612上， 六个图形化 的电极 617分别层叠在六个半导体外延薄膜 614上和一个第二金属基座 613的第一 主表面上。 图 6b中没有画出钝化层和窗口。 当半导体外延薄膜 614的表面的第一 类型限制层是 N类型限制层吋， 六个半导体外延薄膜 614被共阴极控制电路供电  Figure 6b shows a top view of one embodiment of a semiconductor epitaxial film package. The semiconductor epitaxial film package comprises: an insulating holder 611, six first metal bases 612a to 612f, a gate-shaped second metal base 6 13, and six semiconductor epitaxial films 614 stacked on the six first metal bases 612, respectively. Six patterned electrodes 617 are stacked on the six semiconductor epitaxial films 614 and on the first major surface of a second metal pedestal 613, respectively. Passivation layers and windows are not shown in Figure 6b. When the first type of confinement layer of the surface of the semiconductor epitaxial film 614 is an N type confinement layer, the six semiconductor epitaxial films 614 are powered by the common cathode control circuit.
[85] 注意： 图 6a和图 6b中的半导体外延薄膜， 第一金属基座， 和第二金属基座的数 量可以是多个。 可以在钝化层和 /或第一类型限制层中形成沟槽。 [85] Note: The number of semiconductor epitaxial films, the first metal pedestal, and the second metal pedestal in Figures 6a and 6b The amount can be multiple. A trench may be formed in the passivation layer and/or the first type of confinement layer.
[86] 上面的具体的描述并不限制本发明的范围， 而只是提供一些本发明的具体化的 例证。 因此本发明的涵盖范围应该由权利要求和它们的合法等同物决定， 而不是由上述具体化的详细描述和实施实例决定。  The above specific description does not limit the scope of the invention, but merely provides some examples of the invention. The scope of the invention should be determined by the claims and their legal equivalents, rather than the detailed description and the embodiments.

Claims

权利要求书 Claim
[1] 一种封装管壳， 其特征在于， 所述的封装管壳包括： 至少一个第一金属基 座， 至少一个第二金属基座和绝缘支架； 所述的第一金属基座和第二金属 基座分别包括第一主表面和第二主表面； 所述的绝缘支架包括第一主表面 和第二主表面； 所述的绝缘支架的第一主表面和第二主表面分别与所述的 第一金属基座和第二金属基座的第一主表面和第二主表面有相同的方向； 所述的封装管壳包括第一主表面和第二主表面； 所述的封装管壳的第一主 表面和第二主表面分别由所述的第一金属基座、 第二金属基座和绝缘支架 的第一主表面和第二主表面构成； 所述的绝缘支架的第一主表面与第一金 属基座和第二金属基座的第一主表面基本在同一平面； 所述的第一金属基 座和第二金属基座互相电绝缘， 所述的第一金属基座和第二金属基座将分 别与外界电源的两个电极电联接； 所述的绝缘支架把所述的第一和第二金 属基座固定在预定的位置。  [1] A package package, the package case comprising: at least one first metal base, at least one second metal base and an insulating support; the first metal base and the first The two metal bases respectively include a first main surface and a second main surface; the insulating bracket includes a first main surface and a second main surface; the first main surface and the second main surface of the insulating bracket are respectively The first main surface and the second main surface of the first metal base and the second metal base have the same direction; the packaged tube case includes a first main surface and a second main surface; The first major surface and the second major surface of the shell are respectively composed of the first metal base, the second metal base and the first main surface and the second main surface of the insulating bracket; the first of the insulating brackets The main surface is substantially in the same plane as the first main surface of the first metal base and the second metal base; the first metal base and the second metal base are electrically insulated from each other, the first metal base And the second metal base will be separately from the outside world Two electrodes coupled to the source; said first and second insulating holder base metal fixed at a predetermined position according to.
[2] 一种垂直结构半导体外延薄膜封装， 其特征在于， 所述的垂直结构半导体 外延薄膜封装包括：  [2] A vertical structure semiconductor epitaxial thin film package, wherein the vertical structure semiconductor epitaxial film package comprises:
*一个封装管壳； 其中， 所述的封装管壳包括： 至少一个第一金属基座， 至 少一个第二金属基座和绝缘支架； 所述的第一金属基座和第二金属基座分 别包括第一主表面和第二主表面； 所述的绝缘支架包括第一主表面和第二 主表面； 所述的绝缘支架的第一主表面和第二主表面分别与所述的第一金 属基座和第二金属基座的第一主表面和第二主表面有相同的方向； 所述的 封装管壳包括第一主表面和第二主表面； 所述的封装管壳的第一主表面和 第二主表面分别由所述的第一金属基座、 第二金属基座和绝缘支架的第一 主表面和第二主表面构成； 所述的第一金属基座和第二金属基座互相电绝 缘， 所述的第一金属基座和第二金属基座将分别与外界电源的两个电极电 联接； 所述的绝缘支架把所述的第一和第二金属基座固定在预定的位置； *至少一个半导体外延薄膜； 所述的半导体外延薄膜包括： 第一类型限制层 a packaged package; wherein the packaged package comprises: at least one first metal base, at least one second metal base and an insulating support; the first metal base and the second metal base respectively The first main surface and the second main surface are included; the insulating bracket includes a first main surface and a second main surface; the first main surface and the second main surface of the insulating bracket are respectively associated with the first metal The first main surface and the second main surface of the base and the second metal base have the same direction; the packaged tube case includes a first main surface and a second main surface; the first main body of the packaged tube case The surface and the second major surface are respectively composed of the first main surface and the second main surface of the first metal base, the second metal base and the insulating bracket; the first metal base and the second metal base The sockets are electrically insulated from each other, and the first metal base and the second metal base are respectively electrically coupled to the two electrodes of the external power source; the insulating bracket fixes the first and second metal bases at Pre-determined location; * at least one and a half a conductor epitaxial film; the semiconductor epitaxial film comprises: a first type of confinement layer
， 活化层和第二类型限制层； 所述的活化层层叠在所述的第一类型限制层 和所述的第二类型限制层之间； *导电反射 /欧姆 /键合层； 所述的导电反射 /欧姆 /键合层层叠在所述的半导 体外延薄膜的第二类型限制层与所述的第一金属基座的第一主表面之间。An activation layer and a second type of restriction layer; the activation layer being laminated between the first type of restriction layer and the second type of restriction layer; * a conductive reflective / ohmic / bonding layer; said conductive reflective / ohmic / bonding layer is laminated on the second type of confinement layer of the semiconductor epitaxial film and the first main surface of the first metal pedestal between.
*一个钝化层； 所述的钝化层层叠在所述的封装管壳的第一主表面和所述的 半导体外延薄膜的第一类型限制层上； 所述的钝化层在所述的半导体外延 薄膜的第一类型限制层的上方和所述的对应的第二金属基座的第一主表面 的上方的预定的位置上具有窗口； a passivation layer; the passivation layer is laminated on the first main surface of the packaged envelope and the first type of confinement layer of the semiconductor epitaxial film; the passivation layer is in the a window having a predetermined position above the first type of confinement layer of the semiconductor epitaxial film and above the first main surface of the corresponding second metal pedestal;
*图形化的电极； 其中， 所述的图形化的电极通过所述的钝化层在所述的半 导体外延薄膜的第一类型限制层上的窗口， 层叠在所述的半导体外延薄膜 的第一类型限制层上， 并向所述的对应的第二金属基座的第一主表面延伸 a patterned electrode; wherein the patterned electrode is laminated on the first epitaxial film of the semiconductor epitaxial film through a window of the passivation layer on the first type of confinement layer of the semiconductor epitaxial film a type limiting layer and extending toward the first major surface of the corresponding second metal base
， 通过所述的钝化层在所述的对应的第二金属基座的第一主表面的窗口， 层叠在所述的对应的第二金属基座的第一主表面上， 使得所述的半导体外 延薄膜的第一类型限制层通过所述的图形化电极与所述的对应的第二金属 基座电联接。 And a window of the first main surface of the corresponding second metal base is laminated on the first main surface of the corresponding second metal base by the passivation layer, so that the A first type of confinement layer of the semiconductor epitaxial film is electrically coupled to the corresponding second metal pedestal by the patterned electrode.
[3] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的半导体外 延薄膜的材料是从一组材料中选出， 该组材料包括： （1) 氮化镓基材料， 即， 元素镓、 铝、 铟、 氮等的二元系、 三元系和四元系材料； 所述的氮化 镓基的二元系、 三元系和四元系材料包括， GaN, AlGaN， GalnN,  [3] The vertical structure semiconductor epitaxial film package of claim 2, wherein the material of the semiconductor epitaxial film is selected from the group consisting of: (1) a gallium nitride based material, ie a binary, ternary, and quaternary material of the elements gallium, aluminum, indium, nitrogen, etc.; the gallium nitride-based binary, ternary, and quaternary materials including GaN, AlGaN, GalnN,
AlGalnN; 所述的氮化镓基外延层的晶体平面包括： c-平面， a-平面， m-平 面； （2) 磷化镓基材料， 即， 元素镓、 铝、 铟、 磷的二元系， 三元系和四 元系材料； 所述的磷化镓基的二元系、 三元系和四元系材料包括， GaP， A IGaP, GalnP, AlGalnP; (3) 镓氮磷基材料， 即， 元素镓、 铝、 铟、 氮、 磷等的二元系、 三元系、 四元系和五元系材料； 所述的镓氮磷的二元系、 三元系、 四元系和五元系材料包括， GaNP, AlGaNP， GalnNP, AlGalnNP; (4) 氧化锌基材料， 包括， ZnO; 所述的半导体外延薄膜的 活化层的结构是从一组结构中选出， 该组结构包括： 体， 单量子阱， 多量 子阱， 量子点， 量子线。  AlGalnN; the crystal plane of the gallium nitride-based epitaxial layer comprises: c-plane, a-plane, m-plane; (2) gallium phosphide-based material, ie, elemental gallium, aluminum, indium, phosphorus binary System, ternary and quaternary materials; the gallium phosphide-based binary, ternary and quaternary materials include GaP, A IGaP, GalnP, AlGalnP; (3) gallium phosphide-based materials , that is, binary, ternary, quaternary, and quaternary materials of the elements gallium, aluminum, indium, nitrogen, phosphorus, etc.; the binary, ternary, and quaternary systems of gallium, phosphorus, and phosphorus And pentad materials include GaNP, AlGaNP, GalnNP, AlGalnNP; (4) zinc oxide-based materials, including ZnO; the structure of the active layer of the semiconductor epitaxial film is selected from a group of structures, the group structure Including: bulk, single quantum well, multiple quantum wells, quantum dots, quantum wires.
[4] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的半导体外 延薄膜的第一类型限制层的表面和 /或钝化层的表面被粗化或形成光子晶体 结构以便提高光取出效率。 [4] The vertical structure semiconductor epitaxial thin film package of claim 2, wherein a surface of the first type of confinement layer of the semiconductor epitaxial film and/or a surface of the passivation layer is roughened or a photonic crystal is formed Structure to improve light extraction efficiency.
[5] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的半导体外 延薄膜的第一类型限制层和 /或钝化层被蚀刻出图形化的沟槽以便提高光取 出效率。 [5] The vertical structure semiconductor epitaxial thin film package of claim 2, wherein the first type of confinement layer and/or passivation layer of the semiconductor epitaxial film is etched into a patterned trench to improve light extraction efficiency.
[6] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的半导体外 延薄膜的第一类型限制层是 N类型限制层； 所述的半导体外延薄膜进一步 包括一个 N+/N++类型限制层； 所述的 N+/N++类型限制层层叠在所述的 N类 型限制层和活化层之间； 所述的图形化的电极的底部层叠在所述的 N+/N++ 类型限制层上。  [6] The vertical structure semiconductor epitaxial thin film package of claim 2, wherein the first type of confinement layer of the semiconductor epitaxial film is an N type confinement layer; and the semiconductor epitaxial film further comprises an N+/N++ type restriction The N+/N++ type confinement layer is laminated between the N type confinement layer and the activation layer; and the bottom of the patterned electrode is laminated on the N+/N++ type confinement layer.
[7] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的绝缘支架 的材料包括： 绝缘注塑材料， 陶瓷； 所述的陶瓷包括氮化铝， 氧化铝。  [7] The vertical structure semiconductor epitaxial film package of claim 2, wherein the material of the insulating holder comprises: an insulating injection molding material, ceramic; and the ceramic comprises aluminum nitride, aluminum oxide.
[8] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的导电反射  [8] The vertical structure semiconductor epitaxial thin film package of claim 2, wherein said conductive reflection
/欧姆 /键合层具有多层结构； 每层的材料是从一组材料中选出， 该组材料包 括： 分布布喇格反射层， 金属铝， 银， 金， 锡， 镍， 铬， 钛， 铍， 及所述 的金属的合金； 所述的金属的合金包括金锡， 银锡， 金铍。  / Ohm / bonding layer has a multi-layer structure; each layer of material is selected from a group of materials, including: distributed Bragg reflector, aluminum, silver, gold, tin, nickel, chromium, titanium , 铍, and the alloy of the metal; the alloy of the metal includes gold tin, silver tin, gold ruthenium.
[9] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的钝化层具 有单层或多层结构； 每层的材料是从一组材料中选出， 该组材料包括： 透 明的绝缘的氧化物和透明的绝缘的氮化物； 所述的氧化物包括： 氧化硅， 氧化铝， 氧化锌； 所述的氮化物包括： 氮化硅。  [9] The vertical structure semiconductor epitaxial thin film package of claim 2, wherein the passivation layer has a single layer or a multilayer structure; the material of each layer is selected from a group of materials, the set of materials comprising: a transparent insulating oxide and a transparent insulating nitride; the oxide comprises: silicon oxide, aluminum oxide, zinc oxide; and the nitride comprises: silicon nitride.
[10] 权利要求 2的垂直结构半导体外延薄膜封装， 其特征在于， 所述的图形化的 电极的形状包括单线条， 多线条， 网格， 多环， 螺旋， 多叉； 所述的图形 化的电极的形状使得电流分布基本上没有电流拥塞现象。  [10] The vertical structure semiconductor epitaxial film package of claim 2, wherein the shape of the patterned electrode comprises a single line, a multi-line, a grid, a multi-ring, a spiral, a multi-fork; The shape of the electrodes is such that the current distribution is substantially free of current congestion.
[11] 一种制造垂直结构半导体外延薄膜封装的工艺方法， 其特征在于， 所述的 工艺步骤包括：  [11] A process for fabricating a vertical structure semiconductor epitaxial thin film package, characterized in that the process steps include:
(1) 提供封装管壳列阵和半导体芯片； 所述的封装管壳列阵包括至少一个 封装管壳； 每个封装管壳包括： 至少一个第一金属基座， 至少一个第二金 属基座和绝缘支架；  (1) providing a packaged package array and a semiconductor chip; the packaged package array comprising at least one packaged package; each packaged package comprising: at least one first metal pedestal, at least one second metal pedestal And insulating brackets;
(2) 倒装焊每一个半导体芯片到每个封装管壳上的对应的第一金属基座的 第一主表面上； (2) flip-chip bonding each semiconductor chip to a corresponding first metal pedestal on each packaged package On the first major surface;
(3) 剥离半导体芯片的生长衬底和缓冲层， 直到半导体外延层第一类型限 制层暴露；  (3) stripping the growth substrate and the buffer layer of the semiconductor chip until the first type of limiting layer of the semiconductor epitaxial layer is exposed;
(4) 层叠钝化层在封装管壳列阵的每一个封装管壳上；  (4) laminating a passivation layer on each of the packaged packages of the packaged package array;
(5) 在预定的位置， 蚀刻钝化层， 在半导体外延薄膜的第一类型限制层的 表面和对应的第二金属基座的第一主表面上的预定的位置形成窗口；  (5) etching the passivation layer at a predetermined position to form a window at a predetermined position on the surface of the first type of confinement layer of the semiconductor epitaxial film and the first main surface of the corresponding second metal pedestal;
(6) 通过钝化层上的窗口， 层叠图形化的电极使得半导体外延薄膜的第一 类型限制层和对应的封装管壳的第二金属基座电联接；  (6) by patterning the electrodes on the passivation layer, electrically interconnecting the first type of limiting layer of the semiconductor epitaxial film and the second metal base of the corresponding packaged tube;
(8) 分割封装管壳列阵为单个垂直结构半导体外延薄膜封装。  (8) The split package package array is a single vertical structure semiconductor epitaxial film package.
权利要求 11的制造垂直结构半导体外延薄膜封装的工艺方法， 其特征在于 ， 所述的工艺方法进一步包括， 粗化所述的半导体外延薄膜的第一类型限 制层的表面或在第一类型限制层的表面上形成光子晶体结构； 粗化所述的 钝化层的表面或在钝化层的表面上形成光子晶体结构； 在半导体外延薄膜 的第一类型限制层上蚀刻出图形化的沟槽； 在钝化层中蚀刻出图形化的沟 槽。 A method of fabricating a vertical structure semiconductor epitaxial thin film package according to claim 11, wherein said process further comprises: roughening a surface of said first type of confinement layer of said semiconductor epitaxial film or a first type of confinement layer Forming a photonic crystal structure on the surface; roughening the surface of the passivation layer or forming a photonic crystal structure on the surface of the passivation layer; etching a patterned trench on the first type of confinement layer of the semiconductor epitaxial film; A patterned trench is etched into the passivation layer.
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