WO2009114680A3 - Cross-coupled transistor layouts in restricted gate level layout architecture - Google Patents

Cross-coupled transistor layouts in restricted gate level layout architecture Download PDF

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Publication number
WO2009114680A3
WO2009114680A3 PCT/US2009/036937 US2009036937W WO2009114680A3 WO 2009114680 A3 WO2009114680 A3 WO 2009114680A3 US 2009036937 W US2009036937 W US 2009036937W WO 2009114680 A3 WO2009114680 A3 WO 2009114680A3
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Prior art keywords
channel transistor
gate electrode
gate
cross
gate level
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PCT/US2009/036937
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French (fr)
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WO2009114680A2 (en
Inventor
Scott T. Becker
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Tela Innovations, Inc.
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Application filed by Tela Innovations, Inc. filed Critical Tela Innovations, Inc.
Priority to JP2010550861A priority Critical patent/JP5628050B2/en
Publication of WO2009114680A2 publication Critical patent/WO2009114680A2/en
Publication of WO2009114680A3 publication Critical patent/WO2009114680A3/en

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Abstract

A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.
PCT/US2009/036937 2008-03-13 2009-03-12 Cross-coupled transistor layouts in restricted gate level layout architecture WO2009114680A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010550861A JP5628050B2 (en) 2008-03-13 2009-03-12 Cross-coupled transistor layout in constrained gate level layout architecture

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US3646008P 2008-03-13 2008-03-13
US61/036,460 2008-03-13
US4270908P 2008-04-04 2008-04-04
US61/042,709 2008-04-04
US4595308P 2008-04-17 2008-04-17
US61/045,953 2008-04-17
US5013608P 2008-05-02 2008-05-02
US61/050,136 2008-05-02
US12/402,465 US7956421B2 (en) 2008-03-13 2009-03-11 Cross-coupled transistor layouts in restricted gate level layout architecture
US12/402,465 2009-03-11

Publications (2)

Publication Number Publication Date
WO2009114680A2 WO2009114680A2 (en) 2009-09-17
WO2009114680A3 true WO2009114680A3 (en) 2009-12-17

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PCT/US2009/036937 WO2009114680A2 (en) 2008-03-13 2009-03-12 Cross-coupled transistor layouts in restricted gate level layout architecture

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US (52) US7956421B2 (en)
JP (7) JP5628050B2 (en)
MY (2) MY170141A (en)
SG (2) SG189680A1 (en)
TW (5) TW201735325A (en)
WO (1) WO2009114680A2 (en)

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