WO2009114974A1 - General field bus receiver and receiving method thereof - Google Patents

General field bus receiver and receiving method thereof Download PDF

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Publication number
WO2009114974A1
WO2009114974A1 PCT/CN2008/071905 CN2008071905W WO2009114974A1 WO 2009114974 A1 WO2009114974 A1 WO 2009114974A1 CN 2008071905 W CN2008071905 W CN 2008071905W WO 2009114974 A1 WO2009114974 A1 WO 2009114974A1
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WIPO (PCT)
Prior art keywords
data
array
dual
tcam
bit
Prior art date
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PCT/CN2008/071905
Other languages
French (fr)
Inventor
Haibin Yu
Xiaoning Xin
Zhijia Yang
Zhipeng Zhang
Yan Lv
Original Assignee
Shenyang Institute Of Automation Of The Chinese Academy Of Sciences
XIE, Chuang
Cui, Shuping
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Application filed by Shenyang Institute Of Automation Of The Chinese Academy Of Sciences, XIE, Chuang, Cui, Shuping filed Critical Shenyang Institute Of Automation Of The Chinese Academy Of Sciences
Publication of WO2009114974A1 publication Critical patent/WO2009114974A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7453—Address table lookup; Address filtering using hashing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40221—Profibus

Definitions

  • the present invention relates to a technology for a Field Bus control, particularly a general Field Bus receiver based on ternary content addressable memory(TCAM) and receiving method thereof.
  • TCAM ternary content addressable memory
  • Communication controller chip is one of the most important devices of the Field Bus system, which is used to encode and uncode the data on the bus.
  • Field Bus protocols There are many types of Field Bus protocols in the international standard IEC61158 at present.
  • the Manchester code is used in many protocols, however the format and the definitions of preamb ⁇ start-delimiter end-delimiter of the Physical layer protocol are different from each other, the business Field Bus receiver is recently based on the traditional logic circuit, which commonly can only be used for receiving just one type of the protocols.
  • the Field Bus protocols the market share of single communication protocol chip is small and the cost rate of the whole system is on a high side.
  • the major difference of the various hardware Field Bus systems is the communication controller, the key part of which is Manchester code receiving cicuit. In case the circuit is general for various protocols, general Field Bus controller and System on a chip(SOC) can be realized.
  • the purpose of the invention is to provide a programmable receiving method and receiver based on ternary content addressable memohs(TCAM) for all the Field Bus protocols using Manchester code, by receiving the correspongding Field Bus protocols data according to the various data written into the RAM array.
  • TCAM ternary content addressable memohs
  • the technical scheme of the invention is : the programmable state mechanism, which is in stead of the traditional fixed function state mechanism combined by the logic gate circuit, is created through the priority management circuit by combining the TCAM array, functioning to distinguish whether or not the received data being in accordance with the special symbol defined by the expected principle of the protocol, with dual-RAM array being for preserving the corresponding state signal and control signal.
  • the receiving method of the general Field Bus based on the Manchester code is: to create the programmable state mechanism through the priority management circuit by combining the dual-TCAM array with dual-RAM array, for distinguishing the Mancheset code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using "don't care" logic function of TCAM, and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to recive the general Field Bus protocol based on the Manchester code.
  • the method of detecting and distinguishing the Manchester code is those that of decoding the data from the input register to the 2-bit to 4-bit, configuring the input lines of the dual-TCAM array to meet requirement of the Manchester code according to a mode of the dual-TCAM array, and transmiting the register data from the input of the TCAM array to its output for functioning to detect and distinguish the Manchester code, only if the register data of every neighboring bits output from the 2-bit to 4-bit is different which satisfies the requirement of the Manchester code.
  • a bit synchronization circuit which is used to make the serial input data bit synchronize according to the designated communication protocol configuration, for creating valid data sampling information
  • a sample generating circuit which is used to receive the valid data sampling information from the bit synchronization circuit, generates two output signals according to the specified communication protocol configuration, wherein one output signal is as the data that already sampled used to be a shift register data. Another output signal provides the number of the receiving data pulses to a bit counting controller; while one shift register data is generated, one pulse signal is generated.
  • a polarity rectification circuit which is used to judge the polarity of the serial data according to the specified communication protocol configuration, rectify the polarity and then import the polarity rectification information for shift registering.
  • the shift register which is used to transform the serial input data already sampled to the parallel data according to the polarity rectification information.
  • the input register which is used to buffer the parallel data in the shift register on the control of timing.
  • the bit counting controller which is used to receive the pulse signal generated by the sample generating circuit (one shift register data is generated, while one pulse signal is generated by the sample generating circuit), and independently count the data bits imported to the shift register on time according to the receiving data bit number of the specified communication protocol configuration; generate a start-up signal of the sequential controller and the control signal of the specified communication protocol after the received data number reaching the specified communication protocol configuration.
  • a sequential control circuit which is used to generate the configuration information correspond to the specified communication protocol, according to the control signal of the specified communication protocol generated by the bit counting controller, and import the configuration information in correspondence with the specified communication protocol to the input register and the state register, generate the sequential control signal in correspondence with the specified communication protocol, at the same time.
  • the programmable state mechanism which is composed of the TCAM array, the priority management circuit and the dual-RAM array.
  • the TCAM array is used to actualize matching calculation of the received parallel data from the input register with the expected principle of the protocol in time sequential controlling, i.
  • the dual- RAM array receives the valid data of the legal matching data is imported as the "word" line passed by the TCAM array through the priority management circuit after distinguishing the parallel data from the input register whether the special symbol is specified by the protocol;
  • the input of the priority management circuit connects with the output of the TCAM array for confirming the only one valid output while many legal matching data output from the TCAM array, and an output of the priority management circuit connects with the "word” line of the dual-RAM array;
  • the dual-RAM array stores the programmable state signal corresponding to the TCAM array and the programmable control signal applying the data path circuit(such as the bit synchronization circuit, the sample generating cicuit, the polarity rectification circuit, the bit counting controller), which both are from peripheral CPU;
  • the input of the priority management circuit is the valid data from the TCAM array as the "word” line input of the dual-RAM array;
  • the output data on the "bit" line of the dual-RAM array is as the zone state information of the TCAM array at the
  • the state register which is used to feed back the state information of the dual- RAM array to the TCAM array, and decide the information recently expected to receive in time sequential controlling.
  • An output register which is used to receive the state information from the dual- RAM array, being specified communication protocol configuration as the control signal having three ways to go: to the bit counting controller being for the the receiving data bit number, to drive the bit synchronization circuit for confirming steps of the receiving serial protocol data , to the polarity rectification circuit for judging the polarity , and to the sample generating circuit for actualizing the function which is the content of the programmable state mechanism for terminating the number of the required receiving data.
  • the matching calculation of the received data with the expected principle of the protocol adopts "NOR-type” or "NAND-type” TCAM array.
  • the "dual-TCAM” cell comprises eight MOS transistors dividing into four groups parallely connected by each group having two MOS transistors serial connected to form a comparing circuit.
  • the preserving data extremities of four SRAM cells respectively control one gate of the two MOS transistors in each group
  • the input signals respectively control another gate of the two MOS transistors in the same group
  • one idle extremity of the one of the two MOS transistors in each group see connects ⁇ €l together as an output idle extremity
  • another idle extremity of the two MOS transistors in the same group connects together as an input idle extremity.
  • the content of the four SRAM provides the expected receiving data.
  • the "dual-TCAM" array is composed of the dual-TCAMs and 2-bit to 4-bit decoders;
  • the every two neighboring lines of the 2-bit to 4-bit decoder receives singnals from the input register for decoding, and 4 output lines of the decoder are as searching lines of a column cells;
  • the dual-TCAMs in each row are serial connected by a matching line.
  • the invention has the following advantages: 1.
  • the present invention being general for various protocols based on the Manchester code can be applied to verious protocols as the central part of the communication controller .
  • the general Field Bus communication controller chip and SOC can be designed by using this invention.
  • Various content is likely written to the receiver provided by the present invention for various Field Bus protocols to meet requirements of the protocols since the TCAM and dual-RAM are both programmable, and the content of which canbe written by the peripheral CPU.
  • the present invention has a larger market and lower design cost as it is applicable for various communication protocol.
  • the communication controller and SOC based on the Manchester code have the far-ranging using foreground and commercial worth.
  • FIG.1 is a block diagram illustrating Protocol Data Receiver in accordance with the embodiment of the invention.
  • FIG.2 is a structural drawing illustrating the first SRAM cell in accordance with the embodiment of the invention.
  • FIG.3(a) is a structural drawing illustrating the NOR-type1 TCAM.
  • FIG.3(b) is a structural drawing illustrating the NOR-type 2 TCAM.
  • FIG.4 is a structural drawing illustrating the NOR-type TCAM array.
  • FIG.5(a) is a structural drawing illustrating the NAND-type1 TCAM.
  • FIG.5(b) is a structural drawing illustrating the NAND-type2 TCAM.
  • FIG.6 is a structural drawing illustrating the NAND-type TCAM array.
  • FIG.7(a) is a structural drawing illustrating the dual-TCAM cell in accordance with the embodiment of the invention.
  • FIG.7(b) is a block diagram illustrating the symbol of the dual-TCAM cell in accordance with the embodiment of the invention.
  • FIG.8 is a structural drawing illustrating the TCAM array in accordance with the embodiment of the invention.
  • FIG.9 is a structural drawing illustrating the priority management circuit in accordance with the embodiment of the invention.
  • FIG.10 is a structural drawing illustrating the dual-RAM array circuit in accordance with the embodiment of the invention.
  • the programmable state mechanism is composed of the dual-TCAM array and dual-RAM array based on ternary content addressable memohs(TCAM) instead of the trandition one which is composed by the logic circuit with the fixed function, distinguishing the Manchester code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using "don't care" logic function of TCAM(supporting the function of any logic lookup), and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to recive the general Field Bus protocol based on the Manchester code.
  • TCAM ternary content addressable memohs
  • a way of bring about the programmable state mechanism is that the TCAM array is in combination with dual-RAM array connected by the priority management circuit.
  • the programmable state mechanism After the CPU imports the input data to the RAM array initializing the information, the intervention of the CPU is not needed during the process of combination for the programmable state mechanism referenced above.
  • the programmable state mechanism When receiving some data which is definitely defined by the protocol, the programmable state mechanism then performs correct state transform and output the analytical result according to the content of the data. Because the TCAM array and dual-RAM array are both programmable, the programmable state mechanism is realizable.
  • the mothed of detecting and distinguishing the Manchester code is that of decoding the data in the input register to the 2-bit to 4-bit, configuring the input lines of the dual-TCAM array to meet requirement of the Manchester code according to a mode of the dual-TCAM array, and transmiting the register data from the input of the TCAM array to its output for functioning to detect and distinguish the Manchester code, only if the register data of every neighboring bits output from the 2-bit to 4-bit is differentwhich satisfies the requirement of the Manchester code.
  • the bit synchronization circuit which is used to make the serial input data bit synchronize according to the designated communication protocol configuration, and output valid data sampling information;
  • the sample generating circuit which is used to receive the valid data sampling information from the bit synchronization circuit, generates two output signals according to the specified communication protocol configuration, wherein one output signal is as the data that already sampled used to be a shift register data.Another output signal provides the number of the receiving data pulses to a bit counting controller; while one shift register data is generated, one pulse signal is generated.
  • the polarity rectification circuit which is used to judge the polarity of the serial data according to the specified communication protocol configuration, rectify the polarity and then import the polarity rectification information for shift registering.
  • the shift register which is used to transform the serial input data already sampled to the parallel data according to the polarity rectification information.
  • the input register which is used to buffer the parallel data in the shift register on the control of timing.
  • the bit counting controller which is used to receive the pulse signal generated by the sample generating circuit (while one shift register data is generated, one pulse signal is generated by the sample generating circuit), and independently count the data bits imported to the shift register on time according to the receiving data bit number of the specified communication protocol configuration; after the received data number reaches the specified communication protocol configuration, a fee start-up signal of the sequential controller and the control signal of the specified communication protocol are generated by the bit counting controller.
  • the sequential control circuit which is used to generate the configuration information correspond to the specified communication protocol, according to the control signal of the specified communication protocol generated by the bit counting controller, and import the configuration information in correspondence with the specified communication protocol to the input register and state register, at the same time, generate the sequential control signal in correspondence with the specified communication protocol.
  • the programmable state mechanism which is composed of by the TCAM array, the priority management circuit and the dual-RAM array.
  • the TCAM array is used to actualize matching calculation of the received parallel data from the input register with the expected principle of the protocol in time sequential controlling(including identifying the protocol information of the bus such as the start- delimiter, detecting invalid data(whether the data is Manchester code ) . i. e the valid data of the legal matching data is imported to the dual-RAM array as the "word" line passed by the TCAM array through the priority management circuit after distinguishing the parallel data from the input register whether the special symbol is specified by the protocol.
  • the input of the priority management circuit is connected with the output of the TCAM array for confirming the only one valid output while many legal matching data output from the TCAM array, and the output of the priority management circuit is connected with the "word" line of the dual-RAM array.
  • the dual-RAM array stores the programmable state signal corresponding the TCAM array and the programmable control signal corresponding the data path circuit(such as the bit synchronization circuit, the sample generating cicuit, the polarity rectification circuit, the bit counting controller), which both are imported by peripheral CPU.
  • the input of the priority management circuit is the valid data from the TCAM array as the "word" line input of the dual-RAM array.
  • the output data on the "bit" line of the dual-RAM array is as the zone state information of the TCAM array at the next calculating and also as the data bits of the next receiving, which is regarded as the state register data and output state information.
  • the state register which is used to feed back the state information of the dual- RAM array to the TCAM array, and decide the information recently expected to receive in time sequential controlling.
  • the output register which is used to receive the state information from the dual- RAM array , being specified communication protocol configuration (for generally applyed, the related specified communication protocol is the certain communication protocol used in one embodiment), as the control signal having three ways to go: to the bit counting controller being for the the receiving data bit number, to drive the bit synchronization circuit for confirming steps of the receiving serial protocol data, to the polarity rectification circuit for judging the polarity and to the sample generating circuit for actualizing the function which is the content of the programmable state mechanism for terminating the number of the required receiving data.
  • FIG.1 is the circuit diagram which shows a Field Bus receiver including a programmable state mechanism based on TCAM. Using the "NOR-type” or “NAND-type” TCAM array to actualize the matching calculation of the received data with the expected principle of the protocol.
  • a "NOR-type" TCAM array two first-SRAM cells which are shown as FIG.2, connect according to the connected mode shown as FIG.3(a) to compose a "NOR- typei " TCAM cell, or according to the connected mode shown as FIG.3(b) to compose a "NOR-type2" TCAM cell.
  • the connected mode of the "NOR-type" TCAM array is shown as FIG.4.
  • the "NOR-type1 " TCAM cell as shown in FIG.3(a), comprising four MOS transistors(the fifth to eighth MOS transistors N 5 -N 8 in the embodiment) to compose a series-parallel comparison circuit.
  • the gates of two MOS transistors are respectively connected with two SRAM cell(the second to third SRAM cells in the embodiment), the gates of the other two MOS transistors(the seventh to eighth MOS transistors N 7 -N 8 in the embodiment) are respectively connected with the first and second "searching lines" SL 1 and SL 2 ;
  • the MOS transistor whose gate being connected with the SRAM cell is series connected with the MOS transistor whose gate being connected with the "searching line"(that is: the fifth MOS transistor N 5 is series conncected with the seventh MOS transistor N 7 , the sixth MOS transistor N 6 is series conncected with the eighth MOS transistor N 8 ) .
  • the two series connection circuits are parallel connected
  • the "NOR-type” TCAM array as shown in FIG.4, comprising the mxn "NOR-type” TCAM cells(that is the "NOR-type1 " TCAM cell and/or the "NOR-type2" TCAM cell.
  • the "matching line” of the row “NOR-type” TCAM cells are connected with each other as the "word” maching line.
  • the "searching line” of the column “NOR-type” TCAM cells are connected with each other.
  • NAND-type TCAM cell array two SRAM cells which is shown as FIG.2(the sixth to seventh SRAM cells in the embodiment), connect according to the connected mode shown as FIG.5(a) to compose a "NAND-type1 " TCAM cell, or according to the connected mode shown as FIG.5(b) to compose a "NAND-type2" TCAM cell.
  • the connected mode of the "NOR-type” TCAM array is shown as FIG.6.
  • the gates of two MOS are respectively connected with two SRAM cell(the sixth to seventh SRAM cells in the embodiment)
  • the MOS transistors whose connecteing with the SRAM cell by their gates are series connected with the MOS transistors whose connecting with the "searching line" by gate (that is: the thirteenth MOS transistor N 13 is series conncected with the fourteenth MOS transistor N 14 , the fifteenth MOS transistor N 15 is series conncected with the sixteenth MOS transistor N 16 ) .
  • the two series connection circuits are parallel connected together then, wherein, one extremity of the series-parallel connection comparing circuit is as the input "matching line" ML_I and another extremity is as the output "matching line” ML_O.
  • SRAM cell(the eighth SRAM cell in the embodiment) B1 and B 1 are respectively
  • the source or the drain of one of the two MOS transistors(the seventeenth MOS transistor N 17 in the embodiment) is connected with the "searching line” SL 1 .
  • the source or the drain of the other one of the two MOS transistors(the eighteenth MOS transistor N 18 in the embodiment) is connected with the "searching line” SL 2 .
  • the rest two extremities of the two MOS transistors are connected with the gate of the nineteenth MOS transistor N 19 .
  • the gate of the twentieth MOS transistor N 20 is connected with the extremilty B 2 of the other SRAM cell(the nineth SRAM cell in the embodiment) .
  • the twentieth MOS transistor N 20 is parallel connected with the MOS nineteenth transistor N 19 , wherein one extremity of this series-parallel connection comparing circuit is as the input "matching line” ML_I and another extremity is as the output "matching line” ML_O.
  • the "NAND-type” TCAM array as shown in FIG.6, comprising the mxn "NAND- type” TCAM cells(that is the ""NAND-type1 " TCAM cell and/or the "NAND-type2" TCAM cell.
  • the output "matching line” ML_O of the row “NAND-type” TCAM cell is connected with the input "matching line” ML_I of the next row “NAND-type” TCAM cell, which is to form a "word” line.
  • the "searching line” of the column “NOR-type” TCAM cells are connected with each other.
  • the "dual-TCAM" cells is adopted to compose a TCAM array for matching the input signal to the protocol information.
  • Double-TCAM cell as shown in FIG.7(a) and FIG.7(b), eight MOS transistors (the twenty-first to twenty-eigth MOS transistors N 21 -N 28 in the embodiment) are divided into four groups parallely connecting to form a comparison circuit, in which each group is composed of two MOS transistors serial connected.
  • the gate of one of the two MOS transistors in each group (the twenty-first MOS transistor N 21 , the twenty-third MOS transistor N 23 , the twenty-fifth MOS transistor N 25 , the twenty-seventh MOS transistor N 27 , in the embodiment) are respectively controlled by the preserving data extremities of four SRAM cells(the tenth to thirteenth SRAM in the embodiment) .
  • the gate of the other one of the two MOS transistors in each group (the twenty-second MOS transistor N 22 , the twenty-fourth MOS transistor N24, the twenty-sixth MOS transistor N 26 , the twenty-eighth MOS transistor N 28 , in the embodiment) are respectively controlled by the input signal L 0 -L 3 .
  • the idle extremities of the twenty- first MOS transistor N 2 i, the twenty-third MOS transistor N 23 , the twenty-fifth MOS transistor N 25 , the twenty-seventh MOS transistor N 27 are connected to MO as output idle extremities.
  • the idle extremities of the twenty-second MOS transistor N 22 , the twenty-fourth MOS transistor N 24 , the twenty-sixth MOS transistor N 26 , the twenty- eighth MOS transistor N 28 are connected to Ml as input idle extremities.
  • the expected receiving data is confirmed by the content of the four SRAMs(the tenth to thirteenth SRAMs in the embodiment) .
  • Double-TCAM array as shown in FIG.8, the neighboring input signals d l+1 d, are decoded by the 2-bit to 4-bit decoder firstly, and generating four ouput lines as the searching lines of one column cells. Every one row of the dual-TCAM cells are serial connected by the matching line. The data on the output MLSA O -MLSA ⁇ is as the output signal.
  • the whole row cells can be cut- in(that is the whole row cells are in valid operation state) .
  • the lowest row which is used to control the initializing time of all the matching lines is always cut-in.
  • the operating process of the TCAM array is as shown below:
  • the expected input data is deceided by the content of the four SRAM cells(the tenth to thirteenth SRAM in the embodiment) .
  • the advantages of this invention is that it can detect and distinguish the input signal whether is a legality Manchester code (when the B 1 and B 2 are both “1 ", B 0 and B 3 are both "0", only if the d l+1 d, are different from each other, the data canbe able to be transmitted from Ml to MO) .
  • All the MOS transistor mentioned above can therefore be all N- type or P-type, also partly be N-type or P-type.
  • the priority management circuit as shown in FIG.9, its general structure referes to prior art.
  • the inputs of the priority management circuit(such as I 0 , I 1 , I 14 , I 15 ) receive the signal from the output of the TCAM array(such as MLSA 0 -MLSA 15 ) .
  • the outputs of the priority management circuit connect with the input of a group of inner feedback circuit.
  • a inverter which control a gate of the MOS transistor functioning a feedback structure together with the inner feedback circuit.
  • the MOS transistors connecting with every group of inner feedback circuit are serial connected.
  • the output of the inner feedback circuit is connected with the "word" line of the dual-RAM array.
  • the valid data of the legal matching data from the TCAM array is imported to the dual-RAM array as the "word" line through by the priority management circuit.
  • the forty-sixth MOS transistor T 02 is cut-off , which make the input I 1 doesn't work , so the input I 0 has the higest priority.
  • all the inner feedback circuit mentioned above are the same structure.
  • One of them including three MOS transistors, i.e. the inverter and two same-type MOS transistors parallel connected.
  • the share emtrenity of the two same-type MOS transistors is connected with the source/drain of the other-type MOS transistor, and through the inverter connected with the gate of the one MOS transistors of the two same-type MOS transistors parallel connected.
  • the gate of the other one MOS transistors of the two same-type MOS transistors parallel connected is connected with the gate of the other-type MOS transistor, as the input emtrenity.
  • the drain/source of the other-type MOS transistor is as the connecting node with the MOS transistor connected with the inner feedback circuit in every group.
  • the embodiment of the invention for example, there are three MOS transistors and the inverter, in which two same-type MOS transistors(such as PMOS) parallel connected,
  • the share emtrenity of the two same-type MOS transistors parallel connected is connected with the source/drain of the twentieth MOS transistor T O i (NMOS), and connected with the gate of the one MOS transistors of the two same-type MOS transistors parallel connected through the inverter.
  • the gate of the other one MOS transistors of the two same-type MOS transistors parallel connected is connected with the gate of the twentieth MOS transistor T 01 (NMOS), as the input emtrenity.
  • the drain/source of the twentieth MOS transistor T 01 is as the connecting node with the forty-sixth MOS transistor T 02 .
  • the input signal EN 2 is the inverted signal of the output signal EN from the TCAM array in FIG.8, and when the EN 2 is valid, it means the input I 0 -I 15 is at steady opening.
  • the dual-RAM array (referring to prior art) ,see FIG.10, comprises a write port group (having no reference number in the FIG.10) and two read port groups, wherein one group of which (W 02 , W 12 , W 152 ) is as the input "word" line directly connecting with the ouput of the priority management circuit W 0 , W 1 , W 14 , W 15 , another read port group having no reference number in the FIG.10) and the write port group are connect with the peripheral CPU.
  • the "bit" line of the dual-RAM is connected with the state register and output register.
  • the operation process of the circuit is as shown below: after reset, the content of the state register feeds back to the TCAM array for determinating the expected receiving information.
  • the bit number of the receiving data is decided by the content of the output register.
  • the bit counting controller circuit When the number of the receiving data reaches the number specified by the output register, the bit counting controller circuit generates the startup signal and transmits the receiving data from the shift register to the input register, then stats up the matching calculation of the TCAM array.
  • the valid matching data of the legal matching data is imported to the dual-RAM array as the "word" line passed by the priority management circuit.
  • the output data read from the dual-RAM array (including: the coding signal of state from the peripheral CPU which is programmable, corresponding to the TCAM array, and the controlfef signal of the data path circuit ) is as the coding signal of the next state and the controlling signal of the data path circuit. So the function of the progrqmmable is actualized.
  • the function of the Field Bus protocols receiver is actualized by writing the expected information of every phases into the TCAM array. Becase the condition of the state transform and various control signals are both decided by the data in the dual-RAM array, as well as the dual-RAM array and the TCAM array are both programmable, the state machine of the receiver is programmable. Furthermore, the other parts of the Field Bus protocols receiver receiving Manchester code can be actualized by the same structure, so the receiver is widely applicable .

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Abstract

The present invention relates to a technology for a Field Bus control, particularly a general field bus receiver and receiving method thereof. The receiving method is to create the programmable state mechanism through the priority management circuit by combining the dual-TCAM array with dual-RAM array, for distinguishing the Manchester code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using 'don't care' logic function of TCAM, and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to receive the general Field Bus protocol based on the Manchester code. The present invention being general for various protocols can be applied to various protocols based on the Manchester code, instead of all the Field Bus receiving circuits in the art.

Description

GENERAL FIELD BUS RECEIVER AND RECEIVING METHOD THEREOF
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for a Field Bus control, particularly a general Field Bus receiver based on ternary content addressable memory(TCAM) and receiving method thereof. BACKGROUND OF THE INVENTION
Communication controller chip is one of the most important devices of the Field Bus system, which is used to encode and uncode the data on the bus. There are many types of Field Bus protocols in the international standard IEC61158 at present. Herein, the Manchester code is used in many protocols, however the format and the definitions of preamb^ start-delimiter end-delimiter of the Physical layer protocol are different from each other, the business Field Bus receiver is recently based on the traditional logic circuit, which commonly can only be used for receiving just one type of the protocols. As a variety of uses of the Field Bus protocols, the market share of single communication protocol chip is small and the cost rate of the whole system is on a high side. The major difference of the various hardware Field Bus systems is the communication controller, the key part of which is Manchester code receiving cicuit. In case the circuit is general for various protocols, general Field Bus controller and System on a chip(SOC) can be realized. SUMMARY OF THE INVENTION
The purpose of the invention is to provide a programmable receiving method and receiver based on ternary content addressable memohs(TCAM) for all the Field Bus protocols using Manchester code, by receiving the correspongding Field Bus protocols data according to the various data written into the RAM array.
To bring about the functions above, the technical scheme of the invention is : the programmable state mechanism, which is in stead of the traditional fixed function state mechanism combined by the logic gate circuit, is created through the priority management circuit by combining the TCAM array, functioning to distinguish whether or not the received data being in accordance with the special symbol defined by the expected principle of the protocol, with dual-RAM array being for preserving the corresponding state signal and control signal. Wherein
The receiving method of the general Field Bus based on the Manchester code is: to create the programmable state mechanism through the priority management circuit by combining the dual-TCAM array with dual-RAM array, for distinguishing the Mancheset code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using "don't care" logic function of TCAM, and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to recive the general Field Bus protocol based on the Manchester code.
The whole working process is unattached and has no exterior process intervention.
The realization of the programmable state method in detail is as shown below: Inputting the state signal and control signal preserved by the dual-RAM array to the dual-TCAM array by a state register mode for matching calculation of the received data with the expected principle of the protocol, and distinguishing whether the received data in accordance with the special symbol defined by the expected principle of the protocol, by using the "don't care" logic function of TCAM(L e. supporting the function of any logic lookup); and then importing the valid matching data from the legal matching data to the dual-RAM array as the "word" line through the priority management circuit; being as zone state information of the TCAM array by the output data on the "bit" line of the dual-RAM array at the next calculating and also as the data bits of the next receiving, which is regarded as the state register data and output state information; adopting the content of the output state information to be a control signal for driving a data path of the traditional circuit which is implemented by the standard logic cells; and then providng the data from the data path to the TCAM array through the data path part in the operation of an input register, thereby achieving a new calculation and sequentially fulfilling the next transform of the state- mode.
The method of detecting and distinguishing the Manchester code is those that of decoding the data from the input register to the 2-bit to 4-bit, configuring the input lines of the dual-TCAM array to meet requirement of the Manchester code according to a mode of the dual-TCAM array, and transmiting the register data from the input of the TCAM array to its output for functioning to detect and distinguish the Manchester code, only if the register data of every neighboring bits output from the 2-bit to 4-bit is different which satisfies the requirement of the Manchester code.
The general Field Bus receiver consists of :
A bit synchronization circuit, which is used to make the serial input data bit synchronize according to the designated communication protocol configuration, for creating valid data sampling information;
A sample generating circuit, which is used to receive the valid data sampling information from the bit synchronization circuit, generates two output signals according to the specified communication protocol configuration, wherein one output signal is as the data that already sampled used to be a shift register data. Another output signal provides the number of the receiving data pulses to a bit counting controller; while one shift register data is generated, one pulse signal is generated.
A polarity rectification circuit, which is used to judge the polarity of the serial data according to the specified communication protocol configuration, rectify the polarity and then import the polarity rectification information for shift registering.
The shift register, which is used to transform the serial input data already sampled to the parallel data according to the polarity rectification information.
The input register, which is used to buffer the parallel data in the shift register on the control of timing.
The bit counting controller, which is used to receive the pulse signal generated by the sample generating circuit (one shift register data is generated, while one pulse signal is generated by the sample generating circuit), and independently count the data bits imported to the shift register on time according to the receiving data bit number of the specified communication protocol configuration; generate a start-up signal of the sequential controller and the control signal of the specified communication protocol after the received data number reaching the specified communication protocol configuration.
A sequential control circuit, which is used to generate the configuration information correspond to the specified communication protocol, according to the control signal of the specified communication protocol generated by the bit counting controller, and import the configuration information in correspondence with the specified communication protocol to the input register and the state register, generate the sequential control signal in correspondence with the specified communication protocol, at the same time.
The programmable state mechanism, which is composed of the TCAM array, the priority management circuit and the dual-RAM array. Herein the TCAM array is used to actualize matching calculation of the received parallel data from the input register with the expected principle of the protocol in time sequential controlling, i. e the dual- RAM array receives the valid data of the legal matching data is imported as the "word" line passed by the TCAM array through the priority management circuit after distinguishing the parallel data from the input register whether the special symbol is specified by the protocol; In time sequential controlling, the input of the priority management circuit connects with the output of the TCAM array for confirming the only one valid output while many legal matching data output from the TCAM array, and an output of the priority management circuit connects with the "word" line of the dual-RAM array; The dual-RAM array stores the programmable state signal corresponding to the TCAM array and the programmable control signal applying the data path circuit(such as the bit synchronization circuit, the sample generating cicuit, the polarity rectification circuit, the bit counting controller), which both are from peripheral CPU; In time sequential controlling, the input of the priority management circuit is the valid data from the TCAM array as the "word" line input of the dual-RAM array; The output data on the "bit" line of the dual-RAM array is as the zone state information of the TCAM array at the next calculating and also as the data bits of the next receiving , which is regarded as the state register data and output state information.
The state register, which is used to feed back the state information of the dual- RAM array to the TCAM array, and decide the information recently expected to receive in time sequential controlling.
An output register, which is used to receive the state information from the dual- RAM array, being specified communication protocol configuration as the control signal having three ways to go: to the bit counting controller being for the the receiving data bit number, to drive the bit synchronization circuit for confirming steps of the receiving serial protocol data , to the polarity rectification circuit for judging the polarity , and to the sample generating circuit for actualizing the function which is the content of the programmable state mechanism for terminating the number of the required receiving data.
The matching calculation of the received data with the expected principle of the protocol adopts "NOR-type" or "NAND-type" TCAM array.
The "dual-TCAM" cell comprises eight MOS transistors dividing into four groups parallely connected by each group having two MOS transistors serial connected to form a comparing circuit. Wherein, the preserving data extremities of four SRAM cells respectively control one gate of the two MOS transistors in each group, the input signals respectively control another gate of the two MOS transistors in the same group, one idle extremity of the one of the two MOS transistors in each group see connectsβ€l together as an output idle extremity, another idle extremity of the two MOS transistors in the same group connects together as an input idle extremity. The content of the four SRAM provides the expected receiving data.
The "dual-TCAM" array is composed of the dual-TCAMs and 2-bit to 4-bit decoders; Herein, the every two neighboring lines of the 2-bit to 4-bit decoder receives singnals from the input register for decoding, and 4 output lines of the decoder are as searching lines of a column cells; the dual-TCAMs in each row are serial connected by a matching line.
The invention has the following advantages: 1. The present invention being general for various protocols based on the Manchester code can be applied to verious protocols as the central part of the communication controller . The general Field Bus communication controller chip and SOC can be designed by using this invention. Various content is likely written to the receiver provided by the present invention for various Field Bus protocols to meet requirements of the protocols since the TCAM and dual-RAM are both programmable, and the content of which canbe written by the peripheral CPU.
2. Having multifunctional, being shown below:
Distinguishing the preamble from the bus and realizing bit synchronization;
Judging the polarity of signals and operating polarity auto-rectification;
Distinguishing the start-delimiter and actualizing data synchronization;
Decoding the Manchester code data;
Distinguishing invalid data, and preserving the valid data in the receiving buffer of the dual-RAM array;
Judging type and address of information of the receiving data, and shielding the needless data;
Distinguishing the end-delimiter from the bus and generating receiving end-signal of protocol data.
3. The present invention has a larger market and lower design cost as it is applicable for various communication protocol.
4. The communication controller and SOC based on the Manchester code have the far-ranging using foreground and commercial worth.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is a block diagram illustrating Protocol Data Receiver in accordance with the embodiment of the invention.
FIG.2 is a structural drawing illustrating the first SRAM cell in accordance with the embodiment of the invention.
FIG.3(a) is a structural drawing illustrating the NOR-type1 TCAM.
FIG.3(b) is a structural drawing illustrating the NOR-type 2 TCAM.
FIG.4 is a structural drawing illustrating the NOR-type TCAM array.
FIG.5(a) is a structural drawing illustrating the NAND-type1 TCAM.
FIG.5(b) is a structural drawing illustrating the NAND-type2 TCAM.
FIG.6 is a structural drawing illustrating the NAND-type TCAM array.
FIG.7(a) is a structural drawing illustrating the dual-TCAM cell in accordance with the embodiment of the invention.
FIG.7(b) is a block diagram illustrating the symbol of the dual-TCAM cell in accordance with the embodiment of the invention.
FIG.8 is a structural drawing illustrating the TCAM array in accordance with the embodiment of the invention.
FIG.9 is a structural drawing illustrating the priority management circuit in accordance with the embodiment of the invention.
FIG.10 is a structural drawing illustrating the dual-RAM array circuit in accordance with the embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
The method of the inventation of the general Field Bus Manchester code receiver is=as shown below:
The programmable state mechanism is composed of the dual-TCAM array and dual-RAM array based on ternary content addressable memohs(TCAM) instead of the trandition one which is composed by the logic circuit with the fixed function, distinguishing the Manchester code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using "don't care" logic function of TCAM(supporting the function of any logic lookup), and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to recive the general Field Bus protocol based on the Manchester code.The whole working process is unattached and no exterior process intervention.
A way of bring about the programmable state mechanism is that the TCAM array is in combination with dual-RAM array connected by the priority management circuit.
The realization of the programmable state method in detail is as shown below:
Inputting the state signal and control signal preserved by the dual-RAM array to the dual-TCAM array by the state register mode for matching calculation of the received data with the expected principle of the protocol, and distinguishing whether the received data in accordance with the special symbol defined by the expected principle of the protocol, by using the "don't care" logic function of TCAM(L e. supporting the function of any logic lookup); and then importing the valid matching data from the legal matching data to the dual-RAM array as the "word" line through the priority management circuit; being zone state information of the TCAM array, on the "bit" line of the dual-RAM array at the next calculating and also as the data bits of the next receiving , which is regarded as the state register data and output state information; adopting the content of the output state information to be a control signal for driving a data path of the traditional circuit which is implemented by the standard logic cells(such as the bit synchronization, a sampling generator, the bit countinger controller, the shift register, the input register, etc.); and then providing the data from the data path to the TCAM array through the data path part in the operation of an input register, thereby achieving a new calculation and sequentially fulfilling the next transform of the state mechanism-mode.
After the CPU imports the input data to the RAM array initializing the information, the intervention of the CPU is not needed during the process of combination for the programmable state mechanism referenced above. When receiving some data which is definitely defined by the protocol, the programmable state mechanism then performs correct state transform and output the analytical result according to the content of the data. Because the TCAM array and dual-RAM array are both programmable, the programmable state mechanism is realizable.
The mothed of detecting and distinguishing the Manchester code is that of decoding the data in the input register to the 2-bit to 4-bit, configuring the input lines of the dual-TCAM array to meet requirement of the Manchester code according to a mode of the dual-TCAM array, and transmiting the register data from the input of the TCAM array to its output for functioning to detect and distinguish the Manchester code, only if the register data of every neighboring bits output from the 2-bit to 4-bit is differentwhich satisfies the requirement of the Manchester code.
The general Field Bus receiver provided by the present invention consists of:
The bit synchronization circuit, which is used to make the serial input data bit synchronize according to the designated communication protocol configuration, and output valid data sampling information;
The sample generating circuit, which is used to receive the valid data sampling information from the bit synchronization circuit, generates two output signals according to the specified communication protocol configuration, wherein one output signal is as the data that already sampled used to be a shift register data.Another output signal provides the number of the receiving data pulses to a bit counting controller; while one shift register data is generated, one pulse signal is generated.
The polarity rectification circuit, which is used to judge the polarity of the serial data according to the specified communication protocol configuration, rectify the polarity and then import the polarity rectification information for shift registering.
The shift register, which is used to transform the serial input data already sampled to the parallel data according to the polarity rectification information.
The input register, which is used to buffer the parallel data in the shift register on the control of timing.
The bit counting controller, which is used to receive the pulse signal generated by the sample generating circuit (while one shift register data is generated, one pulse signal is generated by the sample generating circuit), and independently count the data bits imported to the shift register on time according to the receiving data bit number of the specified communication protocol configuration; after the received data number reaches the specified communication protocol configuration, a fee start-up signal of the sequential controller and the control signal of the specified communication protocol are generated by the bit counting controller.
The sequential control circuit, which is used to generate the configuration information correspond to the specified communication protocol, according to the control signal of the specified communication protocol generated by the bit counting controller, and import the configuration information in correspondence with the specified communication protocol to the input register and state register, at the same time, generate the sequential control signal in correspondence with the specified communication protocol.
The programmable state mechanism, which is composed of by the TCAM array, the priority management circuit and the dual-RAM array. Herein the TCAM array is used to actualize matching calculation of the received parallel data from the input register with the expected principle of the protocol in time sequential controlling(including identifying the protocol information of the bus such as the start- delimiter, detecting invalid data(whether the data is Manchester code ) . i. e the valid data of the legal matching data is imported to the dual-RAM array as the "word" line passed by the TCAM array through the priority management circuit after distinguishing the parallel data from the input register whether the special symbol is specified by the protocol. In time sequential controlling, the input of the priority management circuit is connected with the output of the TCAM array for confirming the only one valid output while many legal matching data output from the TCAM array, and the output of the priority management circuit is connected with the "word" line of the dual-RAM array. The dual-RAM array stores the programmable state signal corresponding the TCAM array and the programmable control signal corresponding the data path circuit(such as the bit synchronization circuit, the sample generating cicuit, the polarity rectification circuit, the bit counting controller), which both are imported by peripheral CPU. In time sequential controlling, the input of the priority management circuit is the valid data from the TCAM array as the "word" line input of the dual-RAM array. The output data on the "bit" line of the dual-RAM array is as the zone state information of the TCAM array at the next calculating and also as the data bits of the next receiving, which is regarded as the state register data and output state information.
The state register, which is used to feed back the state information of the dual- RAM array to the TCAM array, and decide the information recently expected to receive in time sequential controlling. The output register, which is used to receive the state information from the dual- RAM array , being specified communication protocol configuration (for generally applyed, the related specified communication protocol is the certain communication protocol used in one embodiment), as the control signal having three ways to go: to the bit counting controller being for the the receiving data bit number, to drive the bit synchronization circuit for confirming steps of the receiving serial protocol data, to the polarity rectification circuit for judging the polarity and to the sample generating circuit for actualizing the function which is the content of the programmable state mechanism for terminating the number of the required receiving data.
The embodiment of this inventation is to make one kind of the programmable state mechanism based on the TCAM instead of the traditional state machine. FIG.1 is the circuit diagram which shows a Field Bus receiver including a programmable state mechanism based on TCAM. Using the "NOR-type" or "NAND-type" TCAM array to actualize the matching calculation of the received data with the expected principle of the protocol.
The traditional composing mode of the TCAM array is as shown below: 1. A "NOR-type" TCAM array: two first-SRAM cells which are shown as FIG.2, connect according to the connected mode shown as FIG.3(a) to compose a "NOR- typei " TCAM cell, or according to the connected mode shown as FIG.3(b) to compose a "NOR-type2" TCAM cell. The connected mode of the "NOR-type" TCAM array is shown as FIG.4.
1.1 The "NOR-type1 " TCAM cell: as shown in FIG.3(a), comprising four MOS transistors(the fifth to eighth MOS transistors N5-N8 in the embodiment) to compose a series-parallel comparison circuit. Herein the gates of two MOS transistors (the fifth to sixth MOS transistors N5-N6 in the embodiment) are respectively connected with two SRAM cell(the second to third SRAM cells in the embodiment), the gates of the other two MOS transistors(the seventh to eighth MOS transistors N7-N8 in the embodiment) are respectively connected with the first and second "searching lines" SL1 and SL2; The MOS transistor whose gate being connected with the SRAM cell is series connected with the MOS transistor whose gate being connected with the "searching line"(that is: the fifth MOS transistor N5 is series conncected with the seventh MOS transistor N7, the sixth MOS transistor N6 is series conncected with the eighth MOS transistor N8 ) . The two series connection circuits are parallel connected together. One extremity of the series-parallel connection comparison circuit is connected with "GND", and the other one extremity is as the "matching line" ML.
1.2 The "NOR-type2" TCAM cell: as shown in FIG.3(b), the two extremities of one SRAM cell(the fourth SRAM cell in the embodiment) B1 and B1 are respectively
connected with the gates of two MOS transistors(the ninth MOS transistor N9 and the tenth MOS transistor N10 in the embodiment) . The source or the drain of one of the two MOS transistors(the ninth MOS transistor N9 in the embodiment) is connected with the "searching line" SL1. The source or the drain of the other one of the two MOS transistors(the tenth MOS transistor N10 in the embodiment) is connected with the "searching line" SL2. The rest two extremities of the two MOS transistors are connected with the gate of the eleventh MOS transistor N11, the gate of the twelfth MOS transistor N12 is connected with the extremilty B2 of another SRAM cell(the fifth SRAM cell in the embodiment) . Two extremities of parallel connection circuit of the twelfth MOS transistor N12 and the eleventh MOS transistor N11 respectively connects with "GND" and "matching line" ML.
1.3 The "NOR-type" TCAM array: as shown in FIG.4, comprising the mxn "NOR-type" TCAM cells(that is the "NOR-type1 " TCAM cell and/or the "NOR-type2" TCAM cell. The "matching line" of the row "NOR-type" TCAM cells are connected with each other as the "word" maching line. The "searching line" of the column "NOR-type" TCAM cells are connected with each other.
2. "NAND-type" TCAM cell array: two SRAM cells which is shown as FIG.2(the sixth to seventh SRAM cells in the embodiment), connect according to the connected mode shown as FIG.5(a) to compose a "NAND-type1 " TCAM cell, or according to the connected mode shown as FIG.5(b) to compose a "NAND-type2" TCAM cell. The connected mode of the "NOR-type" TCAM array is shown as FIG.6. 2.1 "NAND-type1 " TCAM cell: shown as FIG.5(a), comprising four MOS transistors(the thirteenth to sixteenth MOS transistors N13-N16 in the embodiment) to compose a series-parallel comparison circuit. Herein the gates of two MOS(the thirteenth MOS transistor N13 and the sixteenth MOS transistor N16 in the embodiment) are respectively connected with two SRAM cell(the sixth to seventh SRAM cells in the embodiment) The gates of the other two MOS transistors(the fourteenth MOS transistor N14 and the fifteenth MOS transistor N15 in the embodiment) are respectively=connected with the first and second "searching line" SL1 and SL2. The MOS transistors whose connecteing with the SRAM cell by their gates are series connected with the MOS transistors whose connecting with the "searching line" by gate (that is: the thirteenth MOS transistor N13 is series conncected with the fourteenth MOS transistor N14, the fifteenth MOS transistor N15 is series conncected with the sixteenth MOS transistor N16 ) . The two series connection circuits are parallel connected together then, wherein, one extremity of the series-parallel connection comparing circuit is as the input "matching line" ML_I and another extremity is as the output "matching line" ML_O.
2.2 The"NAND-type2" TCAM cell: as shown in FIG.5(b), the two extremities of one
SRAM cell(the eighth SRAM cell in the embodiment) B1 and B1 are respectively
connected with the gates of two MOS transistors(the seventeenth MOS transistor N17 and the eighteenth MOS transistor N18 in the embodiment) . The source or the drain of one of the two MOS transistors(the seventeenth MOS transistor N17 in the embodiment) is connected with the "searching line" SL1. The source or the drain of the other one of the two MOS transistors(the eighteenth MOS transistor N18 in the embodiment) is connected with the "searching line" SL2. The rest two extremities of the two MOS transistors are connected with the gate of the nineteenth MOS transistor N19. The gate of the twentieth MOS transistor N20 is connected with the extremilty B2 of the other SRAM cell(the nineth SRAM cell in the embodiment) . The twentieth MOS transistor N20 is parallel connected with the MOS nineteenth transistor N19, wherein one extremity of this series-parallel connection comparing circuit is as the input "matching line" ML_I and another extremity is as the output "matching line" ML_O. 2.3The "NAND-type" TCAM array: as shown in FIG.6, comprising the mxn "NAND- type" TCAM cells(that is the ""NAND-type1 " TCAM cell and/or the "NAND-type2" TCAM cell. The output "matching line" ML_O of the row "NAND-type" TCAM cell is connected with the input "matching line" ML_I of the next row "NAND-type" TCAM cell, which is to form a "word" line. The "searching line" of the column "NOR-type" TCAM cells are connected with each other.
In this invention, the "dual-TCAM" cells is adopted to compose a TCAM array for matching the input signal to the protocol information.
"Dual-TCAM" cell: as shown in FIG.7(a) and FIG.7(b), eight MOS transistors (the twenty-first to twenty-eigth MOS transistors N21-N28 in the embodiment) are divided into four groups parallely connecting to form a comparison circuit, in which each group is composed of two MOS transistors serial connected. The gate of one of the two MOS transistors in each group(the twenty-first MOS transistor N21, the twenty-third MOS transistor N23, the twenty-fifth MOS transistor N25, the twenty-seventh MOS transistor N27, in the embodiment) are respectively controlled by the preserving data extremities of four SRAM cells(the tenth to thirteenth SRAM in the embodiment) . The gate of the other one of the two MOS transistors in each group(the twenty-second MOS transistor N22, the twenty-fourth MOS transistor N24, the twenty-sixth MOS transistor N26, the twenty-eighth MOS transistor N28, in the embodiment) are respectively controlled by the input signal L0-L3. The idle extremities of the twenty- first MOS transistor N2i, the twenty-third MOS transistor N23, the twenty-fifth MOS transistor N25, the twenty-seventh MOS transistor N27 are connected to MO as output idle extremities. The idle extremities of the twenty-second MOS transistor N22, the twenty-fourth MOS transistor N24, the twenty-sixth MOS transistor N26, the twenty- eighth MOS transistor N28 are connected to Ml as input idle extremities. The expected receiving data is confirmed by the content of the four SRAMs(the tenth to thirteenth SRAMs in the embodiment) .
"Dual-TCAM" array: as shown in FIG.8, the neighboring input signals dl+1d, are decoded by the 2-bit to 4-bit decoder firstly, and generating four ouput lines as the searching lines of one column cells. Every one row of the dual-TCAM cells are serial connected by the matching line. The data on the output MLSAO-MLSA^ is as the output signal. When the input signals of all the cells meet the requirement of the logic relation determinated by the data in the SRAM cells, the whole row cells can be cut- in(that is the whole row cells are in valid operation state) . In the FIG.8, the lowest row which is used to control the initializing time of all the matching lines is always cut-in.
The operating process of the TCAM array is as shown below:
Shown as the FIG.7(a) and FIG.8, the input signals L0-L3 are the output data decoded from the neighboring input signal dl+1d, by the 2-bit to 4-bit decoder Such as, when dl+1d,="OO", L0=1 ; when dl+1d,="01 ", L1=I ; when dl+1d,="10", L2=I ; when dl+1d,="11 ", L3=L The expected input data is deceided by the content of the four SRAM cells(the tenth to thirteenth SRAM in the embodiment) . For example, when B0=I which is the output of tenth SRAM cell shown in FIG, 7(a), the output of eleventh to thirteenth SRAM cells B1-B3 are all "0", no other than the dl+1d,="OO"(that is L0=I ), the data can be transmitted from the idle extremity Ml to the idle extremity MO, which actualizes the matching between the niput signal and the preserving protocol information. Comparing the traditional TCAM cell, the advantages of this invention is that it can detect and distinguish the input signal whether is a legality Manchester code (when the B1 and B2 are both "1 ", B0 and B3 are both "0", only if the dl+1d, are different from each other, the data canbe able to be transmitted from Ml to MO) .
The transform of the TCAM cell and array in the invention: interchanges the B and
B of the SRAM cell. All the MOS transistor mentioned above can therefore be all N- type or P-type, also partly be N-type or P-type.
The priority management circuit: as shown in FIG.9, its general structure referes to prior art. The inputs of the priority management circuit(such as I0, I1, I14, I15) receive the signal from the output of the TCAM array(such as MLSA0-MLSA15) . The outputs of the priority management circuit connect with the input of a group of inner feedback circuit. And a inverter which control a gate of the MOS transistor functioning a feedback structure together with the inner feedback circuit. The MOS transistors connecting with every group of inner feedback circuit are serial connected. The output of the inner feedback circuit is connected with the "word" line of the dual-RAM array. The valid data of the legal matching data from the TCAM array is imported to the dual-RAM array as the "word" line through by the priority management circuit. When the input I0 is "1 ", the forty-sixth MOS transistor T02 is cut-off , which make the input I1 doesn't work , so the input I0 has the higest priority.
Herein, all the inner feedback circuit mentioned above are the same structure. One of them including three MOS transistors, i.e. the inverter and two same-type MOS transistors parallel connected. The share emtrenity of the two same-type MOS transistors is connected with the source/drain of the other-type MOS transistor, and through the inverter connected with the gate of the one MOS transistors of the two same-type MOS transistors parallel connected. The gate of the other one MOS transistors of the two same-type MOS transistors parallel connected is connected with the gate of the other-type MOS transistor, as the input emtrenity. The drain/source of the other-type MOS transistor is as the connecting node with the MOS transistor connected with the inner feedback circuit in every group. The embodiment of the invention ,for example, there are three MOS transistors and the inverter, in which two same-type MOS transistors(such as PMOS) parallel connected, The share emtrenity of the two same-type MOS transistors parallel connected is connected with the source/drain of the twentieth MOS transistor TOi (NMOS), and connected with the gate of the one MOS transistors of the two same-type MOS transistors parallel connected through the inverter. The gate of the other one MOS transistors of the two same-type MOS transistors parallel connected is connected with the gate of the twentieth MOS transistor T01(NMOS), as the input emtrenity. The drain/source of the twentieth MOS transistor T01 is as the connecting node with the forty-sixth MOS transistor T02. The input signal EN2 is the inverted signal of the output signal EN from the TCAM array in FIG.8, and when the EN2 is valid, it means the input I0-I15 is at steady opening.
The dual-RAM array (referring to prior art) ,see FIG.10, comprises a write port group (having no reference number in the FIG.10) and two read port groups, wherein one group of which (W02, W12, W152) is as the input "word" line directly connecting with the ouput of the priority management circuit W0, W1, W14, W15, another read port group having no reference number in the FIG.10) and the write port group are connect with the peripheral CPU. The "bit" line of the dual-RAM is connected with the state register and output register.
The operation process of the circuit is as shown below: after reset, the content of the state register feeds back to the TCAM array for determinating the expected receiving information. The bit number of the receiving data is decided by the content of the output register. When the number of the receiving data reaches the number specified by the output register, the bit counting controller circuit generates the startup signal and transmits the receiving data from the shift register to the input register, then stats up the matching calculation of the TCAM array. The valid matching data of the legal matching data is imported to the dual-RAM array as the "word" line passed by the priority management circuit. The output data read from the dual-RAM array (including: the coding signal of state from the peripheral CPU which is programmable, corresponding to the TCAM array, and the controlfef signal of the data path circuit ) is as the coding signal of the next state and the controlling signal of the data path circuit. So the function of the progrqmmable is actualized. The function of the Field Bus protocols receiver is actualized by writing the expected information of every phases into the TCAM array. Becase the condition of the state transform and various control signals are both decided by the data in the dual-RAM array, as well as the dual-RAM array and the TCAM array are both programmable, the state machine of the receiver is programmable. Furthermore, the other parts of the Field Bus protocols receiver receiving Manchester code can be actualized by the same structure, so the receiver is widely applicable .

Claims

What is claimed is:
1. A general field bus receiving method is to create the programmable state mechanism through the priority management circuit by combining the dual-TCAM array with dual-RAM array, for distinguishing the Manchester code by using the TCAM array, matching calculation of the received data with the expected principle of the protocol by using "don't care" logic function of TCAM, and distinguishing whether the received data is in accordance with the special symbol defined by the expected principle of the protocol in order to receive the general Field Bus protocol based on the Manchester code.
2. The general field bus receiving method according to the claim 1 , characterized in that the whole working process is unattached and no exterior process intervention.
3. The general field bus receiving method according to the claim 1 , characterized in that the realization of the programmable state method in detail is as shown below: Inputting the state signal and control signal preserved by the dual-RAM array to the dual-TCAM array by a state register mode for matching calculation of the received data with the expected principle of the protocol, and distinguish whether the received data in accordance with the special symbol defined by the expected principle of the protocol, by using the "don't care" logic function of TCAM; and then importing the valid matching data from the legal matching data to the dual-RAM array as the "word" line through the priority management circuit; being as zone state information of the TCAM array by the output data on the "bit" line of the dual- RAM array at the next calculating and also as the data bits of the next receiving, which is regarded as state register data and output state information; adopting the content of the output state information to be a control signal for driving a data path of the traditional circuit which is implemented by the standard logic cells; and then providing the data from the data path to the TCAM array through the data path part in the operation of an input register, thereby achieving a new calculation, and sequentially fulfilling the next transform of the state-mode.
4. The general field bus receiving method according to the claim 1 , characterized in that the method of detecting and distinguishing the Manchester code is those that of decoding the data from the input register to the 2-bit to 4-bit , configuring the input lines of the dual-TCAM array to meet requirement of the Manchester code according to a mode of the dual-TCAM array, and transmitting the register data from the input of the TCAM array to its output for functioning to detect and distinguish the Manchester code, only if the register data of every neighboring bits output from the 2-bit to 4-bit is different which satisfies the requirement of the Manchester code.
5. A general field bus receiver, characterized in that consisting of: a bit synchronization circuit, which makes the serial input data bit synchronize according to the designated communication protocol configuration, for creating valid data sampling information; a sample generating circuit, which receives the valid data sampling information from the bit synchronization circuit, generates two output signals according to the specified communication protocol configuration, in which one is as sampled data being a shift register data, another provides the number of the receiving data pulses to a bit counting controller; shift register generates one shift register data while the bit counting controller creates one pulse signal; a polarity rectification circuit, which is used to judge the polarity of the serial data according to the specified communication protocol configuration, rectify the polarity and then import the polarity rectification information for shift registering; a shift register, which transforms the serial input data already sampled to the parallel data according to the polarity rectification information; a n input register, which buffers the parallel data in the shift register on the control of timing; a bit counting controller, which receives the pulse signal generated by the sample generating circuit, and independently counts the data bits imported to the shift register on time according to the receiving data bit number of the specified communication protocol configuration; generates a start-up signal of the sequential controller and the control signal of the specified communication protocol after the received data number reaching the specified communication protocol configuration. a sequential control circuit, which is used to generate the configuration information correspond to the specified communication protocol, according to the control signal of the specified communication protocol generated by the bit counting controller, and import the configuration information in correspondence with the specified communication protocol to the input register and the state register, generate the sequential control signal in correspondence with the specified communication protocol, at the same time; a programmable state mechanism, which is composed of the TCAM array, the priority management circuit and the dual-RAM array, wherein the TCAM array is used to actualize matching calculation of the received parallel data from the input register with the expected principle of the protocol in time sequential controlling, i. e the dual- RAM array receives the valid data of the legal matching data is imported as the "word" line passed by the TCAM array through the priority management circuit after distinguishing the parallel data from the input register whether the special symbol is specified by the protocol; In time sequential controlling, the input of the priority management circuit connects with the output of the TCAM array for confirming the only one valid output while many legal matching data output from the TCAM array, and an output of the priority management circuit connects with the "word" line of the dual-RAM array; The dual-RAM array stores the programmable state signal corresponding to the TCAM array and the programmable control signal applying the data path circuit, which both are from peripheral CPU; In time sequential controlling, the input of the priority management circuit is the valid data from the TCAM array as the "word" line input of the dual-RAM array; The output data on the "bit" line of the dual-RAM array is as the zone state information of the TCAM array at the next calculating and also as the data bits of the next receiving , which is regarded as the state register data and output state information; a state register, which feeds back the state information of the dual-RAM array to the TCAM array, and decide the information recently expected to receive in time sequential controlling; an output register, which receives the state information from the dual-RAM array being specified communication protocol configuration as the control signal having three ways to go: to the bit counting controller being for the receiving data bit number, to drive the bit synchronization circuit for confirming steps of the receiving serial protocol data, to the polarity rectification circuit for judging the polarity, and to the sample generating circuit for actualizing the function which is the content of the programmable state mechanism for terminating the number of the required receiving data.
6. The general field bus receiver according to the claim 5, characterized in that the matching calculation of the received data with the expected principle of the protocol adopts "NOR-type" or "NAND-type" TCAM array.
7. The general field bus receiver according to the claim 5, characterized in that the "dual-TCAM" cell comprises eight MOS transistors dividing into four groups parallel connected by each group having two MOS transistors serial connected to form a comparing circuit. Wherein, the preserving data extremities of four SRAM cells respectively control one gate of the two MOS transistors in each group, the input signal respectively control another gate of the two MOS transistors in the same group one idle extremity of the one of the two MOS transistors in each group connects together as an output idle extremity, another idle extremity of the two MOS transistors in the same group connects together as an input idle extremity. The content of the four SRAM provides the expected receiving data. The general field bus receiver according to the claim 5, characterized in that the "dual-TCAM" array comprises the dual-TCAMs and 2-bit to 4-bit decoders; herein, the every two neighboring lines of the 2-bit to 4-bit decoder receives signals from the input register for decoding, and 4 output lines of the decoder are as searching lines of a column cells; the dual-TCAMs in each row are serial connected by the matching line.
PCT/CN2008/071905 2008-03-19 2008-08-07 General field bus receiver and receiving method thereof WO2009114974A1 (en)

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