WO2009141788A1

WO2009141788A1 - Semiconductor devices and methods of manufacture thereof

Info

Publication number: WO2009141788A1
Application number: PCT/IB2009/052079
Authority: WO
Inventors: Bartlomiej Jan Pawlak
Original assignee: Nxp B.V.
Priority date: 2008-05-21
Filing date: 2009-05-19
Publication date: 2009-11-26

Abstract

Semiconductor devices are described which involve resonant tunneling in their operation. Methods for the manufacture for such devices are also described. The devices include a fin (4) of electrode material which forms a first main electrode of the device (2,2') on an insulating substrate (6). A stack of layers is provided on the fin comprising a layer (10) of semiconductor material forming a quantum well layer sandwiched between layers (8,12) of dielectric material which form tunneling barrier layers. A layer (14) of electrode material over the stack forms a second main electrode. The device may be a diode, or a transistor in which further layers are provided which form a gate dielectric layer (16) and a gate electrode layer (18) over the stack.

Description

DESCRIPTION

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

THEREOF

The present invention relates to semiconductor devices and more particularly to devices which involve resonant tunneling in their operation. Methods for the manufacture of such devices are also described.

The article "Resonant Tunneling in Semiconductor Double Barriers" by

Chang et al, App. Phys. Lett., Vol. 24, No. 12, June 1974 describes resonant tunneling of electrons in double barrier structures having a thin GaAs layer sandwiched between GaAIAs barrier layers. These principles have been applied in fabrication of resonant tunneling diodes, for example as described in US 2005/0056827.

US6765303 relates to an SRAM cell including a single FinFET and two tunnel diodes. Each tunnel diode includes an undoped silicon fin, a dielectric layer on each side of the fin, and a protective cap. A doped polysilicon layer surrounds the fin.

The present invention provides a semiconductor device including: a fin of electrode material forming a first main electrode on an insulating substrate; and a stack of layers formed on the fin comprising: a layer of dielectric material forming a first tunnelling barrier layer; a layer of semiconductor material forming a quantum well layer; a further layer of dielectric material forming a second tunnelling barrier layer; and a layer of electrode material forming a second main electrode. In this structure, a central potential well is defined between two potential barriers formed by the barrier layers. The central well has strongly quantized bound states. By varying the potential across the first and second main electrodes, the energy of electrons incident on the double-barrier can be tuned to match a bound state within the quantum well. The electrons may then tunnel through both barrier layers. In embodiments of the invention, the semiconductor device may be a diode in which the first and second main electrodes are the anode and cathode of the device, respectively, or vice versa.

The width of the quantum well layer is a critical dimension of the device as it defines the energies of the resonant states and their separation. The energy level of the first state and the energy separations to the next excited states are critical parameters. Electron scattering within the well may be reduced by reducing the thickness of the well, and such reductions can be used to tune the performance characteristics of the device. In the fabrication of devices embodying the invention, this dimension may be precisely controlled as it is determined by the thickness of a deposited layer. Preferably, the thickness of the quantum well layer is of the order of 1 to 4 nm.

This configuration is in contrast to that shown in US 6765303, in which the quantum states are formed within a fin structure, making it more difficult to control the width, particularly at such small dimensions. Devices embodying the invention are suitable for incorporation in

FinFET process flows, and FinFETs are expected to become increasingly mainstream technology for all CMOS applications.

In preferred embodiments, a gate dielectric layer is provided over the second main electrode layer, and a layer of electrode material forming a gate electrode is provided over the gate dielectric layer, thereby forming a transistor employing resonant tunneling principles in which the gate is operable to switch the transistor between resonant states. This configuration is able to provide high drive currents as well as low currents when the transistor is switched off.

Thus, instead of a channel-accommodating region under the gate, a double- barrier semiconductor structure is provided which is able to transmit current under resonant conditions. Preferably, the gate electrode extends around and over the top of the fin, from one side thereof to the other. Provision of a gate surrounding the fin in this manner permits highly effective tuning of the Fermi level with respect to the quantum states within the well, owing to its coverage of a large area over the underlying layers.

Use of the resonant tunneling effect facilitates the manufacture of transistors with multiple levels of conduction as opposed to only having an on and an off state. These levels are defined by the energy levels present in the quantum well. The first and second main electrodes may extend longitudinally (with respect to the direction of elongation of the fin) beyond respective, opposite sides of the gate electrode to provide respective contact areas for those main electrodes. Alternatively, the first and second main electrodes may extend longitudinally beyond the same side of the gate electrode to provide contact areas.

The present invention also provides a method of manufacturing a semiconductor device, comprising the steps of:

(a) providing an insulating substrate having a top surface;

(b) forming a fin of electrode material on the top surface of the insulating substrate;

(c) successively depositing layers on the fin in a stack comprising: a layer of dielectric material forming a first tunnelling barrier layer; a layer of semiconductor material forming a quantum well layer; a further layer of dielectric material forming a second tunnelling barrier layer; and a layer of electrode material; and

(d) patterning the layers so as to expose a portion of the fin to provide a contact area for a first main electrode of the device formed by the fin. In a preferred embodiment of the invention, a transistor structure is formed by including further steps after step (c) and before step (d) of:

(e) depositing a gate dielectric layer over the electrode layer; and (f) depositing a layer of gate electrode material over the gate dielectric layer, wherein step (d) also includes patterning the layers so as to expose a portion of the layer of electrode material to provide a contact area for a second main electrode of the device.

The first and second main electrodes represent the source and drain electrodes, respectively, in the finished device, or vice versa.

Embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein:

Figures 1 to 3 are energy diagrams representing a double-barrier tunnel junction at different bias conditions;

Figures 4 and 5 are a cross-sectional transverse side view and a longitudinal side view, respectively, of a transistor device embodying the invention;

Figure 6 is a longitudinal side view of an embodiment having an alternative configuration to that of Figure 5; and

Figures 7 and 8 are a transverse cross-sectional side view and a longitudinal side view, respectively, of a diode device embodying the invention.

It should be noted that the figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

The resonant tunneling effect is described for example in a paper entitled "Long Journey into Tunneling", by Leo Esaki, Reviews of Modern Physics, Vol. 46, No. 2, April 1974, pages 237 to 244. Figures 1 to 3 herein illustrate the concept of resonant tunneling in a double-barrier junction. Each Figure is an energy diagram plotting electron energy against distance measured transversely to the planes of the layers forming the junction.

Figure 1 represents the situation with no voltage applied across the junction. Two potential barriers 1 ,5 define a quantum well 3 therebetween. The narrow central potential well has weakly quantized bound states, the energies of which are denoted by Ei and E₂ in Figure 1. E_F denotes the Fermi energy level within an electrode at one side of the barrier. By varying the potential across the barrier, this Fermi level can be tuned to match a loosely bound quantum state within the quantum well. When this matching occurs and the energy of incident electrons coincides with one of the bound states in the well, the electrons are able to tunnel through both barriers without any attenuation. In Figures 2 and 3, the applied potential is such that the Fermi level matches energies Ei and E₂, respectively, and resonant transmission is achieved. The configuration of a transistor device embodying the invention and a process for its manufacture will now be described with reference to Figures 4 and 5. The device 2 has a concentric structure formed by deposition of successive layers on a fin 4. Initially, fin 4 is formed on an insulating substrate 6. The substrate may for example consist of an oxide layer over a silicon substrate. The oxide layer may have a thickness of about 100nm to 500nm, for example. It will be appreciated that this insulating layer may be formed of dielectric materials other than silicon oxide.

Fin 4 is formed in a known manner by defining a photoresist mask and etching a semiconductor layer with a suitable conventional anisotropic agent. The layer may be formed of monocrystalline silicon, polysilicon or another conductive material. When formed of semiconductor material, the fin is doped by implantation or by inclusion of a dopant during deposition of the layer from which it is derived, at concentration of around 1x10²⁰ atoms/cm³. Fin 4 forms the source electrode of the device in this example. A first dielectric layer is then deposited over the top and side walls of the fin. This layer forms a first barrier layer 8 in the finished device and may be 1 to 3 nm thick, for example. Next, a layer 10 of doped semiconductor material is deposited over the fin, again having a thickness in the range 1 to

3nm. This layer forms the quantum well layer of the finished device.

A further deposition process is then carried out to form a second barrier layer 12, in the form of a dielectric layer around 1 to 3nm thick. Each barrier layer may be formed from silicon dioxide, for example, or a material with a higher energy band gap than silicon.

A layer of electrode material, such as doped polysilicon for example, is then deposited to form the drain electrode 14 of the finished device. Doped silicon may be used instead, or another doped semiconductor material with band gap alignment to silicon. This layer may be around 3 to 10nm thick, and doped at a concentration of around 5x10¹⁹ to 10²⁰ atoms/cm³. A further dielectric layer 16 is now deposited which forms the gate dielectric in the finished device and may be around 1 nm thick. It may be formed of silicon dioxide, silicon oxynitride, or any other high-k materials. The final layer of the stack shown in Figure 4 is a layer of gate electrode material 18, formed of doped polysilicon for example, and this layer may be around 50nm thick, and doped at a concentration of around 2x10²⁰ atoms/cm³.

Instead of doped polysilicon, it will be appreciated that an ohmic metal contact may form the gate electrode. Uniform or complementary dopant types may be used for the device electrodes, depending on the voltages required to set the transistor in resonant conditions.

Successive masked etching processes are then carried out to expose the drain electrode 14 to one side of the gate electrode 18, and the source electrode 4 to the other side of the gate electrode, as shown in Figure 5.

Viewed transversely to the fin, the gate electrode extends around all three sides of the fin.

It will be appreciated that the main electrode described above as the source electrode could be the drain electrode instead and vice versa. In the finished device, dielectric layers 8 and 12 form the barriers of a double-barrier tunnel junction, with layer 10 forming a quantum well therebetween. In operation of the device, the energy levels in the double-barrier structure may be varied by applying a potential to the gate electrode 18 between the source electrode and drain electrode 14.

Electrode material is subsequently deposited to provide contacts with the exposed surfaces of the source and drain electrodes.

In the alternative embodiment shown in Figure 6, the source and drain electrodes 4,14 extend to the same side of the gate electrode 18.

Figures 7 and 8 show transverse cross-sectional and longitudinal side views of a resonant tunneling diode 2' fabricated in accordance with the invention. Its structure is similar to that of the transistor device discussed above, except that gate electrode layer 18 and the underlying insulating layer 16 are omitted. Fin 4 and electrode layer 14 instead form the anode and cathode of the device respectively, or vice versa, depending on the conductivity types of the dopants employed in these regions. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the art, and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

1. A semiconductor device (2,2') including: a fin (4) of electrode material forming a first main electrode on an insulating substrate (6); and a stack of layers formed on the fin comprising: a layer (8) of dielectric material forming a first tunneling barrier layer; a layer (10) of semiconductor material forming a quantum well layer; a further layer (12) of dielectric material forming a second tunneling barrier layer; and a layer (14) of electrode material forming a second main electrode.

2. A device of claim 1 including a gate dielectric layer (16) over the second main electrode layer, and a layer (18) of electrode material forming a gate electrode over the gate dielectric layer.

3. A device of claim 2 wherein the gate electrode (18) extends over the top of the fin (4), from one side of the fin to the other.

4. A device of claim 2 or claim 3 wherein the first and second main electrodes (4,14) extend longitudinally beyond respective, opposite sides of the gate electrode (18) to provide respective contact areas.

5. A device of claim 2 or claim 3 wherein the first and second main electrodes (4,14) extend longitudinally beyond the same side of the gate electrode (18) to provide respective contact areas.

6. A method of manufacturing a semiconductor device (2,2'), comprising the steps of: (a) providing an insulating substrate (6) having a top surface;

(b) forming a fin (4) of electrode material on the top surface of the insulating substrate;

(c) successively depositing layers on the fin in a stack comprising: a layer (8) of dielectric material forming a first tunneling barrier layer; a layer (10) of semiconductor material forming a quantum well layer; a further layer (12) of dielectric material forming a second tunneling barrier layer; and a layer (14) of electrode material; and

(d) patterning the layers so as to expose a portion of the fin (4) to provide a contact area for a first main electrode formed by the fin.

7. A method of claim 6 including the steps after step (c) and before step (d) of:

(e) depositing a gate dielectric layer (16) over the electrode layer; and

(f) depositing a layer of gate electrode material (18) over the gate dielectric layer, wherein step (d) also includes patterning the layers so as to expose a portion of the layer of electrode material to provide a contact area for a second main electrode of the device.

8. An integrated circuit device including a semiconductor device (2,2') of any of claims 1 to 5or a semiconductor device (2,2') manufactured in accordance with a method of claims 6 or 7.