WO2009155067A3 - Method for forming fine pitch structures - Google Patents
Method for forming fine pitch structures Download PDFInfo
- Publication number
- WO2009155067A3 WO2009155067A3 PCT/US2009/045515 US2009045515W WO2009155067A3 WO 2009155067 A3 WO2009155067 A3 WO 2009155067A3 US 2009045515 W US2009045515 W US 2009045515W WO 2009155067 A3 WO2009155067 A3 WO 2009155067A3
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- WO
- WIPO (PCT)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP09767378A EP2304771A2 (en) | 2008-06-17 | 2009-05-28 | Method for forming fine pitch structures |
CN200980122694.3A CN102067282B (en) | 2008-06-17 | 2009-05-28 | Method for forming fine pitch structures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/140,928 | 2008-06-17 | ||
US12/140,928 US8404600B2 (en) | 2008-06-17 | 2008-06-17 | Method for forming fine pitch structures |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009155067A2 WO2009155067A2 (en) | 2009-12-23 |
WO2009155067A3 true WO2009155067A3 (en) | 2010-02-25 |
Family
ID=41415184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/045515 WO2009155067A2 (en) | 2008-06-17 | 2009-05-28 | Method for forming fine pitch structures |
Country Status (6)
Country | Link |
---|---|
US (3) | US8404600B2 (en) |
EP (1) | EP2304771A2 (en) |
KR (1) | KR20110030599A (en) |
CN (1) | CN102067282B (en) |
TW (1) | TWI518740B (en) |
WO (1) | WO2009155067A2 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2942738B1 (en) * | 2009-03-03 | 2016-04-15 | Commissariat A L'energie Atomique | METHOD FOR MANUFACTURING A MOLD FOR NANO-PRINTING LITHOGRAPHY |
KR20130002527A (en) * | 2011-06-29 | 2013-01-08 | 엘지이노텍 주식회사 | Method of manufacturing a nanowire |
US8791023B2 (en) * | 2012-08-31 | 2014-07-29 | Eastman Kodak Company | Patterned thin film dielectric layer formation |
US20140065838A1 (en) * | 2012-08-31 | 2014-03-06 | Carolyn R. Ellinger | Thin film dielectric layer formation |
US8927434B2 (en) * | 2012-08-31 | 2015-01-06 | Eastman Kodak Company | Patterned thin film dielectric stack formation |
EP3050086A4 (en) * | 2013-09-27 | 2017-05-03 | Intel Corporation | Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects |
CN110060972B (en) | 2013-09-27 | 2024-02-23 | 英特尔公司 | Self-aligned via and plug patterning for back end of line (BEOL) interconnects |
CN105493250B (en) | 2013-09-27 | 2018-12-18 | 英特尔公司 | Subtractive method self-aligned via hole and plug patterning for back segment (BEOL) interconnection |
KR102171263B1 (en) * | 2014-08-21 | 2020-10-28 | 삼성전자 주식회사 | Integrated circuit device having single crystal silicon thin film and method of manufacturing the same |
US10043672B2 (en) * | 2016-03-29 | 2018-08-07 | Lam Research Corporation | Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask |
US9607886B1 (en) * | 2016-06-30 | 2017-03-28 | International Business Machines Corporation | Self aligned conductive lines with relaxed overlay |
US9941118B2 (en) * | 2016-08-22 | 2018-04-10 | International Business Machines Corporation | Dense vertical nanosheet |
US10083842B2 (en) * | 2016-11-16 | 2018-09-25 | Tokyo Electron Limited | Methods of sub-resolution substrate patterning |
US10515896B2 (en) * | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02143527A (en) * | 1988-11-25 | 1990-06-01 | Sony Corp | Wiring formation |
JPH033375A (en) * | 1989-05-31 | 1991-01-09 | Fujitsu Ltd | Manufacture of oxide superconducting device |
US20080057687A1 (en) * | 2006-09-01 | 2008-03-06 | Ngimat Co., A Georgia Corporation | Selective area deposition and devices formed therefrom |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328810A (en) | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US6518189B1 (en) | 1995-11-15 | 2003-02-11 | Regents Of The University Of Minnesota | Method and apparatus for high density nanostructures |
US5772905A (en) | 1995-11-15 | 1998-06-30 | Regents Of The University Of Minnesota | Nanoimprint lithography |
JP3189773B2 (en) | 1998-01-09 | 2001-07-16 | 三菱電機株式会社 | Method of forming resist pattern, method of manufacturing semiconductor device using the same, and semiconductor device |
IL131037A (en) * | 1999-07-22 | 2004-06-20 | Israel Atomic Energy Comm | Method for making threedimensional photonic band-gap crystals |
US6667237B1 (en) | 2000-10-12 | 2003-12-23 | Vram Technologies, Llc | Method and apparatus for patterning fine dimensions |
US6746825B2 (en) | 2001-10-05 | 2004-06-08 | Wisconsin Alumni Research Foundation | Guided self-assembly of block copolymer films on interferometrically nanopatterned substrates |
JP3967114B2 (en) | 2001-11-22 | 2007-08-29 | 株式会社東芝 | Processing method |
US20080105646A1 (en) * | 2002-05-07 | 2008-05-08 | Microfabrica Inc. | Multi-step Release Method for Electrochemically Fabricated Structures |
US20050032375A1 (en) * | 2003-05-07 | 2005-02-10 | Microfabrica Inc. | Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization |
US6638879B2 (en) * | 2001-12-06 | 2003-10-28 | Macronix International Co., Ltd. | Method for forming nitride spacer by using atomic layer deposition |
TW576864B (en) | 2001-12-28 | 2004-02-21 | Toshiba Corp | Method for manufacturing a light-emitting device |
AU2003234397A1 (en) * | 2002-05-07 | 2003-11-11 | Memgen Corporation | Methods of and apparatus for electrochemically fabricating structures |
US6911400B2 (en) | 2002-11-05 | 2005-06-28 | International Business Machines Corporation | Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same |
US20080283405A1 (en) * | 2003-05-01 | 2008-11-20 | Johns Hopkins University | Method for Producing Patterned Structures by Printing a Surfactant Resist on a Substrate for Electrodeposition |
US7258895B2 (en) * | 2003-08-06 | 2007-08-21 | Micron Technology, Inc. | Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate |
US7018917B2 (en) * | 2003-11-20 | 2006-03-28 | Asm International N.V. | Multilayer metallization |
US7141866B1 (en) * | 2004-04-16 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | Apparatus for imprinting lithography and fabrication thereof |
US7268065B2 (en) | 2004-06-18 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing metal-silicide features |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7208379B2 (en) | 2004-11-29 | 2007-04-24 | Texas Instruments Incorporated | Pitch multiplication process |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
KR100674970B1 (en) * | 2005-04-21 | 2007-01-26 | 삼성전자주식회사 | Method for fabricating small pitch patterns by using double spacers |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
WO2008136882A2 (en) * | 2007-02-14 | 2008-11-13 | The Board Of Trustees Of The Leland Stanford Junior University | Fabrication method of size-controlled, spatially distributed nanostructures by atomic layer deposition |
US8215074B2 (en) * | 2008-02-05 | 2012-07-10 | International Business Machines Corporation | Pattern formation employing self-assembled material |
US8262916B1 (en) * | 2009-06-30 | 2012-09-11 | Microfabrica Inc. | Enhanced methods for at least partial in situ release of sacrificial material from cavities or channels and/or sealing of etching holes during fabrication of multi-layer microscale or millimeter-scale complex three-dimensional structures |
-
2008
- 2008-06-17 US US12/140,928 patent/US8404600B2/en active Active
-
2009
- 2009-05-28 WO PCT/US2009/045515 patent/WO2009155067A2/en active Application Filing
- 2009-05-28 CN CN200980122694.3A patent/CN102067282B/en active Active
- 2009-05-28 EP EP09767378A patent/EP2304771A2/en not_active Withdrawn
- 2009-05-28 KR KR1020117001126A patent/KR20110030599A/en active IP Right Grant
- 2009-06-09 TW TW098119261A patent/TWI518740B/en active
-
2013
- 2013-03-11 US US13/794,084 patent/US8846537B2/en active Active
-
2014
- 2014-09-26 US US14/497,773 patent/US20150011085A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02143527A (en) * | 1988-11-25 | 1990-06-01 | Sony Corp | Wiring formation |
JPH033375A (en) * | 1989-05-31 | 1991-01-09 | Fujitsu Ltd | Manufacture of oxide superconducting device |
US20080057687A1 (en) * | 2006-09-01 | 2008-03-06 | Ngimat Co., A Georgia Corporation | Selective area deposition and devices formed therefrom |
Also Published As
Publication number | Publication date |
---|---|
WO2009155067A2 (en) | 2009-12-23 |
TWI518740B (en) | 2016-01-21 |
CN102067282A (en) | 2011-05-18 |
CN102067282B (en) | 2013-08-14 |
EP2304771A2 (en) | 2011-04-06 |
KR20110030599A (en) | 2011-03-23 |
TW201003739A (en) | 2010-01-16 |
US8404600B2 (en) | 2013-03-26 |
US20150011085A1 (en) | 2015-01-08 |
US20130252420A1 (en) | 2013-09-26 |
US20090311867A1 (en) | 2009-12-17 |
US8846537B2 (en) | 2014-09-30 |
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