WO2010022009A3 - Process for through silicon via filling - Google Patents

Process for through silicon via filling Download PDF

Info

Publication number
WO2010022009A3
WO2010022009A3 PCT/US2009/054094 US2009054094W WO2010022009A3 WO 2010022009 A3 WO2010022009 A3 WO 2010022009A3 US 2009054094 W US2009054094 W US 2009054094W WO 2010022009 A3 WO2010022009 A3 WO 2010022009A3
Authority
WO
WIPO (PCT)
Prior art keywords
silicon via
copper
via filling
silicon
micrometers
Prior art date
Application number
PCT/US2009/054094
Other languages
French (fr)
Other versions
WO2010022009A2 (en
Inventor
Jonathan D. Reid
Katie Qun Wang
Mark J. Willey
Original Assignee
Novellus Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novellus Systems, Inc. filed Critical Novellus Systems, Inc.
Priority to KR1020107026766A priority Critical patent/KR101105485B1/en
Priority to CN200980132002.3A priority patent/CN102124551B/en
Publication of WO2010022009A2 publication Critical patent/WO2010022009A2/en
Publication of WO2010022009A3 publication Critical patent/WO2010022009A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/12Process control or regulation
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias.
PCT/US2009/054094 2008-08-18 2009-08-17 Process for through silicon via filling WO2010022009A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020107026766A KR101105485B1 (en) 2008-08-18 2009-08-17 Process for through silicon via filling
CN200980132002.3A CN102124551B (en) 2008-08-18 2009-08-17 Silicon through hole fill process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/193,644 2008-08-18
US12/193,644 US7776741B2 (en) 2008-08-18 2008-08-18 Process for through silicon via filing

Publications (2)

Publication Number Publication Date
WO2010022009A2 WO2010022009A2 (en) 2010-02-25
WO2010022009A3 true WO2010022009A3 (en) 2010-05-14

Family

ID=41681550

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/054094 WO2010022009A2 (en) 2008-08-18 2009-08-17 Process for through silicon via filling

Country Status (5)

Country Link
US (3) US7776741B2 (en)
KR (1) KR101105485B1 (en)
CN (2) CN102124551B (en)
TW (1) TWI474436B (en)
WO (1) WO2010022009A2 (en)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7776741B2 (en) 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US9677188B2 (en) 2009-06-17 2017-06-13 Novellus Systems, Inc. Electrofill vacuum plating cell
US8268155B1 (en) 2009-10-05 2012-09-18 Novellus Systems, Inc. Copper electroplating solutions with halides
US10472730B2 (en) 2009-10-12 2019-11-12 Novellus Systems, Inc. Electrolyte concentration control system for high rate electroplating
US9109295B2 (en) 2009-10-12 2015-08-18 Novellus Systems, Inc. Electrolyte concentration control system for high rate electroplating
FR2958300B1 (en) * 2010-03-31 2012-05-04 Snecma DEVICE FOR CONTROLLING PHYSICAL CHARACTERISTICS OF A METAL ELECTRODEPOSITION BATH.
EP2378548A1 (en) 2010-04-19 2011-10-19 Nanda Technologies GmbH Methods of processing and inspecting semiconductor substrates
US8992757B2 (en) 2010-05-19 2015-03-31 Novellus Systems, Inc. Through silicon via filling using an electrolyte with a dual state inhibitor
US9190371B2 (en) 2010-12-21 2015-11-17 Moon J. Kim Self-organizing network with chip package having multiple interconnection configurations
US9816193B2 (en) 2011-01-07 2017-11-14 Novellus Systems, Inc. Configuration and method of operation of an electrodeposition system for improved process stability and performance
TWI456726B (en) 2011-01-24 2014-10-11 Ind Tech Res Inst Interconnection structure, apparatus therewith, circuit structure therewith, and method to prevent an interconnection structure from emi
WO2012103357A1 (en) 2011-01-26 2012-08-02 Enthone Inc. Process for filling vias in the microelectronics
US8970043B2 (en) 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
JP5698558B2 (en) * 2011-02-21 2015-04-08 東京エレクトロン株式会社 Substrate processing method and storage medium
EP2684213A4 (en) 2011-03-11 2014-11-26 Basf Se Method for forming through-base wafer vias
US8575028B2 (en) 2011-04-15 2013-11-05 Novellus Systems, Inc. Method and apparatus for filling interconnect structures
US8753981B2 (en) 2011-04-22 2014-06-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
TWI436466B (en) * 2011-04-27 2014-05-01 Ind Tech Res Inst Filled through-silicon via and the fabrication method thereof
EP2533276A1 (en) * 2011-06-07 2012-12-12 Imec Method for detecting embedded voids in a semiconductor substrate
EP2535441A1 (en) 2011-06-14 2012-12-19 Atotech Deutschland GmbH Copper filled opening with a cap layer
CN103000567B (en) * 2011-09-13 2015-07-22 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device
CN102443828B (en) * 2011-09-23 2014-11-19 上海华力微电子有限公司 Method for electro-coppering in through hole of semiconductor silicon chip
CN102446829A (en) * 2011-09-23 2012-05-09 上海华力微电子有限公司 Device for carrying out electroplating copper in through hole of silicon wafer
US20130075268A1 (en) * 2011-09-28 2013-03-28 Micron Technology, Inc. Methods of Forming Through-Substrate Vias
KR102147003B1 (en) 2011-12-12 2020-08-24 노벨러스 시스템즈, 인코포레이티드 Monitoring leveler concentrations in electroplating solutions
JP5851233B2 (en) 2011-12-22 2016-02-03 ローム・アンド・ハース電子材料株式会社 Electrolytic copper plating solution and electrolytic copper plating method
KR20130077627A (en) * 2011-12-29 2013-07-09 에스케이하이닉스 주식회사 Semicondcutor apparatus and method of manufacturing the same
US8664060B2 (en) 2012-02-07 2014-03-04 United Microelectronics Corp. Semiconductor structure and method of fabricating the same
CN103295915B (en) * 2012-03-05 2016-02-10 北京北方微电子基地设备工艺研究中心有限责任公司 The manufacture method of TSV keyset and TSV keyset
US8754531B2 (en) 2012-03-14 2014-06-17 Nanya Technology Corp. Through-silicon via with a non-continuous dielectric layer
US20130249096A1 (en) * 2012-03-23 2013-09-26 Texas Instruments Incorporated Through silicon via filling
US10665503B2 (en) * 2012-04-26 2020-05-26 Applied Materials, Inc. Semiconductor reflow processing for feature fill
US9816196B2 (en) 2012-04-27 2017-11-14 Novellus Systems, Inc. Method and apparatus for electroplating semiconductor wafer when controlling cations in electrolyte
FR2991108A1 (en) * 2012-05-24 2013-11-29 St Microelectronics Sa BLINDED COPLANAR LINE
US9330975B2 (en) 2012-05-31 2016-05-03 Micron Technology, Inc. Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
CN103811413B (en) * 2012-11-15 2016-06-08 上海华虹宏力半导体制造有限公司 The method of manufacturing technology of semiconductor chip
US9034769B2 (en) 2012-12-12 2015-05-19 Micron Technology, Inc. Methods of selectively removing a substrate material
US9613833B2 (en) 2013-02-20 2017-04-04 Novellus Systems, Inc. Methods and apparatus for wetting pretreatment for through resist metal plating
US9070750B2 (en) 2013-03-06 2015-06-30 Novellus Systems, Inc. Methods for reducing metal oxide surfaces to modified metal surfaces using a gaseous reducing environment
US9865501B2 (en) 2013-03-06 2018-01-09 Lam Research Corporation Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
US20140262794A1 (en) * 2013-03-15 2014-09-18 Applied Materials, Inc. Electrochemical deposition processes for semiconductor wafers
TWI510680B (en) * 2013-03-15 2015-12-01 Omg Electronic Chemicals Llc Copper plating solutions and method of making and using such solutions
KR101290670B1 (en) * 2013-06-03 2013-07-29 구본술 A integrated antenna manufacturing method has the plating reliability enhancement function
US9689083B2 (en) 2013-06-14 2017-06-27 Lam Research Corporation TSV bath evaluation using field versus feature contrast
US20150053565A1 (en) * 2013-08-26 2015-02-26 Lam Research Corporation Bottom-up fill in damascene features
US9318413B2 (en) 2013-10-29 2016-04-19 Globalfoundries Inc. Integrated circuit structure with metal cap and methods of fabrication
US9318414B2 (en) 2013-10-29 2016-04-19 Globalfoundries Inc. Integrated circuit structure with through-semiconductor via
US9435049B2 (en) 2013-11-20 2016-09-06 Lam Research Corporation Alkaline pretreatment for electroplating
CN103668356B (en) * 2013-12-17 2016-04-13 上海交通大学 Fe is added in copper-connection copper sulfate bath 2+and Fe 3+electro-plating method
CN103887232B (en) * 2014-04-04 2016-08-24 华进半导体封装先导技术研发中心有限公司 The method improving the metal filled uniformity of TSV
US9469912B2 (en) 2014-04-21 2016-10-18 Lam Research Corporation Pretreatment method for photoresist wafer processing
CN106574390A (en) * 2014-04-25 2017-04-19 株式会社杰希优 High-speed filling method for copper
US9809891B2 (en) 2014-06-30 2017-11-07 Rohm And Haas Electronic Materials Llc Plating method
US9472377B2 (en) 2014-10-17 2016-10-18 Lam Research Corporation Method and apparatus for characterizing metal oxide reduction
US9617648B2 (en) 2015-03-04 2017-04-11 Lam Research Corporation Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias
CN106486415B (en) 2015-09-01 2020-03-31 中芯国际集成电路制造(上海)有限公司 Method for manufacturing interconnection structure
US10329683B2 (en) 2016-11-03 2019-06-25 Lam Research Corporation Process for optimizing cobalt electrofill using sacrificial oxidants
JP6726610B2 (en) * 2016-12-13 2020-07-22 東京エレクトロン株式会社 Etching method and substrate processing system
US9991161B1 (en) 2017-03-07 2018-06-05 Hong Kong Applied Science and Technology Research Institute Company Limited Alternate plating and etching processes for through hole filling
US10103056B2 (en) * 2017-03-08 2018-10-16 Lam Research Corporation Methods for wet metal seed deposition for bottom up gapfill of features
US10443146B2 (en) 2017-03-30 2019-10-15 Lam Research Corporation Monitoring surface oxide on seed layers during electroplating
US10157842B1 (en) 2017-05-31 2018-12-18 International Business Machines Corporation Semiconductor device including superconducting metal through-silicon-vias and method of manufacturing the same
US10692735B2 (en) 2017-07-28 2020-06-23 Lam Research Corporation Electro-oxidative metal removal in through mask interconnect fabrication
CN109385650A (en) * 2017-08-09 2019-02-26 中南大学 The manufacturing method and its device of a kind of through-silicon via structure, through-silicon via structure
US11600713B2 (en) * 2018-05-30 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102060360B1 (en) * 2018-07-20 2019-12-30 한양대학교 에리카산학협력단 Method for forming bumps on a tsv substrate
US11437250B2 (en) * 2018-11-15 2022-09-06 Tokyo Electron Limited Processing system and platform for wet atomic layer etching using self-limiting and solubility-limited reactions
US10982335B2 (en) * 2018-11-15 2021-04-20 Tokyo Electron Limited Wet atomic layer etching using self-limiting and solubility-limited reactions
US20220216104A1 (en) * 2019-02-14 2022-07-07 Lam Research Corporation Gold through silicon mask plating
US11915941B2 (en) 2021-02-11 2024-02-27 Tokyo Electron Limited Dynamically adjusted purge timing in wet atomic layer etching
CN113078131A (en) * 2021-03-23 2021-07-06 浙江集迈科微电子有限公司 TSV structure and TSV electroplating process
US11802342B2 (en) 2021-10-19 2023-10-31 Tokyo Electron Limited Methods for wet atomic layer etching of ruthenium
US11866831B2 (en) 2021-11-09 2024-01-09 Tokyo Electron Limited Methods for wet atomic layer etching of copper

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223858A (en) * 1996-02-15 1997-08-26 Fujitsu Ltd Manufacture of printed wiring board
KR19990015599A (en) * 1997-08-07 1999-03-05 윤종용 Method of forming dual damascene metal wiring layer of semiconductor device using electroless plating
KR20020077811A (en) * 2001-04-02 2002-10-14 미쓰비시덴키 가부시키가이샤 Chemical processing system, plating system and chemical processing method
JP2003113479A (en) * 2001-10-04 2003-04-18 Chang Chun Petrochemical Co Ltd Method for forming crystal layer for copper interconnection of integrated circuit

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USH36H (en) 1981-10-13 1986-03-04 At&T Bell Laboratories Electroplating process with inert anodes
US5858196A (en) 1996-01-31 1999-01-12 Kawasaki Steel Corporation Method of controlling component concentration of plating solution in continuous electroplating
US7556722B2 (en) 1996-11-22 2009-07-07 Metzger Hubert F Electroplating apparatus
WO1999054527A2 (en) 1998-04-21 1999-10-28 Applied Materials, Inc. Electro-chemical deposition system and method of electroplating on substrates
US6113771A (en) 1998-04-21 2000-09-05 Applied Materials, Inc. Electro deposition chemistry
PL344529A1 (en) 1998-05-16 2001-11-05 Blasberg Oberflaechentech Method for electro copperplating substrates
MY144573A (en) * 1998-09-14 2011-10-14 Ibiden Co Ltd Printed circuit board and method for its production
KR20020092444A (en) * 2001-02-23 2002-12-11 가부시키 가이샤 에바라 세이사꾸쇼 Copper-plating solution, plating method and plating apparatus
WO2002090623A1 (en) * 2001-05-09 2002-11-14 Ebara-Udylite Co., Ltd. Copper plating bath and method for plating substrate by using the same
JP3695703B2 (en) * 2001-10-25 2005-09-14 株式会社日立製作所 Electroplating method, electroplating apparatus and semiconductor device manufacturing method and manufacturing apparatus
JP2003293193A (en) * 2002-04-02 2003-10-15 Nec Electronics Corp Method for forming fine circuit wiring and apparatus used for the same
CN1679154A (en) * 2002-05-16 2005-10-05 新加坡国立大学 Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
JP3819840B2 (en) 2002-07-17 2006-09-13 大日本スクリーン製造株式会社 Plating apparatus and plating method
EP1574600A4 (en) 2002-10-11 2006-11-15 Electroplating Eng Cup type plating equipment
CN1314838C (en) * 2002-12-11 2007-05-09 财团法人工业技术研究院 Making process of electrolytic copper foil with great high-temperature elongation
US7827930B2 (en) * 2004-01-26 2010-11-09 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7405157B1 (en) * 2003-11-10 2008-07-29 Novellus Systems, Inc. Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US7794573B2 (en) 2003-12-05 2010-09-14 Semitool, Inc. Systems and methods for electrochemically processing microfeature workpieces
JP4540981B2 (en) * 2003-12-25 2010-09-08 株式会社荏原製作所 Plating method
TWI320062B (en) * 2004-03-31 2010-02-01 Composition for copper electroplating solution
CN1290160C (en) * 2004-09-24 2006-12-13 清华大学 Metallization method for producing integrated circuit copper interconnecting wire by separating bipolar acid chemical plating
CN1773675A (en) * 2004-11-10 2006-05-17 北京大学 Process for producing radio frequency inductance
JP2007051362A (en) 2005-07-19 2007-03-01 Ebara Corp Plating apparatus and method for managing plating liquid
US7631423B2 (en) * 2006-02-13 2009-12-15 Sanmina-Sci Corporation Method and process for embedding electrically conductive elements in a dielectric layer
TWI341554B (en) 2007-08-02 2011-05-01 Enthone Copper metallization of through silicon via
US20090038947A1 (en) 2007-08-07 2009-02-12 Emat Technology, Llc. Electroplating aqueous solution and method of making and using same
US7776741B2 (en) 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing
US9109295B2 (en) 2009-10-12 2015-08-18 Novellus Systems, Inc. Electrolyte concentration control system for high rate electroplating

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223858A (en) * 1996-02-15 1997-08-26 Fujitsu Ltd Manufacture of printed wiring board
KR19990015599A (en) * 1997-08-07 1999-03-05 윤종용 Method of forming dual damascene metal wiring layer of semiconductor device using electroless plating
KR20020077811A (en) * 2001-04-02 2002-10-14 미쓰비시덴키 가부시키가이샤 Chemical processing system, plating system and chemical processing method
JP2003113479A (en) * 2001-10-04 2003-04-18 Chang Chun Petrochemical Co Ltd Method for forming crystal layer for copper interconnection of integrated circuit

Also Published As

Publication number Publication date
KR101105485B1 (en) 2012-01-13
CN105845558A (en) 2016-08-10
KR20110022571A (en) 2011-03-07
TWI474436B (en) 2015-02-21
US20120031768A1 (en) 2012-02-09
TW201027668A (en) 2010-07-16
US8043967B2 (en) 2011-10-25
US7776741B2 (en) 2010-08-17
CN102124551B (en) 2016-06-01
WO2010022009A2 (en) 2010-02-25
CN102124551A (en) 2011-07-13
US20100041226A1 (en) 2010-02-18
US20100200412A1 (en) 2010-08-12
CN105845558B (en) 2021-01-29
US8722539B2 (en) 2014-05-13

Similar Documents

Publication Publication Date Title
WO2010022009A3 (en) Process for through silicon via filling
WO2010148147A3 (en) Apparatus for wetting pretreatment for enhanced damascene metal filling
WO2010085685A3 (en) Diffusion barrier layers
HK1132768A1 (en) Method and compositions for direct copper plating and filling to form interconnects in the fabrication of semiconductor devices
TW200741915A (en) Method for fabricating last level corper-to-C4 connection with interfacial cap structure
EP2779224A3 (en) Methods for producing interconnects in semiconductor devices
TW200723448A (en) Interconnect structure and fabrication method thereof and semiconductor device
MY153822A (en) Method f'or manufacturing printed wiring board
GB2442634A (en) Carbon nanotube interconnect contacts
SG159451A1 (en) Reliable interconnects
TW200917398A (en) Methods for forming a through via
WO2012082956A3 (en) Methods for metal plating and related devices
WO2011149965A3 (en) Copper filling of through silicon vias
TW200746379A (en) Contact surrounded by passivation and polyimide and method therefor
EP2916351A3 (en) Embedded die flip-chip package assembly
WO2009057422A1 (en) Copper anode or phosphorus-containing copper anode, method for electroplating copper on semiconductor wafer, and semiconductor wafer with particle not significantly deposited thereon
MX352763B (en) Analytical aid with hydrophilic coating that contains nanoparticles with a silicon dioxide structure.
TW200943425A (en) ULSI microwiring member having ruthenium-plating layer on barrier layer
TW200746358A (en) Semiconductor interconnect having adjacent reservoir for bonding and method for formation
DE102008049069B8 (en) Optoelectronic module with a carrier substrate, at least one radiation-emitting semiconductor component and at least one electrical component and method for its production
TW200741923A (en) Method for forming reinforced interconnects on a substrate
WO2012095340A3 (en) Gravity based fluid trap
TW201211322A (en) Composition of copper electroplating solution
KR20160037800A (en) Method for manufacturing wiring structure, copper displacement plating solution, and wiring structure
Bae et al. Electroplating of copper using pulse-reverse electroplating method for SiP via filling

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980132002.3

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09808681

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase

Ref document number: 20107026766

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09808681

Country of ref document: EP

Kind code of ref document: A2