WO2010025786A1

WO2010025786A1 - Logic circuit for calculating crc test values

Info

Publication number: WO2010025786A1
Application number: PCT/EP2009/004427
Authority: WO
Inventors: Stephan Schultze
Original assignee: Robert Bosch Gmbh
Priority date: 2008-09-05
Filing date: 2009-06-19
Publication date: 2010-03-11
Also published as: DE102008045813A1

Abstract

The invention relates to a logic circuit for calculating a CRC test value of a message, wherein the CRC test value has a specifiable length. The logic circuit comprises an input (402) for receiving the message, an input (401) for receiving a freely specifiable CRC polynomial, calculation means (421-426, "&", "=1") for calculating a CRC test value of the message using the CRC polynomial and switching means (430), which connect the calculation means (421-426, "&", "=1") according to a length of the CRC polynomial in such a way that the length of the CRC test value corresponds to the length of the CRC polynomial. Therefore, a hardware circuit can be provided which permits the calculation of test values of different lengths while using any generator polynomials.

Description

324753

04.09.2008 - Kauth

Robert Bosch GmbH, Stuttgart

Logic circuit for calculating CRC test values

description

The present invention relates to a logic circuit for calculating CRC check values and to a use of such a circuit in a data transmission.

State of the art

The Cyclic Redundancy Check (CRC) is an information technology method for determining a check value for data (e.g., network traffic or a file) to detect errors in the transmission or duplication of data.

CRC check values are also commonly referred to as CRC checksums, although they are actually test division residuals rather than sums. In the CRC, a data block is modulo divided by a CRC polynomial. The remainder of the division represents the CRC check value.

CRC types are distinguished by the CRC polynomial used (generator polynomial). After the bit length of Polynomial is the length of the testable data block. There are known standard polynomials, such as:

CRC-CCITT (CRC-16): 0x11021 IBM-CRC-16: 0x18005

IEEE-802 CRC (CRC-32): 0xl04CllDB7 CRC32 / 4: 11EDC6F41 CAN-CRC: 0xC599 Bluetooth: 0x35

It is known CRC logic circuits using a shift register - typically a shift register with linear feedback LFSR (linear feedback ^'shift register) - realizing said XOR gate are provided between the individual bits of the register. The placement of the XOR gates depends on the coefficients of the corresponding antenna in the polynomial, which are 1. US 4,723,243 and US 6,253,346 Bl disclose dedicated circuits for calculating a CRC-32 checksum. However, these circuits are inflexible because they can only use a given generator polynomial, CRC-32 in the example given.

In particular, in certain areas of data transmission, it is necessary to be able to use different generator polynomials. These must be calculated either by implementing several hardware circuits or by software. Both options are complex. Furthermore, in situations where the necessary CRC polynomials are not yet known, no (fast) hardware circuits can be used. Instead, slow software solutions must be used. Starting from this state of the _. Technique a logic circuit for calculating a CRC check value of a message with the features of claim 1 is proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

Advantages of the invention

By means of the logic circuit according to the invention, a substantial acceleration of the calculation method can be achieved with great flexibility. The logic circuit is capable of using arbitrary CRC polynomials, the maximum bit number of the polynomial being limited only by the design of the circuit. In practice, however, it will be useful to set a maximum bit number of 32 or 64.

It is advantageous if the logic circuit provides an interface functionality, such as an API. This procedure allows for fast

Calculation of CRC test values, in particular of data blocks in a data telegram at variable positions. The logic circuit may be formed as an integrated circuit or part of an integrated circuit. You may ^• also designed as an ASIC or FPGA etc. In the prior art, logic circuits in most cases no longer consist of hard-wired logic, as in the past, but of flexibly programmable devices (FPGAs, EPLDs, ASICs, gate arrays, etc.). Depending on the type, these blocks do not contain any predetermined logic functionalities, but instead provide a kind of "logic building block ^11. By programming these blocks, a desired functionality can be specified. Conventional logic devices have a predetermined, manufacturing or type-related capacity. In many cases, logic modules are already present in existing circuits whose capacity is not yet fully occupied. In this case, the logic circuit according to the invention can be implemented particularly advantageously, since only small or no circuit-related changes are necessary. Thus, a cost saving can be achieved. During data transmission, the data blocks are transferred to the logic circuit, which then independently calculates the corresponding CRC test values. The transfer can for example be serial or parallel, via registers, etc.

The checksum of a data stream can be calculated in bits or bytes, etc., and attached to the data by the sender. The calculation of the checksum per se is preferably carried out by known methods, in particular

Use of shift registers for processing a bit stream, as described, for example, in the cited prior art. Conveniently, the most significant bit of the shift register is defined by the switching means. Advantageously, the switching means for this purpose at least one multiplexer, are passed to the at least two bits of the shift register. Furthermore, the calculating means expediently comprise at least one XOR gate. By means of XOR gates, a polynomial division can be implemented particularly easily in hardware. The length dependence can then be achieved, for example, by selecting one of the bits of the shift register via the multiplexer and writing it as Feedback is performed in the XOR block. For example, for a 32-bit checksum, the multiplexer requires five control inputs that select one of 2 ^A 5 (= 32) inputs as the CRC register bit to feed back. Alternatively, a chain of 31 AND gates could be used, with each AND gate having two inputs, each with a CRC register bit and a configurable bit. In this case one needs, for example, 31 control bits (instead of 5 control bits in comparison with a MUX), of which only exactly one AND gate is provided with a "1", all others have the value "0".

Preferably, the logic circuit has an input for receiving an initial value for the shift register. Depending on the CRC polynomial used, various initialization values have proved to be advantageous, which advantageously can also be fed to the logic circuit from the outside. For example, in CRC-16, after CCITT, the polynomial x ^A 16 + x ^A 12 + x ^A 5 + 1 is used as the seed "1" in each register bit. The starting value can also assume any value, in particular also "0".

Advantageously, at least one predetermined CRC polynomial is integrated. It is advisable to already firmly integrate the polynomials required for the intended purpose and / or the known polynomials mentioned in the description of the prior art into the circuit, whereby in particular the external circuit complexity can be reduced. In particular, a choice may be made to select one of the predetermined CRC polynomials for use. It is also possible to use only one predetermined CRC polynomial integrate, which, for example, is then used automatically when no freely definable CRC polynomial is applied to the input. It is advisable to also predetermine an initialization value for each predetermined CRC polynomial.

It is expedient if a length of the CRC polynomial can be specified externally. It is also possible to determine the length of the externally specified CRC polynomial within the circuit, but the external specification of the length can reduce the complexity of the circuit. By determining the length within the circuit, it is possible to reduce the external circuitry overhead.

It is particularly expedient if the logic circuit according to the invention is integrated in a communication controller. Communication controllers are used for data transmission and provide various functionality for data transmission. The additional integration of the logic circuit, an advantageous space savings can be achieved. It is understood that the logic circuit according to the invention can also be integrated into other logic modules.

It is equally advantageous if the logic circuit according to the invention is designed as an integrated circuit module. As a result, it can be used in addition to existing components or controllers and used in existing systems.

It is expedient if the logic circuit according to the invention is used for Ethernet-based data transmission. Ethernet-based data transmission is now widespread and forms a standard embodiment of the Data transfer. The logic circuit according to the invention can advantageously be integrated into existing systems.

In a particularly preferred embodiment, the logic circuit according to the invention is used in a fieldbus network, in particular in a network according to a SERCOS standard. For example, a SERCOS III standard network may be used that allows the use of Ethernet components in a SERCOS connection.

The logic circuit according to the invention is expediently used for real-time data transmission or real-time communication. Particularly in the case of real-time communication, the accelerated CRC test value calculation has an advantageous effect.

Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings _. ,

It is understood that the features mentioned above and those yet to be explained not only in the particular combination given, but also in other combinations or alone, without departing from the scope of the present invention.

figure description

In the following, the invention and in particular its advantages with reference to an embodiment shown in the figures will be explained in more detail. It shows

FIG. 1 a shows a flowchart of a data transmission in which

Data fields are provided with CRC test values, in the prior art;

FIG. 1 b shows a flowchart corresponding to FIG. 1 a, wherein an embodiment of a logic circuit according to the invention is used;

Figure 2 is a schematic representation of a

Embodiment of a logic circuit according to the invention;

Figure 3 shows the structure of a master data telegram according to the SERCOS III standard, which is generated using an embodiment of the logic circuit according to the invention; and

Figure 4 is a schematic representation of the switching elements of an embodiment of a logic circuit according to the invention.

In FIG. 1 a, a flow diagram of a data transmission in the prior art is shown, wherein selected data fields are provided with CRC check values.

In method step 100, the data to be transmitted is prepared. Among other things, this includes the division of the data into data blocks, whereby individual data blocks are transmitted in data telegrams. - S -

In step 101, the associated CRC check value is calculated for each data block. This is done in the prior art by software routines that take a relatively long period of time due to the described requirements.

In method step 102, the data blocks are then combined with the calculated CRC test values. The summarized data are finally transferred in method step 103 to the communication controller. The communication controller performs the subsequent data transfer largely independently.

FIG. 1 b shows a flow chart corresponding to the flowchart shown in FIG. 1 a, wherein a preferred embodiment of a logic circuit according to the invention is used.

In step 110, in turn, the data to be transmitted is divided into individual data blocks. In method step 111, the logic circuit dedicated for calculating CRC test values is initialized and configured. In this case, the logic circuit u.a. the CRC polynomial to be used, the length of the CRC polynomial to be used, and the position of the data blocks for which CRC check values are to be calculated.

In method step 112, only the data blocks of the logic circuit or of a communication controller having an integrated logic circuit are to be transferred. Before the subsequent data transfer leads the logic circuit or in the communication controller integrated logic circuit independently performs the CRC test value calculation. In this way, the process can be accelerated.

By using a logic circuit according to the invention, in particular communication controllers can be provided which are suitable for different transmission protocols, in particular different fieldbus systems. For example, a 16-bit checksum is used on a SERCOS I / II or CAN bus, whereas a SERCOS III, safety SERCOS or EtherCAT bus uses a 32-bit checksum.

In FIG. 2, an embodiment of a logic circuit according to the invention is shown roughly schematically and designated overall by 200. The logic circuit 200 has an input 201 and an output 202. The input 201 and the output 202 may be configured for serial or parallel data transmission, as is well known in the art. It is understood that the input 201 and the output 202 are not components physically formed in this form, such as e.g. Plug, etc., but that also inputs and outputs of a logical interface description are included in this description.

Input data 203 is provided to the input 201. The input data 203 includes various data areas or data blocks 203a to 203e. In this schematic representation, the subdivision of the input data 203 into individual blocks does not necessarily correspond to a temporal, spatial or other subdivisions, but above all represents a schematic subdivision. The input data blocks 203a to 203e contain, on the one hand, the configuration data necessary for initialization and configuration of the logic circuit 200 and, on the other hand, the data for which a CRC test value calculation is to take place. For example, the input data block 203a includes the CRC polynomial to be used, the input data block 203b the length of the CRC polynomial to be used, the input data block 203c the amount or number of data for which the CRC check value calculation is to be made, and the input data blocks 203d and 203e the Data for which the CRC test value calculation is to take place.

Preferably, a starting value for a shift register within the logic circuit 200 can also be predeterminable via the input 201. Usually, different start values, for example, "111111 .... 1" ("1" in each register bit) or "0" ("0" in each register bit) depending on the selected CRC polynomial have proven to be advantageous. The starting value can be specified within the input data 203 as a further data area or data block (not shown).

The input data blocks 203a to 203e are transferred as input data 203 to the input 201. The

Logic circuit 200 then calculates the associated CRC check values according to its configuration for the data transferred.

The logic circuit 200 finally provides the output data 204 at its output 202. In this embodiment, the output data 204 includes output data blocks 204a to 204d. The number of Output data blocks are preferably determined by the number of input data blocks. In this example, a CRC check value is calculated for each of the two input data blocks 203d and 203e. ^• the input data blocks 203d and 203e are outputted as output data blocks 204a and 204c, with the associated CRC check values are inserted in each case as more output data blocks 204b and 204d.

In this way, a fast CRC test value calculation for variable data blocks can be achieved, as occur in particular in a data transmission according to the SERCOS III standard, as will be explained in more detail with reference to FIG.

FIG. 3 schematically shows the structure of an exemplary master data telegram (MDT) according to the SERCOS III standard.

SERCOS is a standardized servo drive interface with fieldbus couplers. The range of applications includes not only machining technologies, but also other automation solutions, e.g. in the field of assembly robots, as well as of printing and packaging machines.

The access to the transmission medium is realized by a time slot method. Each participant is assigned a time at which he exclusively has access to the transmission medium.

The communication cycle is determined by the

Master synchronization telegram (MST) of the master, eg a control system, started. The slaves, eg Drive systems or I / O stations send successively one ^' drive telegram (AT) with their current actual values. Afterwards, the master sends the master data telegram (MDT) with the setpoints. This process is repeated every communication cycle. All data telegrams are received by all slaves. An MDT therefore contains data for all the slaves to be controlled.

An MDT field (MDT field) 300 has three areas 301, 302, 303, the area 301 being called "MDT hotplug field", the area 302 being "MDT Service Channel field" and the area 303 being "MDT realtime data field " referred to as. Area 303 (MDT realtime data field) contains the real-time data, which is transmitted to all the slaves to be controlled.

In the example shown, the area 303 has three inner areas 304, 305, and 306, each containing real-time data for different connected slaves. In this example, data is included for three connected slaves, so areas 304, 305 and 306 are referred to as "realtime data 1", "realtime data 2" and "realtime data 3". The number of slaves for which data is transferred may change each transmission cycle.

Depending on the intended use of the addressed slaves, the regions 304, 305, 306 again have a different internal structure.

In the example shown, area 304 (realtime data 1) has two areas 304a and 304b, which are called "Default real-time data 1 "(SRD 1) and" safe data container 1 "(SDC 1).

Area 305 (realtime data 1) has area 305a (SRD 1), area 306 (realtime data 3) has area 306a (SRD 3) and area 306b (SDC 3).

In the areas 304a (SRD 1), 305a (SRD 2) and 306a

(SRD 3) contain the data for the respective slaves, which do not have to have increased error safety. In the areas 304b (SDC 1) and 306b (SDC 3), however, the data are included, which have an increased error safety. CRC check values are added to provide increased error safety.

In the prior art, the CRC check values for areas 304b and 306b are calculated via software routines. The contents of regions 304a, 305a, 306a and regions 304b and 306b will normally vary at each transmission cycle. Also, the subdivisions of area 303 (MDT realtime data field) into areas 304 (realtime data 1), 305 (realtime data 2), and 306 (realtime data 3) are exemplary only and also vary from application to application. Also, the number of subdivisions mentioned is not constant.

For these reasons, the CRC check values must be recalculated every transmission cycle. This takes a long time in each transmission cycle.

By using a preferred embodiment of the method according to the invention for calculating the CRC test values that are in the varying ranges "SDC" can be added, a significant time savings can be achieved.

A preferred embodiment of a logic circuit according to the invention is shown schematically in FIG. 4 and indicated as a whole by 400. The logic circuit 400 has a first input 401 for receiving a generator polynomial. Furthermore, the logic circuit 400 has a second input 402 for receiving a message. Furthermore, the logic circuit 400 has a third one

Input 403 for receiving the length of the CRC polynomial to be used. Finally, the logic circuit 400 has an output 404 for outputting the calculated CRC check value.

The message is supplied to a shift register within the logic circuit 400, which has a number of bits freely selectable in the design of the logic circuit. In the illustrated embodiment, the shift register has six bits 421 to 426. The arbitrary number of bits of the shift register determines the maximum size of the CRC polynomial usable with the logic circuit.

The logic circuit 400 further has

Storage means for receiving the CRC polynomial. The storage means store the individual bits 411 to 416 of the generator polynomial and can be designed, for example, as flip-flops. The number of storage means preferably corresponds to the number of shift register locations.

For example, it is advisable to provide a number of 32 or 64 bits, in which case CRC checksums with a maximum of 32 or 64 bits can be calculated. Optionally, the logic circuit also has an input (not shown) for receiving a preset or initialization value for the shift register. Depending on the CRC polynomial used, various initialization values have proved to be advantageous, which advantageously can also be fed to the logic circuit from the outside.

For determining the CRC check value, each of the polynomials 411 to 416 is connected to an XOR gate ("= 1") through an AND gate "&". The individual XOR gates "= 1" are arranged between the bits of the shift register. The basic mode of operation of such a circuit is known to the person skilled in the art and will therefore not be explained further here. For example, an inversion may occur, etc.

According to the invention, 400 variable-length CRC polynomials may be used in the logic circuit 400. For this purpose, an input of the AND gates "&" is in each case connected to a multiplexer circuit 430, which selects a bit of the shift register by means of the length of the CRC polynomial supplied via the input 403 and defines it as the most significant bit.

At the end of the calculation of the CRC check value, this is stored in bits 421, 422,... Including the selected most significant bit. The test value can be taken there, for example, also via the multiplexer circuit 430 or in another way (for example, in parallel), for which purpose the output 404 is provided. Although in the illustrated embodiment, the length of the CRC polynomial is supplied via input 403, this input may also be internally connected to a computing circuit which determines the length of the polynomial from bits 411 through 416.

It is understood that in the illustrated figures, only exemplary embodiments of the invention is shown. In addition, any other embodiment is conceivable without departing from the scope of this invention. For example, the functionality of the AND gates in Figure 4 may also be implemented by multiplexers. Conversely, the functionality of the multiplexer 430 can also be achieved by AND gates.

reference numeral

101 - 103 process step

110 - 112 Method step 200 Logic circuit

201 entrance

202 output

203 input data

203a-203e input data block 204 output data

204a-204d output data block

300 MDT field

301 MDT hotplug field

302 MDT service Channel field 303 MDT realtime data field

304 realtime data 1

304a standard realtime data 1

304b safe data container 1

305 realtime data 2 305a Standard realtime data 2

306 realtime data 3

306a standard realtime data 3

306b safe data container 3

400 logic circuit 401, 402, 403 input

404 exit

411 - 416 generator polynom bits

421 - 426 shift register bits

430 Multiplexers & AND gates

= 1 XOR gate

Claims

claims

A logic circuit for calculating a CRC check value of a message, the CRC check value having a predeterminable length, comprising an input (201; 402) for receiving the message (203d, 203e), an input (201; 401) for recording a freely definable CRC polynomial (203a), calculating means (421-426, "&", "= 1") for calculating a CRC check value (204b, 204d) of the message (203d, 203e) from the CRC polynomial (203a ) , and

Switching means (430) which polled the calculation means (421-426, "Sc", "= 1") in dependence on a length (203b) of the CRC polynomial (203a) such that the length of the CRC check value is of length ( 203b) of the CRC polynomial (203a).

A logic circuit according to claim 1, wherein said calculating means (421-426, "&", "= 1") comprises at least one shift register (421-426) whose most significant bit (422-426) is defined by the switching means (430) ,

The logic circuit of claim 2, including an input (201) for receiving an initialization value for the shift register (421-426).

4. Logic circuit according to claim 2 or 3, wherein the switching means comprise at least one multiplexer (430), to the at least two bits of the at least one shift register (421-426).

A logic circuit as claimed in any preceding claim, wherein the calculating means (421-426, "&", "= 1") comprises at least one XOR gate ("= 1").

A logic circuit as claimed in any one of the preceding claims, wherein an input (201; 403) is provided for receiving the length (203b) of the CRC polynomial (203a).

7. Logic circuit according to one of the preceding claims, wherein at least one predetermined CRC polynomial is integrated.

8. Logic circuit according to one of the preceding claims, which is integrated in a communication controller.

9. Logic circuit according to one of the preceding claims, which is designed as an integrated circuit module.

10. A device for calculating CRC test values comprising at least two logic circuits according to one of the preceding claims.

11. Use of a logic circuit according to one of claims 1 to 9 or an apparatus according to claim 10 in a field bus communication system.

12. Use of a logic circuit according to one of

Claims 1 to 9 or a device according to claim 10 in a network according to a SERCOS standard.

13. Use of a logic circuit according to one of claims 1 to 9 or an apparatus according to claim 10 for real-time data transmission.