WO2010080068A1 - Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies - Google Patents

Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies Download PDF

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Publication number
WO2010080068A1
WO2010080068A1 PCT/SG2009/000021 SG2009000021W WO2010080068A1 WO 2010080068 A1 WO2010080068 A1 WO 2010080068A1 SG 2009000021 W SG2009000021 W SG 2009000021W WO 2010080068 A1 WO2010080068 A1 WO 2010080068A1
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WO
WIPO (PCT)
Prior art keywords
chip
wafer level
package according
stacked package
encapsulant
Prior art date
Application number
PCT/SG2009/000021
Other languages
French (fr)
Inventor
Ravi Kanth Kolan
Original Assignee
Ravi Kanth Kolan
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Publication date
Application filed by Ravi Kanth Kolan filed Critical Ravi Kanth Kolan
Publication of WO2010080068A1 publication Critical patent/WO2010080068A1/en

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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention generally relates to electronic packaging technology and more particularly relates to methods and apparatus for electronically interconnecting and assembling a three dimensional multi-chip stack package using through silicon via technology.
  • Three dimensional (3D) chip stacking technologies with through silicon interconnection is a method to realize, high density and high performance system in package (SIP).
  • SIP system in package
  • FIG. 1 illustrates a three dimensional chip stack package 10, that includes stacking of same chips 20 on to an interposer chip 15. The whole stack is under-filled with epoxy 22 and encapsulated with mold compound 23. On the bottom side of the interposer chip 15, solder balls 25 are attached to complete the assembly.
  • FIG. 2 illustrates a similar multi chip stack package 50 having an additional controller chip 40 attached at the bottom of the interposer chip 15. The controller chip 40 bump connections to the interposer chip 15 pads are protected using an under-fill epoxy 42.
  • FIG 4 Illustrated in FIG 4 is the wafer support system using a dummy silicon wafer or a glass wafer as support, referred as 45. For simplicity sake only one chip 20 is shown attached to wafer support wafer 45, using an adhesive 46. Chip 20 can be treated as part of full wafer.
  • FIG 4 also shows a thinned bottom interposer wafer 15 attached to a support wafer 45 using an adhesive 46.
  • the wafer bonding and de-bonding equipment are expensive and they use thermo plastic resin or UV curable liquid resin or some kind thermo-set epoxies, all of them here referred as 46.
  • Each of the above mentioned epoxies 46 have their own limitations, like, the limitation of the adhesive 46 to withstand certain temperature and they also have requirements of a cleaning system after de-bonding from the wafer support. At high temperature process exposures, the adhesive 46 tends to deteriorate and result in wafer cracks or chip-off issues due to de-lamination of epoxy 46 from the support wafer 45 or active wafer 20. All the above mentioned issues resulting in yield losses will add a huge cost to the package.
  • under-fill 32 is dispensed on the landing pad prior to chip attach. As illustrated in FIG 3B, during the chip attach process at high temperature, under-fill 32 might squeeze out at the sides of the stack due to high compressive forces needed during chip attach process. The other major concern is the filler 35 entrapment in between the bump 28 and the bond pad 29, leading to very high electrical failures and ultimately to low yields. [16] All the above challenges listed above add up hugely to the packaging cost. People involved in the art acknowledge that above mentioned challenges are the bottle necks for the migration to 3D packaging using through silicon vias.
  • the present invention has made to solve the foregoing problems.
  • the objective of the present invention is to make chip stacking process simpler, environmentally friendly and cost effective.
  • the invention also addresses to solve warpage issue, arising due to the co-efficient of thermal mis-match between silicon and the encapsulant.
  • a wafer level stacked package having a main silicon chip with first and second face, the main silicon chip having dielectric and wiring patterns at both first and second faces, and having plurality of bumps on first face.
  • a silicon chip having plurality of through silicon metal filled vias, electrically connecting with metal trace patterns of first and second faces.
  • the main silicon chip having plurality of bumps at the first face, attached with a bottom chip at first face and having liquid adhesive sealing the bottom chip, having an bottom encapsulant member covering the first face, covering the bottom chip and the bumps, with bump connections extended outside the encapsulant surface and with bottom encapsulant extending sideways and being exactly equal to the size of the main silicon chip.
  • the proposed wafer level stacked package further comprises a first top chip with plurality of micro bumps attached to the second face of the main silicon chip and sealed with a liquid adhesive, a first top encapsulant, covering the second face of the main silicon chip, and sides of the first top chip, and extending sideways, exactly to the size of the main silicon chip, a first top dielectric and metal trace layering pattern covering on top of the first top encapsulant, and the first top chip.
  • the first top dielectric and metal trace patterns extending exactly to the size of main silicon chip, the first top metal trace patterns having electrically connected to the metal filled through silicon vias of first top chip.
  • One of the biggest advantage of this present invention is the ultra thinning of chips, approximately 50 microns and less, thus needing very thin through silicon vias, resulting in low cost of stacking the chips in a three dimensional pattern.
  • FIG 5 is an exemplary view, showing a section of a three dimensional stacked semiconductor devise according to a first embodiment; FIG 5, also shows stacking of similar chips.
  • FIG6 to FIG 18 shows an exemplary view, depicting a method of manufacturing the three dimensional stack package according to first embodiment.
  • FIG 26, is an exemplary view, showing a section of a three dimensional stacked semiconductor device according to second embodiment.
  • FIG26 also shows integration of heterogeneous technologies, chips of different sizes and different technologies being stacked.
  • FIG 27 to FIG 32 shows possible combination of different structures.
  • FIG 5 is an explanatory view showing a section of a three dimensional stacked semiconductor device according to a first embodiment.
  • a chip stack package 200 includes two or more semiconductor chips 105 and top semiconductor chip 106, stacked on top side of common silicon interposer chip 101, while chip 103 and bumps 140 are attached to the bottom side of silicon interposer chiplOl.
  • the silicon chip 101 could be just an interposer chip or it could be an active chip itself.
  • the silicon chip 101 having through silicon vias 130, enable electrical connections to the top chips 105, 106 and to the bottom chip 103 and solder bumps 140.
  • each of the metal 131 filled vias 130 is preferably surrounded by a layer of a seed metal 132 which in turn is covered with insulating layer 134.
  • Encapsulant 150 encapsulates bottom side of silicon chip 101, sides of chip 103 and part of the bumps 140. Coefficient of thermal expansion of encapsulant 150 ranges from 6 to 15 parts per million per degree centigrade, while that of silicon chip 101 ranges from 4 to 10 parts per million per degree centigrade. This mis-match of co-efficient of thermal expansion between chip 101 and encapsulant 150, is compensated by a series of encapsulant 152 layers encapsulating top side of chip 101 and sides of the top chips 105 and 106.
  • reference numeral 100 indicates a plan view of a silicon wafer, having a plurality of chip 101 locations.
  • the silicon wafer 100 could be an interposer wafer or it could be an active wafer.
  • the silicon wafer 100 has features like wafer notch 156, edge exclusion zone 102 and scribe lines 115. Wafer notch 156 is used for gross alignment purposes and scribe lines 115 are used to saw the wafer into individual chips.
  • Edge exclusion zone 102 • . ranges from 3 to 8mm in width where no chips 101 are populated.
  • FIG7 shows a cross sectional view of silicon wafer 100, having an active top surface 102 and a back surface 104. Both the top surface 102 and bottom surface 104 have identical alignment features and scribe lines. Wafer 100 is composed of plurality of chips 101, but for the purpose of simplicity and clear explanation, only two chip 101 locations are shown. [35] FIG 7, reference to numeral 100 indicates a silicon active wafer or silicon interposer wafer, which has plurality of through silicon vias 130, metal traces 136 redistributed to pads 138 and bumps 14O.Bumps 140 can be formed using combination of metals like tin, silver and copper.
  • Bumps 140 could be any commercially available solder balls that are place on the wafer 100 using wafer level solder ball drop process and reflowed to establish the interconnection between the balls 140 and the pad.
  • die-electric layers 120 and 122 are spin coated for every layer of metal tracesl36.
  • Dielectric layers are usually made of polyimide (PI) or similar dielectric ' materials like BCB (benzocyclobutene).
  • FIG 8 shows a flip chip 103 being attached on to the silicon wafer 100 at the top side 102 and under-filled using an under-fill epoxy 160.
  • the dispense process could be a needle dispense or a jetting process, which is well known to the people in the art.
  • FIG 9 Depicted in FIG 9, is a pre-molded stiffener ring 155 using some kind of thermo set epoxy and having features such as a wafer notch 156 used for alignment and having similar outer diameter as silicon wafer 100.
  • Feature 157 on the stiffener ring 155 is a very shallow recess molded in such a shape so as to prevent the mold flash contaminating the mold tooling during molding.
  • Stiffener ring 155 acts as vents, to vent out the air trapped in the mold cavity, during encapsulation. Stiffener ring 155 also helps to reduce any wafer warpage after encapsulation. Stiffener ring 155 could also be resized from other materials like silicon wafer etc, in such instances the air vent feature could be incorporated in the mold tooling 80, ' . referenced in FIG 11.
  • the method of laminating the stiffener ring 155 to the interposer wafer 100 is depicted in FTG 10.
  • Stiffener ring 155 is stencil printed with a thermo-set epoxy 168 and the epoxy 168 is partially cured before laminating the stiffener ring 155 to the top side 102 of the silicon wafer 100.
  • EV Group's 540C2W can be used to laminate the ring 155 to the wafer 100.
  • the thermo-set epoxy 168 could also be in a pre-cut tape form and in such cases it could be laminated to the stiffener ring 155.
  • thermo-set epoxy 168 undergoes a partial curing prior to encapsulating (referring to FIG 12) the top side 102, of the silicon wafer 100.
  • FIG 11 shows the encapsulation concept.
  • the reference numeral 80 indicates a mold tooling.
  • the mold tooling comprises of a spring loaded floating bottom chase 81.
  • the bottom chase floating spring allows for compensating, for any variation in the thickness of the wafer stack.
  • the wafer stack at this point comprises of silicon wafer 100 and stiffener ring 155 laminated with epoxy layer 168 in between.
  • the bottom chase floating mechanism also avoids any wafer crack during mold clamping. Locating pins 82 helps to locate the wafer stack on to the bottom chase 81.
  • Mold tooling on the top consists of a fixed top cavity bar 83, having a spring loaded top cavity insert 84 to compensate for mold compound variation.
  • the mold tooling 80 on the top has a film system 85 for easy releasing of the encapsulated mold compound 150, referenced in the FIG 12.
  • the film 85 also acts as a cushion during mold clamping, thus preventing any crack in the wafer stack.
  • FIG 12 shows an encapsulation of top side 102, of the silicon wafer 100, using a compression molding technology.
  • the encapsulated mold compound 150 could be any thermo-set granular mold compound or a liquid mold compound or any commercially available thermo-set epoxy compounds.
  • the temperature of mold tooling 80, during molding is as at least as high as the glass transition temperature of the mold compound 150.
  • the final molded shape of the encapsulated mold compound 150 can be as simple as flat or it can take complex shape as needed.
  • mold compound 150 ranges from 6 to 15 parts per million per degree centigrade after the post mold curing process. During the post mold curing process both the mold compound 150 and epoxy 168 will be fully cured. [43] Due to difference in co-efficient of thermal expansion of mold compound 150 and silicon wafer 100, slight bowing could be seen on molded wafer. Molded encapsulated compound 150 undergoes a planarization process, to make it flat and planar with respect to surface 104, for easier subsequent handling.
  • FIG 13A and FIG 13B shows a stiffener wafer 119 being attached to the planar mold surface 150 using an epoxy 169 and cured. Stiffener wafer 119 can be back grinded and polished planar with respect to surface 104 of the silicon wafer 100.
  • stiffener wafer 119 helps to minimize or totally eliminate the warpage of the molded stack. Stiffener wafer also helps in, to transfer all the alignment features from surface 104 to surface 118, needed for subsequent stacking process. This completes the preparation at surface 102 of the silicon wafer 100.
  • FIG 14 illustrates the thinning of silicon wafer 100 from the surface 104. Thinning is followed with standard chemical mechanical polishing (CMP) to expose to the vias 130. CMP also helps to remove any subsurface damage in the silicon 100 that might have been induced by back grind process. It is quite normal to see copper vias 130 protruding up by 1 to 2 microns than the silicon surface.
  • CMP chemical mechanical polishing
  • the exposed through silicon vial 30 surface is cleaned and dry baked at 125 deg C, before proceeding to the redistribution layering (RDL) and pad patterning.
  • RDL redistribution layering
  • Disco Corp's DGP 8760/8761 can be used polish and dry etching to expose the- through silicon via's.
  • FIG 15, depicts the redistribution layering of metal traces 136 and pad 138 patterning.
  • a layer of polyimide 124 is spin coated to a thickness of 3 to 8 microns.
  • the dielectric layer 124 can also be BCB (benzocyclobutene).
  • PI 124 is soft baked with a temperature range between 110 deg C and 140degC.
  • the soft baked PI 120 coated wafer is transferred to an aligner.
  • the mask is used in the aligner to expose the copper pad 131 positions of through silicon via 130.
  • the copper pad 131 is exposed in such a way that around 5 to lOum all around the copper pad 131 is covered with the dielectric layer 124.
  • a cleaning process called de-scum is carried out to clean the exposed through silicon copper pad- 131.
  • a very thin layer of copper is sputtered on the developed layer 124.
  • the thin layer of copper acts as an electrically conductive medium for plating the metal trace 136.
  • a photo sensitive resist is coated and developed to expose the copper trace pattern.
  • a cleaning process called de-scum is carried out to clean the trace areas of any photo resist. Plating of the metal traces 136 is done.
  • the photo resist layer is removed and etching is carried out to remove the sputtered thin seed metal layer.
  • the metal traces 136 will not be affected with the etching.
  • Second dielectric layer 126 is spin coated and developed to expose the bump pad 138 locations. Pads 138 are developed with the plating of under bump metallurgy called UBM.
  • the UBM pad 138 may be slightly sink-in 3 to 5 microns or pad 138 can be flat.
  • FIG 16A refers to flip chip attaching of top chip 105.
  • the advantage of this embodiment is that top chips 105 are thick enough to be handled by standard flip chip attach process. Those known to the art will appreciate the benefit of handling thick chip for robust flip chip attach process.
  • the micro bump 139 is in the range of 20 to 30 microns in height ' ..
  • the bump 139 structure can be composed of 15 to 20 microns copper post with solder cap of
  • Solder material could be pure tin(Sn) or combination of tin(Sn)/silver(Ag) or combination of tin, silver and copper or any commercially available solder.
  • Flip chip attach process involves two steps, first is the placement of chips 105 using a tacky flux 167 and second, a gang pressing of the chips 105 and re-flow.
  • the chips are dipped in a tacky flux 167 reservoir.
  • the reservoir cavity depth is controlled, to control the amount of flux 167 that need to attach to the bumps 139.
  • Usual design rule is flux reservoir depth to be half the bump 139 height.
  • Tacky flux 167 holds the plurality of chips 105 in place, on the wafer stack.
  • the placement of chips can be carried out by any commercial flip chip bonder whose X/Y placement accuracy is +/- 3microns. Some of the production ready flip chip bonders with 3 microns placement accuracy are from equipment companies like Panasonic's FCB3 NM-SB50A and Toray Engineering Co Ltd's FC3000.
  • the wafer can be transferred to any commercially available gang chip bonder, like the one from EVGroup, 540C2W.
  • a gang chip bonder's vacuum table holds the wafer flat.
  • the top flat bonder head 87 has the capability to keep intact the chip 105 locations.
  • the bonder head 87 holds the chips 105 intact, a set compressive force is applied on all chips 105.
  • the heaters 88, in the gang chip bonder ramps up the temperature to solder re-flow temperature of bumps 139. Once reflow is completed the temperature ramps down to room temperature. All this process is carried out in a nitrogen environment in the bonder chamber.
  • the gang bonder opens and wafer can be transferred to a flux cleaning system.
  • the bumps 139 are gold stud bumps a low temperature ultrasonic bonding can be carried out and in such situations the pad 138 may also be sputtered with a thin layer of gold (Au) and this chip attach process can be flux less process.
  • Au gold
  • FIG 17, shows a under-fill process, to fill the gap between the top chips 105 and thinned silicon wafer 100.
  • a low stress under-fill epoxy 161 with high glass transition temperature and low co-efficient of thermal expansion is best suited.
  • the under-fill secures the bump 139 connections and as well as the chip 105 itself.
  • the dispense process could be a needle dispense or a jetting process, which is well known to the people in the art.
  • FIG 18, shows that the whole wafer is encapsulated with mold compound 152 after laminating with the stiffener ring 155.
  • a planarization process is carried out to expose the thru silicon vias 130 of the chips 105.
  • Planarization involves back grinding followed by chemical mechanical polish (CMP) to expose the through silicon vias 130 of chips 105.
  • CMP chemical mechanical polish
  • the ' encapsulation process is earlier explained referring to FIG 11 and FIG 12.
  • Steps earlier explained in FTG 15, are repeated.
  • a dielectric layer 124 is spin coated and developed to expose the center of metal via 131, but with dielectric layer 124 still covering 5 to 10 microns of metal pad 131 edges.
  • the metal trace 136 redistribution layering and pad 138 patterning is carried out as shown in the FIG19. The metal redistribution layering and pad patterning is explained referring to FIG 15.
  • reference numeral 190 indicates a chip stack, realized by the stacking of identical chips 105 and the top chip 106. Between each chip 105, the process steps, Dielectric patterning, metal trace 136 redistribution and pad 138 patterning referring to FIG 15, chip attach referring to FIG 16, under-fill referring to FIG17, Stiffener ring attach, encapsulation and planarization and chemical mechanical polishing referring to FTG 18 will repeatedly ' . carried out until the whole chip stack is completed.
  • FIG 21 is an exemplary view showing a section of semiconductor device according to a second embodiment.
  • FIG 21, reference to numeral 220 indicates a heterogeneous integration of chips 105, 107,108 and 109. Chips 105, 107 and 108 are of different sizes, shapes and even their through silicon via positions are different. The advantage of this exemplary embodiment is that it facilitates the integration of these varied chips of different technology, into a three dimensional chip stack package.
  • FIG 21 reference to numeral 220 indicates completion of top chip stacking with the final planarization process step.
  • FIG 22, illustrates completion of stacking of chips 105, 107.
  • a dielectric layer 124 is spin coated and developed to expose the center of metal via 131, but with dielectric layer 124 still covering 5 to 10 microns of metal pad 131 edges.
  • Next metal trace 136 redistribution of pad 138 patterning is carried out.
  • FIG22 shows copper post 146 plating, using some photo resist patterning and removal of such resist after copper post 146 plating.
  • FIG 23, shows completion of chip 108 stacking, under-filling 163, encapsulation 152 and planarization to expose both the copper post 146 and through silicon via 130 of chip 108.
  • FIG 24A and FIG 24B depicts removal of stiffener wafer 119 and expose of part of the solder ball pads through a back grind process.
  • the co-efficient of thermal mis-match between mold compound 150 on top side 102 of the silicon wafer 100 will be compensated with layers mold compound 152 stack on the bottom side 104 of the silicon wafer 100. This enables to have very low warpage.
  • the removal of stiffener wafer 119 will no way affects the warpage of the stack.
  • the relationship between the mold compound thickness 150 and the number of chip stacks 105,106,107,108 and 109 , interlaced with mold compound 152 need to be maintained. Selection of mold compounds 150 and 152 need to be selected after careful evaluations. •
  • FIG 25A and FIG 25B illustrate wafer level solder ball 140 placement processes for both the first and second embodiments.
  • Wafer level solder ball drop needs two stencils, one for the flux printing and the second composite stencil for ball placement. After the ball placement the whole wafer stack undergoes a reflow process to establish the solder ball placement.
  • the ball 140 mounted wafer stacks are mounted on a dicing tape, with solder balls 140 facing up.
  • the saw machine can reference two solder balls 140 of adjacent chip stacks and guide the saw blade exactly along the saw streets 115.
  • the wafer stacks are sawed into individual chip stacks referred to numeral 200 in FIG5 and 240 in FIG 26.

Abstract

A Wafer level stacked package (200), comprising a main silicon chip (101 ) having first face and second face and having plurality of dielectric and metal trace patterns on first (122) and second faces (126). The silicon chip having plurality of through silicon metal filled vias linking (130), the metal trace patterns of first and second faces of the main silicon chip. The silicon chip having plurality of bumps (140) at the first face. The silicon chip having a bottom encapsulant member (150) covering the first face and the bumps, with bump connections extended outside the encapsulant surface and with bottom encapsulant extending sideways and exactly equal to the size of the main silicon chip.

Description

METHOD FOR MANUFACTURING A LOW COST THREE DIMENSIONAL STACK PACKAGE AND RESULTING STRUCTURES USING THROUGH SILICON VIAS AND ASSEMBLIES.
BACKGROUND OF THE INVENTION [01] Field of the Invention
[02] The present invention generally relates to electronic packaging technology and more particularly relates to methods and apparatus for electronically interconnecting and assembling a three dimensional multi-chip stack package using through silicon via technology.
[03] Description of the related art
[04] Three dimensional (3D) chip stacking technologies with through silicon interconnection is a method to realize, high density and high performance system in package (SIP). Short interconnect length of through silicon copper filled or metal filled vias, greatly enhances the electrical performance of the packages.
[05] A three dimensional chip stack packaging has been introduced as part of multi chip packaging. FIG. 1 illustrates a three dimensional chip stack package 10, that includes stacking of same chips 20 on to an interposer chip 15. The whole stack is under-filled with epoxy 22 and encapsulated with mold compound 23. On the bottom side of the interposer chip 15, solder balls 25 are attached to complete the assembly. FIG. 2 illustrates a similar multi chip stack package 50 having an additional controller chip 40 attached at the bottom of the interposer chip 15. The controller chip 40 bump connections to the interposer chip 15 pads are protected using an under-fill epoxy 42.
[06] The current challenges with the above mentioned packages 10 and 50 will be summarized below. [07] THIN WAFER HANDLING CHALLENGES
[08] In the prior arts, FIG 1 and FIG 2, the top chips 20 are thinned using a wafer support system. Illustrated in FIG 4 is the wafer support system using a dummy silicon wafer or a glass wafer as support, referred as 45. For simplicity sake only one chip 20 is shown attached to wafer support wafer 45, using an adhesive 46. Chip 20 can be treated as part of full wafer. FIG 4 also shows a thinned bottom interposer wafer 15 attached to a support wafer 45 using an adhesive 46. The wafer bonding and de-bonding equipment are expensive and they use thermo plastic resin or UV curable liquid resin or some kind thermo-set epoxies, all of them here referred as 46. Each of the above mentioned epoxies 46 have their own limitations, like, the limitation of the adhesive 46 to withstand certain temperature and they also have requirements of a cleaning system after de-bonding from the wafer support. At high temperature process exposures, the adhesive 46 tends to deteriorate and result in wafer cracks or chip-off issues due to de-lamination of epoxy 46 from the support wafer 45 or active wafer 20. All the above mentioned issues resulting in yield losses will add a huge cost to the package.
[09] It should be noted that before thinning the wafer, a process called wafer edge protection is introduced. Those involved in the art would know it very well and wafer edge protection process is well documented by wafer back grind supplier "Disco Corp". So this • added edge protection process will add up to the cost of the packages as well. [10] The co-efficient of thermal expansion of silicon support wafer 45 is around 3 part per million per degree centigrade, while that of active wafer 20 with copper filled through silicon vias is understood to be around 10 parts per million per degree centigrade. When the stack of support silicon wafer 45 and active wafer 20 is subjected to high temperature process above 200degree centigrade, due to the mis-match of co-efficient of thermal expansions, usually wafer cracks are encountered. This is one of the major yield losses resulting from support wafer issues.
[11] CHIP ATTACH CHALLENGES
[12] As illustrated in FIG 3A, stacking the chips is also a major challenge, as it is not easy to handle very thinned chips 30 during chip attach process, due to risk of chip crack. This is one of reason why chips are not grinded very thin. Very thin chips 30 are also not stiff enough, so chips 30 tend to warp, which would lead to open interconnections during chip attach process. Under-filling thin chips 30 with under-fill epoxy 22, also tend to bend the chips 30 at the chip edges, resulting in stress concentration and prone to chip crack at the edges. The above mentioned are just few reasons why chips 20 are maintained at reasonable thickness. So thicker chips 20 require deeper through silicon vias 33 and filling deep vias with copper or any other conductive medium adds a huge cost to the 3D stack package. [13] UNDER-FILL CHALLENGES
[14] As illustrated in FTG 1, FIG 2 and FIG 3 A, under-filling the whole stack using epoxy 22 is another major challenge. It is difficult for under-fill epoxy 22 to penetrate the small gaps between chips, particularly in between the top chips of the stack. This leads to voids 30. Voids 30 is a major package reliability concern. Voids 30 leads to low yields and ultimately to high package cost.
[15] Other under-fill methods illustrated in FIG 3B uses a pre-applied under-fill 32. Underfill 32 is dispensed on the landing pad prior to chip attach. As illustrated in FIG 3B, during the chip attach process at high temperature, under-fill 32 might squeeze out at the sides of the stack due to high compressive forces needed during chip attach process. The other major concern is the filler 35 entrapment in between the bump 28 and the bond pad 29, leading to very high electrical failures and ultimately to low yields. [16] All the above challenges listed above add up hugely to the packaging cost. People involved in the art acknowledge that above mentioned challenges are the bottle necks for the migration to 3D packaging using through silicon vias.
SUMMARY OF THE INVENTION
[17] The present invention has made to solve the foregoing problems. The objective of the present invention is to make chip stacking process simpler, environmentally friendly and cost effective. The invention also addresses to solve warpage issue, arising due to the co-efficient of thermal mis-match between silicon and the encapsulant.
[18] According to one aspect of the present invention, for attaining the above objective, a wafer level stacked package is introduced, having a main silicon chip with first and second face, the main silicon chip having dielectric and wiring patterns at both first and second faces, and having plurality of bumps on first face. A silicon chip having plurality of through silicon metal filled vias, electrically connecting with metal trace patterns of first and second faces. The main silicon chip having plurality of bumps at the first face, attached with a bottom chip at first face and having liquid adhesive sealing the bottom chip, having an bottom encapsulant member covering the first face, covering the bottom chip and the bumps, with bump connections extended outside the encapsulant surface and with bottom encapsulant extending sideways and being exactly equal to the size of the main silicon chip. To overcome the warpage due to co-efficient of thermal mis-match between the silicon and encapsulant, the proposed wafer level stacked package further comprises a first top chip with plurality of micro bumps attached to the second face of the main silicon chip and sealed with a liquid adhesive, a first top encapsulant, covering the second face of the main silicon chip, and sides of the first top chip, and extending sideways, exactly to the size of the main silicon chip, a first top dielectric and metal trace layering pattern covering on top of the first top encapsulant, and the first top chip. The first top dielectric and metal trace patterns extending exactly to the size of main silicon chip, the first top metal trace patterns having electrically connected to the metal filled through silicon vias of first top chip.
[19] The bottom and top encapsulant over the silicon chip will shrink to the same amount and thus balancing out the effect the co-efficient of thermal mis-match between silicon and encapsulant, thus resolving the warpage issue.
[20] According to the assembly process introduced in the present invention, there is no requirement of any external temporary wafer handling system. Thus no temporary adhesive usage, which is considered environmental friendly. Chip stacking is sequential and there are no challenges to chip stacking as the chips handled will be of reasonable thickness during chip attach, there are no challenges related to re-flow temperature of chips during chip attach as thermo-set encapsulant layer can easily with-stand normal reflow temperatures such as 260 degree centigrade. Finally there are no under-fill challenges as well, as each chip is underfilled, one after the other.
[21] One of the biggest advantage of this present invention is the ultra thinning of chips, approximately 50 microns and less, thus needing very thin through silicon vias, resulting in low cost of stacking the chips in a three dimensional pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
[22] Exemplary embodiments of the present invention will be readily understood with reference to the detailed descriptions provided, when read in conjunction with the accompanying drawings in which similar or identical reference numerals are used to designate similar or corresponding structural elements, and in which:
[23] FIG 5, is an exemplary view, showing a section of a three dimensional stacked semiconductor devise according to a first embodiment; FIG 5, also shows stacking of similar chips. [24] FIG6 to FIG 18 shows an exemplary view, depicting a method of manufacturing the three dimensional stack package according to first embodiment.
[25] FIG 26, is an exemplary view, showing a section of a three dimensional stacked semiconductor device according to second embodiment.
[26] FIG26, also shows integration of heterogeneous technologies, chips of different sizes and different technologies being stacked.
[27] FIG 27 to FIG 32, shows possible combination of different structures.
DETAILED DESCRIPTION OF THE INVENTION
[28] Embodiments of the present invention will be herein after described with reference to the accompanying drawings. This invention may however be embodied in many different forms and should not be construed as limited to the particular embodiments set forth herein.
Rather these exemplary embodiments are provided so that this disclosure will be through and complete and will fully convey the scope of the invention to those skilled in the art.
[29] In the description, well known structures and conventional processes have not been described or illustrated in detail to avoid obscuring the present invention. It will be appreciated that for simplicity and clarity of illustration, some elements illustrated in the figures have not necessarily been drawn to scale. For example the dimensions of some elements have been exaggerated or reduced relative to other elements for clarity.
Additionally, similar features and elements common between the drawing figures retain the same numeral designation.
[30] HRST PREFERRED EMBODIMENT.
[31] FIG 5, is an explanatory view showing a section of a three dimensional stacked semiconductor device according to a first embodiment.
[32] As illustrated in FIG 5, a chip stack package 200 according to a first embodiment of the present invention, includes two or more semiconductor chips 105 and top semiconductor chip 106, stacked on top side of common silicon interposer chip 101, while chip 103 and bumps 140 are attached to the bottom side of silicon interposer chiplOl. The silicon chip 101 could be just an interposer chip or it could be an active chip itself. The silicon chip 101, having through silicon vias 130, enable electrical connections to the top chips 105, 106 and to the bottom chip 103 and solder bumps 140. In order to improve electrical properties, each of the metal 131 filled vias 130 is preferably surrounded by a layer of a seed metal 132 which in turn is covered with insulating layer 134. Encapsulant 150 encapsulates bottom side of silicon chip 101, sides of chip 103 and part of the bumps 140. Coefficient of thermal expansion of encapsulant 150 ranges from 6 to 15 parts per million per degree centigrade, while that of silicon chip 101 ranges from 4 to 10 parts per million per degree centigrade. This mis-match of co-efficient of thermal expansion between chip 101 and encapsulant 150, is compensated by a series of encapsulant 152 layers encapsulating top side of chip 101 and sides of the top chips 105 and 106.
[33] FIG 6, reference numeral 100 indicates a plan view of a silicon wafer, having a plurality of chip 101 locations. The silicon wafer 100 could be an interposer wafer or it could be an active wafer. The silicon wafer 100 has features like wafer notch 156, edge exclusion zone 102 and scribe lines 115. Wafer notch 156 is used for gross alignment purposes and scribe lines 115 are used to saw the wafer into individual chips. Edge exclusion zone 102 •. ranges from 3 to 8mm in width where no chips 101 are populated.
[34] FIG7, shows a cross sectional view of silicon wafer 100, having an active top surface 102 and a back surface 104. Both the top surface 102 and bottom surface 104 have identical alignment features and scribe lines. Wafer 100 is composed of plurality of chips 101, but for the purpose of simplicity and clear explanation, only two chip 101 locations are shown. [35] FIG 7, reference to numeral 100 indicates a silicon active wafer or silicon interposer wafer, which has plurality of through silicon vias 130, metal traces 136 redistributed to pads 138 and bumps 14O.Bumps 140 can be formed using combination of metals like tin, silver and copper. Bumps 140 could be any commercially available solder balls that are place on the wafer 100 using wafer level solder ball drop process and reflowed to establish the interconnection between the balls 140 and the pad. To maintain electrical integrity and to avoid shorting of any traces, die-electric layers 120 and 122 are spin coated for every layer of metal tracesl36. Dielectric layers are usually made of polyimide (PI) or similar dielectric ' materials like BCB (benzocyclobutene).
[36] FIG 8, shows a flip chip 103 being attached on to the silicon wafer 100 at the top side 102 and under-filled using an under-fill epoxy 160. The dispense process could be a needle dispense or a jetting process, which is well known to the people in the art. [37] Depicted in FIG 9, is a pre-molded stiffener ring 155 using some kind of thermo set epoxy and having features such as a wafer notch 156 used for alignment and having similar outer diameter as silicon wafer 100. Feature 157 on the stiffener ring 155, is a very shallow recess molded in such a shape so as to prevent the mold flash contaminating the mold tooling during molding. These features 157 act as vents, to vent out the air trapped in the mold cavity, during encapsulation. Stiffener ring 155 also helps to reduce any wafer warpage after encapsulation. Stiffener ring 155 could also be resized from other materials like silicon wafer etc, in such instances the air vent feature could be incorporated in the mold tooling 80, ' . referenced in FIG 11.
[38] The method of laminating the stiffener ring 155 to the interposer wafer 100 is depicted in FTG 10. Stiffener ring 155 is stencil printed with a thermo-set epoxy 168 and the epoxy 168 is partially cured before laminating the stiffener ring 155 to the top side 102 of the silicon wafer 100. EV Group's 540C2W can be used to laminate the ring 155 to the wafer 100. [39] The thermo-set epoxy 168 could also be in a pre-cut tape form and in such cases it could be laminated to the stiffener ring 155. The thermo-set epoxy 168 undergoes a partial curing prior to encapsulating (referring to FIG 12) the top side 102, of the silicon wafer 100. [40] FIG 11, shows the encapsulation concept. The reference numeral 80 indicates a mold tooling. The mold tooling comprises of a spring loaded floating bottom chase 81. The bottom chase floating spring allows for compensating, for any variation in the thickness of the wafer stack. The wafer stack at this point comprises of silicon wafer 100 and stiffener ring 155 laminated with epoxy layer 168 in between. The bottom chase floating mechanism also avoids any wafer crack during mold clamping. Locating pins 82 helps to locate the wafer stack on to the bottom chase 81. Mold tooling on the top consists of a fixed top cavity bar 83, having a spring loaded top cavity insert 84 to compensate for mold compound variation. The mold tooling 80 on the top has a film system 85 for easy releasing of the encapsulated mold compound 150, referenced in the FIG 12. The film 85 also acts as a cushion during mold clamping, thus preventing any crack in the wafer stack.
[41] FIG 12, shows an encapsulation of top side 102, of the silicon wafer 100, using a compression molding technology. The encapsulated mold compound 150 could be any thermo-set granular mold compound or a liquid mold compound or any commercially available thermo-set epoxy compounds. The temperature of mold tooling 80, during molding is as at least as high as the glass transition temperature of the mold compound 150. The final molded shape of the encapsulated mold compound 150 can be as simple as flat or it can take complex shape as needed.
[42] The co-efficient of thermal expansion of mold compound 150 ranges from 6 to 15 parts per million per degree centigrade after the post mold curing process. During the post mold curing process both the mold compound 150 and epoxy 168 will be fully cured. [43] Due to difference in co-efficient of thermal expansion of mold compound 150 and silicon wafer 100, slight bowing could be seen on molded wafer. Molded encapsulated compound 150 undergoes a planarization process, to make it flat and planar with respect to surface 104, for easier subsequent handling.
[44] FIG 13A and FIG 13B, shows a stiffener wafer 119 being attached to the planar mold surface 150 using an epoxy 169 and cured. Stiffener wafer 119 can be back grinded and polished planar with respect to surface 104 of the silicon wafer 100.
[45] Addition of stiffener wafer 119, helps to minimize or totally eliminate the warpage of the molded stack. Stiffener wafer also helps in, to transfer all the alignment features from surface 104 to surface 118, needed for subsequent stacking process. This completes the preparation at surface 102 of the silicon wafer 100.
[46] FIG 14, illustrates the thinning of silicon wafer 100 from the surface 104. Thinning is followed with standard chemical mechanical polishing (CMP) to expose to the vias 130. CMP also helps to remove any subsurface damage in the silicon 100 that might have been induced by back grind process. It is quite normal to see copper vias 130 protruding up by 1 to 2 microns than the silicon surface. The exposed through silicon vial 30 surface is cleaned and dry baked at 125 deg C, before proceeding to the redistribution layering (RDL) and pad patterning. Disco Corp's DGP 8760/8761 can be used polish and dry etching to expose the- through silicon via's.
[47] FIG 15, depicts the redistribution layering of metal traces 136 and pad 138 patterning. To electrically isolate the metal traces 136 from the silicon surface, first a layer of polyimide 124 is spin coated to a thickness of 3 to 8 microns. The dielectric layer 124 can also be BCB (benzocyclobutene). PI 124 is soft baked with a temperature range between 110 deg C and 140degC. The soft baked PI 120 coated wafer is transferred to an aligner. The mask is used in the aligner to expose the copper pad 131 positions of through silicon via 130. The copper pad 131 is exposed in such a way that around 5 to lOum all around the copper pad 131 is covered with the dielectric layer 124. A cleaning process called de-scum, is carried out to clean the exposed through silicon copper pad- 131.
[48] A very thin layer of copper is sputtered on the developed layer 124. The thin layer of copper, acts as an electrically conductive medium for plating the metal trace 136. A photo sensitive resist is coated and developed to expose the copper trace pattern. A cleaning process called de-scum is carried out to clean the trace areas of any photo resist. Plating of the metal traces 136 is done.
[49] The photo resist layer is removed and etching is carried out to remove the sputtered thin seed metal layer. The metal traces 136 will not be affected with the etching.
[50] Second dielectric layer 126 is spin coated and developed to expose the bump pad 138 locations. Pads 138 are developed with the plating of under bump metallurgy called UBM.
[51] The UBM pad 138 may be slightly sink-in 3 to 5 microns or pad 138 can be flat.
[52] TOP CHIP STACKING OF FIRST PREFERRED EMBODIMENT
[53] FIG 16A, refers to flip chip attaching of top chip 105. The advantage of this embodiment is that top chips 105 are thick enough to be handled by standard flip chip attach process. Those known to the art will appreciate the benefit of handling thick chip for robust flip chip attach process. The micro bump 139 is in the range of 20 to 30 microns in height'..
The bump 139 structure can be composed of 15 to 20 microns copper post with solder cap of
5 to lOum. Solder material could be pure tin(Sn) or combination of tin(Sn)/silver(Ag) or combination of tin, silver and copper or any commercially available solder.
[54] Flip chip attach process involves two steps, first is the placement of chips 105 using a tacky flux 167 and second, a gang pressing of the chips 105 and re-flow.
[55] The chips are dipped in a tacky flux 167 reservoir. The reservoir cavity depth is controlled, to control the amount of flux 167 that need to attach to the bumps 139. Usual design rule is flux reservoir depth to be half the bump 139 height. Then the chips are placed on the bond pad 138 locations. Tacky flux 167 holds the plurality of chips 105 in place, on the wafer stack. The placement of chips can be carried out by any commercial flip chip bonder whose X/Y placement accuracy is +/- 3microns. Some of the production ready flip chip bonders with 3 microns placement accuracy are from equipment companies like Panasonic's FCB3 NM-SB50A and Toray Engineering Co Ltd's FC3000. [56] The wafer can be transferred to any commercially available gang chip bonder, like the one from EVGroup, 540C2W. Referring to FIG 16B, a gang chip bonder's vacuum table holds the wafer flat. The top flat bonder head 87 has the capability to keep intact the chip 105 locations. The bonder head 87 holds the chips 105 intact, a set compressive force is applied on all chips 105. The heaters 88, in the gang chip bonder ramps up the temperature to solder re-flow temperature of bumps 139. Once reflow is completed the temperature ramps down to room temperature. All this process is carried out in a nitrogen environment in the bonder chamber. The gang bonder opens and wafer can be transferred to a flux cleaning system. [57] The advantage of this two step flip chip attach process, helps to keep all the chips same plane, thus helps in the subsequent process to expose the through silicon vias 130 in single plane, referring to FIG 18.
[58] In case the bumps 139 are gold stud bumps a low temperature ultrasonic bonding can be carried out and in such situations the pad 138 may also be sputtered with a thin layer of gold (Au) and this chip attach process can be flux less process.
[59] However it should be noted that this embodiment is not just limited to the above specifications of the bumps or the pad sizes.
[60] FIG 17, shows a under-fill process, to fill the gap between the top chips 105 and thinned silicon wafer 100. A low stress under-fill epoxy 161 with high glass transition temperature and low co-efficient of thermal expansion is best suited. The under-fill secures the bump 139 connections and as well as the chip 105 itself. The dispense process could be a needle dispense or a jetting process, which is well known to the people in the art. [61] FIG 18, shows that the whole wafer is encapsulated with mold compound 152 after laminating with the stiffener ring 155. A planarization process is carried out to expose the thru silicon vias 130 of the chips 105. Planarization involves back grinding followed by chemical mechanical polish (CMP) to expose the through silicon vias 130 of chips 105. The ' encapsulation process is earlier explained referring to FIG 11 and FIG 12. [62] Steps earlier explained in FTG 15, are repeated. After the through silicon vias 130 expose, a dielectric layer 124 is spin coated and developed to expose the center of metal via 131, but with dielectric layer 124 still covering 5 to 10 microns of metal pad 131 edges. Next the metal trace 136 redistribution layering and pad 138 patterning is carried out as shown in the FIG19. The metal redistribution layering and pad patterning is explained referring to FIG 15.
[63] FIG 20 , reference numeral 190 indicates a chip stack, realized by the stacking of identical chips 105 and the top chip 106. Between each chip 105, the process steps, Dielectric patterning, metal trace 136 redistribution and pad 138 patterning referring to FIG 15, chip attach referring to FIG 16, under-fill referring to FIG17, Stiffener ring attach, encapsulation and planarization and chemical mechanical polishing referring to FTG 18 will repeatedly '. carried out until the whole chip stack is completed.
[64] It can be appreciated that at each level the chips 105 can be thinned to very thin profile, thus saving cost on through silicon via filling requirement, but at the same time eliminating the need for any thin chip handling and having robust chip attach and under-fill processes. [65] SECOND PREFERRED EMBODIMENT [66] FIG 21 is an exemplary view showing a section of semiconductor device according to a second embodiment.
[67] Incidentally, constituent elements or portions similar to those employed in the first embodiment are given the same reference numerals and their description will be omitted. [68] FIG 21, reference to numeral 220, indicates a heterogeneous integration of chips 105, 107,108 and 109. Chips 105, 107 and 108 are of different sizes, shapes and even their through silicon via positions are different. The advantage of this exemplary embodiment is that it facilitates the integration of these varied chips of different technology, into a three dimensional chip stack package.
[69] FIG 21, reference to numeral 220 indicates completion of top chip stacking with the final planarization process step.
[70] FIG 22, illustrates completion of stacking of chips 105, 107. A dielectric layer 124 is spin coated and developed to expose the center of metal via 131, but with dielectric layer 124 still covering 5 to 10 microns of metal pad 131 edges. Next metal trace 136 redistribution of pad 138 patterning is carried out. FIG22, shows copper post 146 plating, using some photo resist patterning and removal of such resist after copper post 146 plating. [71] FIG 23, shows completion of chip 108 stacking, under-filling 163, encapsulation 152 and planarization to expose both the copper post 146 and through silicon via 130 of chip 108. [72] PROCESS STEPS COMMON TO FIRST AND SECOND EMBODIMENTS [73] FIG 24A and FIG 24B, depicts removal of stiffener wafer 119 and expose of part of the solder ball pads through a back grind process. The co-efficient of thermal mis-match between mold compound 150 on top side 102 of the silicon wafer 100 will be compensated with layers mold compound 152 stack on the bottom side 104 of the silicon wafer 100. This enables to have very low warpage. Thus the removal of stiffener wafer 119, will no way affects the warpage of the stack. However the relationship between the mold compound thickness 150 and the number of chip stacks 105,106,107,108 and 109 , interlaced with mold compound 152 need to be maintained. Selection of mold compounds 150 and 152 need to be selected after careful evaluations. •
[74] FIG 25A and FIG 25B illustrate wafer level solder ball 140 placement processes for both the first and second embodiments. Wafer level solder ball drop needs two stencils, one for the flux printing and the second composite stencil for ball placement. After the ball placement the whole wafer stack undergoes a reflow process to establish the solder ball placement.
[75] FIG 26, referring to numeral 240, indicates a sawed chip stack of heterogeneous chips
105,107,108 and 109 on top of an interposer chip 101. First the ball 140 mounted wafer stacks are mounted on a dicing tape, with solder balls 140 facing up. The saw machine can reference two solder balls 140 of adjacent chip stacks and guide the saw blade exactly along the saw streets 115. Finally the wafer stacks are sawed into individual chip stacks referred to numeral 200 in FIG5 and 240 in FIG 26.
[76] Referring to FIG27, FTG28, FIG29, FIG30, FIG31 and FIG32: Finally the sawed stacks are flipped and attached on to the laminate substrate 180, such that the solder balls 140 of the chip stack sits exactly at the landing pads 182, as in a flip chip system. A reflow process will establish the interconnection between the chip stack and laminate substrate 180, before the under-filling 166, over molding with mold compound 154 is carried out. It will be also understood by those skilled in the art that, various configurations and combinations of the package structures illustrated in FIG27, FIG28, FIG29, FIG30, HG 31 and FIG 32 are possible.
While this invention has been particularly shown and described with reference to preferred embodiment thereof, it will be understood by those skilled in the art, that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

What is Claimed is :
1. A Wafer level stacked package , comprising: a main silicon chip having first face and second face; having dielectric and metal trace patterns on first and second faces; having plurality of through silicon metal filled vias linking, metal trace patterns of first and second faces of main silicon chip; having plurality of bumps at the first face; having a bottom encapsulant member covering the first face of the main silicon chip and the bumps; with bump connections extended outside the encapsulant surface; and with bottom encapsulant extending sideways and exactly equal to the size of the main silicon chip.
2. A Wafer level stacked package according to claim 1 , further comprising: a bottom chip attached on the first face of the main silicon chip and having a liquid epoxy sealing the bottom chip; having a bottom encapsulant member covering the first face of the main silicon chip, the bottom chip and the bumps, with bump connections extended outside the encapsulant surface; and with bottom encapsulant extending sideways and exactly equal to the size of the main silicon chip; having a bottom chip electrically connected to the metal traces, on the first face of main silicon chip.
3. A wafer level stacked package according to claim 2, further comprises.: a top chip with plurality of micro bumps attached to the second face of the main silicon chip and sealed with a liquid adhesive; the top chip electrically connected to the metal traces, on the second face of main silicon chip; a top encapsulant member, covering the second face of the main silicon chip, and the sides of the top chip; the top encapsulant member extending sideways and exactly equal to the size of the main silicon chip;
4. A wafer level stacked package according to claim 3, further comprises: a plurality of top dielectric and metal trace layering patterns covering over the top encapsulant member, and the top chip; the top dielectric and metal trace layers, extending sideways and exactly equal to the size of main silicon chip; the top metal trace patterns having electrically connected to the metal filled through silicon vias of top chip.
5. A wafer level stacked package according to claim 3, wherein, materials at the bottom and top of the main silicon chip are same.
6. A wafer level stacked package according to claim 3, wherein, the top chips are plural and are of same size and thickness.
7. A wafer level stacked package according to claim 3, wherein, the top chips are plural and are of different size and same thickness.
8. A wafer level stacked package according to claim 3, wherein, the top and bottom encapsulant members are having same co-efficient of thermal expansion.
9. A wafer level stacked package according to claim 3, wherein, the top and bottom encapsulant members are having different co-efficient of • thermal expansion.
10. A wafer level stacked package according to claim 4, wherein, the top encapsulant member's top surface and top surface of top chip are in a plane.
1 1. A wafer level stacked package according to claim 1 , wherein, there are plurality of dielectric and top metal trace layers on both sides of the main silicon chip, extending out ward and having exactly the same size of main silicon chip.
12. A wafer level stacked' package according to claim 4, further comprises of plurality of top stack-layers in the Z direction also called direction of top chip thickness; each stack-layer comprising of, top chips which are sealed with a liquid adhesive, an encapsulant member, plurality of dielectric" and metal trace layers; having all the encapsulant layers extending sideways and having exactly the same size of main silicon chip; and having all dielectric and metal trace layers extending sideways and having exactly same size of main silicon chip.
13. A wafer level stacked package according to claim 12, wherein, all the stacked chips are of same size.
14. A wafer level stacked package according to claim 12, wherein, all the stacked chips are of different size.
15. A wafer level stacked package according to claim 12, wherein, the whole chip assembly which is electrically connected in flip chip system, be called as main chip stack.
16. A wafer level stacked package according to claim 12, further comprises a lower substrate composed of a glass epoxy resin having wiring patterns.
17. A wafer level stacked package according to claim 16,
Wherein, the main chip stack is attached to the lower glass epoxy substrate and electrically connected to the wirings in a flip chip system.
18. A wafer level stacked package according to claim 17, further comprises of an encapsulant member covering the upper side of glass epoxy substrate and whole of the main chip stack.
19. A wafer level stacked package according to claim 17,
Wherein, an intermediate liquid epoxy member seals the gap between the glass epoxy substrate and the main chip stack.
20. A wafer level stacked package according to claim 19, wherein, an encapsulant member covers the upper side of glass epoxy substrate, whole of the main chip stack and sides of the intermediate cured epoxy member.
21. A wafer level stacked package according to claim 18, further comprises of plurality of solder balls at the bottom side of glass epoxy substrate , solder balls being electrically connected through the glass epoxy substrate wiring pattern to the main chip stack.
22. A wafer level stacked package according to claim 20, further comprises of plurality of solder balls at the bottom side of glass epoxy substrate , solder balls being electrically connected through the glass epoxy substrate wiring pattern to the main chip stack.
23. A wafer level stacked package according to claim 20,
Wherein, a stiffener member is attached to the top of the exposed chip stack to act as heat sink.
24. A wafer level stacked package according to claim 4, further comprises. of plurality of top stack-layers in the Z direction also called direction of top chip thickness; each stack-layer comprising of, top chips which are sealed with liquid epoxy, an encapsulant, a plurality of dielectric and metal trace layers; having all or some of the encapsulant layers extending sideways and having size, larger than the main silicon chip; and having all or some of the dielectric and metal trace layers extending sideways and having size, larger than the main silicon chip.
5. A wafer level stacked package according to claim 3, further comprises of plurality of top stack-layers in the Z direction also called direction of top chip thickness; each stack-layer comprising of, top chips which are sealed with liquid epoxy, an encapsulant, a dielectric and metal trace layers; having all or some of the the encapsulant layers extending sideways and having size, smaller than the main silicon chip; and having all or some of the passivation and metal trace layers extending sideways and having size, smaller than the main silicon chip.
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