WO2010090903A3 - Method for forming trench isolation using a gas cluster ion beam growth process - Google Patents

Method for forming trench isolation using a gas cluster ion beam growth process Download PDF

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Publication number
WO2010090903A3
WO2010090903A3 PCT/US2010/022061 US2010022061W WO2010090903A3 WO 2010090903 A3 WO2010090903 A3 WO 2010090903A3 US 2010022061 W US2010022061 W US 2010022061W WO 2010090903 A3 WO2010090903 A3 WO 2010090903A3
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WO
WIPO (PCT)
Prior art keywords
trench isolation
ion beam
cluster ion
gas cluster
growth process
Prior art date
Application number
PCT/US2010/022061
Other languages
French (fr)
Other versions
WO2010090903A2 (en
Inventor
John J. Hautala
Original Assignee
Tel Epion Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tel Epion Inc. filed Critical Tel Epion Inc.
Publication of WO2010090903A2 publication Critical patent/WO2010090903A2/en
Publication of WO2010090903A3 publication Critical patent/WO2010090903A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2

Abstract

A method of forming shallow trench isolation on a substrate (152, 252, 1102, 1202, 1302) using a gas cluster ion beam (GCIB) (128, 1101, 1201, 1301) is described. The method comprises generating a GCIB (128, 1101, 1201, 1301), and irradiating the substrate (152, 252, 1102, 1202, 1302) with the GCIB (128, 1101, 1201, 1301) to form a shallow trench isolation structure (1100, 1200, 1300) by growing a dielectric layer (1114, 1204, 1312) in at least one region on the substrate (152, 252, 1102, 1202, 1302).
PCT/US2010/022061 2009-02-09 2010-01-26 Method for forming trench isolation using a gas cluster ion beam growth process WO2010090903A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/367,697 US7968422B2 (en) 2009-02-09 2009-02-09 Method for forming trench isolation using a gas cluster ion beam growth process
US12/367,697 2009-02-09

Publications (2)

Publication Number Publication Date
WO2010090903A2 WO2010090903A2 (en) 2010-08-12
WO2010090903A3 true WO2010090903A3 (en) 2010-10-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/022061 WO2010090903A2 (en) 2009-02-09 2010-01-26 Method for forming trench isolation using a gas cluster ion beam growth process

Country Status (3)

Country Link
US (1) US7968422B2 (en)
TW (1) TWI476862B (en)
WO (1) WO2010090903A2 (en)

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US7905199B2 (en) * 2008-06-24 2011-03-15 Tel Epion Inc. Method and system for directional growth using a gas cluster ion beam
US9142462B2 (en) 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US20120326230A1 (en) * 2011-06-22 2012-12-27 International Business Machines Corporation Silicon on insulator complementary metal oxide semiconductor with an isolation formed at low temperature
JP2013016557A (en) * 2011-06-30 2013-01-24 Toshiba Corp Method of manufacturing semiconductor device
US8557710B2 (en) * 2011-09-01 2013-10-15 Tel Epion Inc. Gas cluster ion beam etching process for metal-containing materials
US8691700B2 (en) * 2011-09-01 2014-04-08 Tel Epion Inc. Gas cluster ion beam etch profile control using beam divergence
US8512586B2 (en) * 2011-09-01 2013-08-20 Tel Epion Inc. Gas cluster ion beam etching process for achieving target etch process metrics for multiple materials
US8513138B2 (en) * 2011-09-01 2013-08-20 Tel Epion Inc. Gas cluster ion beam etching process for Si-containing and Ge-containing materials
US8815734B2 (en) 2011-11-07 2014-08-26 International Business Machines Corporation Use of gas cluster ion beam to reduce metal void formation in interconnect structures
US8546209B1 (en) 2012-06-15 2013-10-01 International Business Machines Corporation Replacement metal gate processing with reduced interlevel dielectric layer etch rate
US8946792B2 (en) 2012-11-26 2015-02-03 International Business Machines Corporation Dummy fin formation by gas cluster ion beam
TWI581367B (en) * 2012-12-12 2017-05-01 聯華電子股份有限公司 Method for manufacturing semiconductor structure
US9123673B2 (en) * 2013-03-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer back side processing structure and apparatus
US9540725B2 (en) 2014-05-14 2017-01-10 Tel Epion Inc. Method and apparatus for beam deflection in a gas cluster ion beam system
JP6545053B2 (en) * 2015-03-30 2019-07-17 東京エレクトロン株式会社 Processing apparatus and processing method, and gas cluster generating apparatus and generating method
US10541172B2 (en) * 2016-08-24 2020-01-21 International Business Machines Corporation Semiconductor device with reduced contact resistance
US9905459B1 (en) * 2016-09-01 2018-02-27 International Business Machines Corporation Neutral atom beam nitridation for copper interconnect
KR20180068229A (en) 2016-12-13 2018-06-21 삼성전자주식회사 Semiconductor device and method for fabricating the same
CN109698274B (en) 2017-10-23 2021-05-25 联华电子股份有限公司 Method for manufacturing capacitor
US10741678B2 (en) * 2017-10-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11120997B2 (en) * 2018-08-31 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Surface treatment for etch tuning

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Also Published As

Publication number Publication date
US20100200946A1 (en) 2010-08-12
WO2010090903A2 (en) 2010-08-12
TW201034117A (en) 2010-09-16
TWI476862B (en) 2015-03-11
US7968422B2 (en) 2011-06-28

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