WO2010129154A3 - Address translation trace message generation for debug - Google Patents

Address translation trace message generation for debug Download PDF

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Publication number
WO2010129154A3
WO2010129154A3 PCT/US2010/031251 US2010031251W WO2010129154A3 WO 2010129154 A3 WO2010129154 A3 WO 2010129154A3 US 2010031251 W US2010031251 W US 2010031251W WO 2010129154 A3 WO2010129154 A3 WO 2010129154A3
Authority
WO
WIPO (PCT)
Prior art keywords
address translation
debug
message generation
trace
module
Prior art date
Application number
PCT/US2010/031251
Other languages
French (fr)
Other versions
WO2010129154A2 (en
Inventor
William C. Moyer
Richard G. Collins
Original Assignee
Freescale Semiconductor Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc. filed Critical Freescale Semiconductor Inc.
Priority to CN201080016420.9A priority Critical patent/CN102395949B/en
Priority to KR1020117026210A priority patent/KR101661499B1/en
Publication of WO2010129154A2 publication Critical patent/WO2010129154A2/en
Publication of WO2010129154A3 publication Critical patent/WO2010129154A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter

Abstract

A data processing system (10) and method generates debug messages by permitting an external debug tool (36) to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory (30) for information storage. Debug module (26) generates debug messages including address translation trace messages. A memory management unit (16) has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug module includes message generation module (64) that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation module generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug module.
PCT/US2010/031251 2009-05-05 2010-04-15 Address translation trace message generation for debug WO2010129154A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201080016420.9A CN102395949B (en) 2009-05-05 2010-04-15 Address translation trace message generation for debug
KR1020117026210A KR101661499B1 (en) 2009-05-05 2010-04-15 Address translation trace message generation for debug

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/435,723 2009-05-05
US12/435,723 US8438547B2 (en) 2009-05-05 2009-05-05 Address translation trace message generation for debug

Publications (2)

Publication Number Publication Date
WO2010129154A2 WO2010129154A2 (en) 2010-11-11
WO2010129154A3 true WO2010129154A3 (en) 2011-01-13

Family

ID=43050691

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/031251 WO2010129154A2 (en) 2009-05-05 2010-04-15 Address translation trace message generation for debug

Country Status (5)

Country Link
US (1) US8438547B2 (en)
KR (1) KR101661499B1 (en)
CN (1) CN102395949B (en)
TW (1) TWI502341B (en)
WO (1) WO2010129154A2 (en)

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US9946548B2 (en) * 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
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US9965375B2 (en) * 2016-06-28 2018-05-08 Intel Corporation Virtualizing precise event based sampling
US10331446B2 (en) * 2017-05-23 2019-06-25 International Business Machines Corporation Generating and verifying hardware instruction traces including memory data contents
WO2021122066A1 (en) * 2019-12-16 2021-06-24 Commsolid Gmbh A trace handler module system and a method using said system

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US20060036830A1 (en) * 2004-07-31 2006-02-16 Dinechin Christophe De Method for monitoring access to virtual memory pages

Also Published As

Publication number Publication date
CN102395949B (en) 2015-06-17
KR101661499B1 (en) 2016-09-30
KR20120018307A (en) 2012-03-02
WO2010129154A2 (en) 2010-11-11
US8438547B2 (en) 2013-05-07
TWI502341B (en) 2015-10-01
TW201135456A (en) 2011-10-16
US20100287417A1 (en) 2010-11-11
CN102395949A (en) 2012-03-28

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