WO2010136056A1 - Resistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method - Google Patents

Resistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method Download PDF

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Publication number
WO2010136056A1
WO2010136056A1 PCT/EP2009/006015 EP2009006015W WO2010136056A1 WO 2010136056 A1 WO2010136056 A1 WO 2010136056A1 EP 2009006015 W EP2009006015 W EP 2009006015W WO 2010136056 A1 WO2010136056 A1 WO 2010136056A1
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WO
WIPO (PCT)
Prior art keywords
resistive
storage cell
storage
passive
switching
Prior art date
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PCT/EP2009/006015
Other languages
French (fr)
Inventor
Eike Linn
Rainer Waser
Roland Rosezin
Carsten KÜGELER
Original Assignee
Rheinisch-Wetfälische Technische Hochschule Aachen
Forschungszentrum Jülich
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Application filed by Rheinisch-Wetfälische Technische Hochschule Aachen, Forschungszentrum Jülich filed Critical Rheinisch-Wetfälische Technische Hochschule Aachen
Priority to PCT/DE2010/000514 priority Critical patent/WO2010136007A2/en
Priority to EP10724255.4A priority patent/EP2436011B1/en
Priority to CN201080023633.4A priority patent/CN102449702B/en
Priority to EP17001319.7A priority patent/EP3273444A1/en
Priority to US13/261,044 priority patent/US8587988B2/en
Priority to KR1020117026795A priority patent/KR101725361B1/en
Priority to JP2012512199A priority patent/JP5551769B2/en
Publication of WO2010136056A1 publication Critical patent/WO2010136056A1/en
Priority to US13/943,141 priority patent/US20130301342A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0047—Read destroying or disturbing the data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • Resistive storage cell Resistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method
  • the invention relates to a resistive storage cell, a crossbar array circuit, a resistive random access memory device comprising said resistive storage cells and a method for reading out information from a bipolar resistive storage cell.
  • ECM electrochemical metallization
  • PMC programmable metallization cell
  • An ECM memory cell is in general made of two solid metal electrodes, wherein one electrode is a relatively inert first electrode and the other electrode is an electrochemically active second electrode.
  • the ECM memory cell further comprises a thin film of an electrolyte located between said two electrodes.
  • the ECM technology is based on the physical re-location of ions 5 within a solid electrolyte.
  • RRAM resistive random-access memory
  • CBRAM conductive-bridging RAM
  • Each of the memory units of a CBRAM device comprises a ECM memory cell and a control transistor.
  • the storage cell comprises a dielectric material, which is normally insulating. This dielectric material can be made to conduct through at least one internal conduction path formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms, including defects, metal migration or others. Once the conduction path is formed, it can be reset by cutting of the path which results in high resistance, or can be set, resulting in lower resistance. The adjustment of the corresponding resistivity can be carried out by applying an appropriately voltage or by changes of a related interface.
  • the RRAM device comprises passive storage cells, each consisting of a current path with a single resistive switching storage member. In this concept a noticeable parasitic current occurs.
  • each of the passive storage cells of the RRAM device comprises a current path with single resistive switching storage member and a passive but nonlinear member, e. g. a diode, both members connected in series within the current path to reduce the parasitic current, but even in this second concept a non- negligible parasitic current occurs.
  • WO 2006/037432 depicts a CBRAM memory circuit with a ECM memory cell (lTIR-cell) and an evaluation circuit for evaluation of a read out process by means of a reference memory cell, said memory cell comprising a resistance memory element, an active switching element and said reference memory cell comprising a reference resistance, wherein the memory cell is mounted between a ground connection and a capacitor and the reference memory cell is mounted between the ground connection and a reference capacitor.
  • the object of the invention is achieved by the features of claims 1 , 9 and 1 1.
  • the resistive storage cell is a passive resistive storage cell comprising a pair of two at least functionally identical resistive switching storage members, said two switching storage mem- bers are connected in series in a serial connection (current) path and are electrically anti- parallel orientated within the serial connection path.
  • the connection of the anti-parallel oriented two switching storage members within the serial connection path of the passive storage cell is called an "anti-serial connection" as well. Because of this "anti-serial connection" the intensity of the parasitic current in the serial connection path is drastically reduced.
  • the term “passive storage cell” relates to a storage cell which is devoid of an additional active switching device, like for example a transistor, beneath the switching storage member or switching storage members and the term “passive crossbar array circuit” relates to a crossbar array circuit comprising interconnected passive storage cells.
  • the passive resistive storage cell consists of the serial connection path comprising the pair of two resistive switching storage members.
  • the passive resistive storage cell com- prises nothing but one current path, which is said serial connection path.
  • the passive resistive storage cell can be a unipolar switchable passive resistive storage cell and/or a bipolar switchable passive resistive storage cell.
  • the unipolar switchable passive resistive storage cell is called unipolar passive resistive storage cell
  • the bipolar switchable passive resistive storage cell is called bipolar passive resistive storage cell
  • the unipolar and bipolar switchable passive resistive storage cell is called nonpolar passive resistive storage cell.
  • the terms "unipolar”, "bipolar” and “nonpolar” relate to the current direction through the serial connection path.
  • the passive resistive storage cell is a bipolar passive resistive storage cell. In comparison to the unipolar passive resistive storage cell, the bipolar passive resistive storage cell needs lower currents and therefore has a lower static power dissipation or power loss and better scaling characteristics.
  • one of the resistive switching storage members is in a high resistive state and the other is in a low resistive state, for reading out information a readout- voltage is applied to the resistive storage cell, wherein the readout-voltage is higher than a first voltage limit V th ,i for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit V t h, 2 for switching the corresponding second of the two resistive switching storage members in the high resistive state.
  • the information is written back by apply- ing a negative write-voltage with an absolute value greater than the second voltage limit V t h )2 .
  • the passive resistive storage cell comprises at least two electrodes for external wiring of an arrangement of at least two elements made of active materials (active element) and an additional electrode arranged between said electrodes.
  • the arrangement and at least parts of the two electrodes represents the two storage members.
  • the arrangement is a stack of layers, wherein a first layer is the first active element; a second layer is the additional electrode and a third layer is the second active element.
  • the electrodes are preferably made of one of the following materials: Au, Cu, Ag, Pt, W, Ti, Al, Ni, TiN, Pd, Ir, Os, IrO 2 , RuO 2 , SrRuO 3 and polycrystalline Si.
  • the active materials are at least one of the following materials: Ge x Se ⁇ -x , TiO x , SiO x , CuO x , ZnO x , ZrO x , NiO x , HfO x , WO x , Si 3 N 4 , SrZrO 3 :Cr, Ba, -x Sr x Ti0 3 , MSQ (methyl silsesquioxane or methylated-hydrogen silsesquoxane), HSQ (Hydrogen Silsesquioxane), Cu:TCNQ (Copper: Tetra-Cyanoquinodimethane), (Pr 5 Ca)MnO 3 , (La 5 Ca)MnO 3 , Cu 2 S, Ag 2 S, (Zn 5 Cd)S, Al 2 O 3 , FeO, CoO, MnO 2 , In 2 O 3 , Ta 2 O 5 , Nb 2 O 5 and VO 2 .
  • each of the resistive switching storage members comprises a solid electrolyte being the active material (bipolar resistive switching material) for performing the active switching.
  • the two resistive switching storage members of the bipolar passive resistive storage cell are composed of a linear bipolar resistive switching material.
  • Linear bipolar resistive switching materials are for example: silicon dioxide (SiO 2 ), Methyl silsesquioxane (MSQ) or methylated Hydrogen Silsesquioxane and tungsten oxide (WO 3 ).
  • the bipolar resistive switching storage member is based on at least one of the following active materials: silicon dioxide (SiO 2 ),
  • the resistive storage cell is adapted for an implementation in a crossbar array circuit of a resistive random access memory device.
  • the passive resistive storage cell further comprises a resistive element arranged in the serial connection path for symmetrisation of the characteristic curve of the resistive storage cell.
  • the present invention further relates to a crossbar array circuit of a resistive random access memory device comprising a plurality of aforementioned storage cells, wherein the crossbar array circuit comprises first wiring elements in a first plane, second wiring elements in a second plane and wherein the storage cells are arranged at the cross points arising from a top view on the arrangement of the first and second wiring elements.
  • the wiring ele- ments are electrodes of the passive resistive storage cells.
  • the wiring elements are formed as bars each bar connecting a group of passive resistive storage cells.
  • the size of the crossbar array is e.g. 4F 2 .
  • the feature size F is preferably not higher than 10 nanometres (F ⁇ 10 nm).
  • the first wiring elements are arranged in parallel with each other in the first plane and the second wiring elements arranged in parallel with each other in the second plane.
  • the crossbar array circuit is a three dimensional crossbar array circuit.
  • the present invention further relates to a resistive random access memory device comprising an aforementioned crossbar array circuit, wherein said crossbar array circuit comprises a plurality of aforementioned resistive storage cells.
  • the resistive random access memory further comprises an external circuit for driving the resistive storage cells.
  • the external circuit for driving the resistive storage cells is based on CMOS technology.
  • the bipolar passive resistive storage cells are arranged in a crossbar array circuit of a resistive random access memory device comprising said bipolar resistive storage cells.
  • the cross-bar array circuit is a passive crossbar array circuit comprising only pas- sive resistive storage cells and is devoid of any active switching device being actuatable independently from a current through the wiring elements for wiring the passive resistive storage cells.
  • the first wiring elements are electrically switchable interconnected with a first decoder and the second wiring elements are electrically switchable interconnected with a second decoder.
  • the present invention further relates to a method for reading out information from a bipolar resistive storage cell.
  • the cell comprises a pair of two at least functionally identical resistive switching storage members being connected in series in a serial connection path and electrically anti-parallel orientated within said serial connection path, wherein without external voltage supply one of the resistive switching storage members is in a high resistive state and the other is in a low resistive state, the method comprising the step of applying a readout- voltage to the passive resistive storage cell, wherein the readout-voltage is higher than a first voltage limit V th, i suitable for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit V t h, 2 suit- able for switching the corresponding second of the two resistive switching storage members in the high resistive state.
  • the method further comprises the following step of writing back the information by applying a negative write- voltage with an ab- solute value greater than the second voltage limit V t h, 2 , if the first resistive switching storage member is the one resistive storage member being in the high resistive state before the readout.
  • Fig. 1 shows a cross bar array of a random access memory according to an embodiment of the invention in a perspective view
  • Fig. 2 shows the applied voltage and the resulting current in the serial connection path of the passive resistive storage cell for several read/write cycles in a voltage-time-diagram and a current-time diagram respectively;
  • Fig. 3 shows the cross bar array together with its periphery
  • Fig. 4 shows parasitic paths within the cross bar array
  • Fig. 5 shows a write scheme for writing symmetric RDS cells (resistive double switch cells or passive resistive storage cells);
  • Fig. 6 shows the characteristic I-V-curves of (6A) a positive poled first single cell A (switching storage member), (6B) a negative poled single cell B (second switching storage member) and (6C) the RDS cell (resistive double switch or passive resistive storage cell);
  • Fig. 7 shows the measured characteristic I-V-curve of two GeSe switching members in RDS configuration
  • Fig. 8 shows the applied voltage and the resulting current in the serial connection path of the passive resistive storage cell embedded in a cross bar array; the voltage and current for several read/write cycles in a voltage-time-diagram and a current-time diagram respectively.
  • Fig. 1 is a perspective view of a resistive random access memory (RRAM) device 10 according to a preferred embodiment of the invention.
  • the RRAM device 10 is a multi- layer cross point RRAM device comprising a crossbar array circuit 12.
  • first wiring elements 14 shaped as bars are formed at distances to each other in a first plane on a substrate (not shown) and second wiring elements 16 shaped as bars are formed at distances to each other in a second plane at a predetermined distance from the first plane of the first wiring elements 14.
  • the first wiring elements 14 are first electrodes 18 and the second wiring elements 16 are second electrodes 20 of passive resistive storage cells 22 arranged at the cross points 24 arising from the arrangement of the first and second wiring elements 14, 16 (e.g.
  • bit line 14 and word line 16 are bit line 14 and word line 16.
  • first wiring elements 14 are bit-lines of the crossbar array circuit 12 and the second wiring elements 16 are word-lines of the crossbar array circuit 12.
  • the passive resistive storage cells 22 are called RDS cells (resistive double switch cells) as well.
  • Each of the resistive storage cells 22 comprises a stack of layers 26, 28, 30 between the first and second electrodes 18, 20.
  • the stack shows a first sequence of layers, wherein the first electrode 18 is an inert electrode (e.g. a platinum electrode), the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first layer 26 is an active electrode layer (e.g. Cu layer: Copper layer), the third layer 30 on top of the second layer 28 is a second active layer (e.g. a GeSe layer: Germanium Selenid layer) and the second electrode 20 on top of the third layer is an inert electrode (e.g. a platinum electrode).
  • the first electrode 18 is an inert electrode (e.g. a platinum electrode)
  • the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer)
  • the second layer 28 on top of the first layer 26 is an active electrode layer (e.g. Cu layer: Copper layer)
  • the stack shows a second sequence of layers, wherein the first electrode 18 is an active electrode (e.g. a copper electrode), the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first layer 26 is an inert electrode layer (e.g. Pt layer: platinum layer), the third layer 30 on top of the second layer 28 is a second active layer (e.g. a first active electrode (e.g. a copper electrode), the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first layer 26 is an inert electrode layer (e.g. Pt layer: platinum layer), the third layer 30 on top of the second layer 28 is a second active layer (e.g. a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first
  • GeSe layer Germanium Selenid layer
  • the second electrode 20 on top of the third layer is an active electrode (e.g. a copper electrode).
  • the stack of the resistive storage cells 22 in both embodiments can be depicted in an equivalent circuit as a serial connection path 32 comprising two at least functionally identical resistive switching storage members 34, 36 as shown in the inlay of Fig. 2. Said two resistive switching storage members 34, 36 are electrically anti-parallel orientated but connected in series within the serial connection path 32 (anti-serial interconnected).
  • the first storage member 34 comprises the first electrode 18, the first layer 26 and the second layer 28; the second storage member 36 comprises the second layer 28 and the third layer 30 and the second electrode 20.
  • Each of the resistive storage cells 22 is a passive bipolar resistive storage cell 38, devoid of any additional active switching device beneath the switching storage members.
  • each storage cell 22 is in a high impedance state without external energising as well as with an external energising associated with a voltage higher than a write voltage threshold.
  • the assembling of the passive resistive storage cell 22 results in four different possible states of the cell: 1. only the first resistive switching storage members 34 is in the low resistive state (cell in state O);
  • both resistive switching storage members 34, 36 are in the low resistive state (cell in state 1); 3. both resistive switching storage members 34, 36 are in a low resistive state (cell in state ON); and 4. both resistive switching storage members 34, 36 are in the high resistive state.
  • Fig. 2 shows an applied voltage V and the resulting readout current I in the serial connection path 32 of the passive resistive storage cell 38 for several read/write cycles in a voltage-time- diagram (F-t-diagram) and a current-time diagram (/-/-diagram) respectively.
  • the inlay of Fig. 2 shows the equivalent circuit of the passive resistive storage cell 22 comprising the first storage member 34 and the second storage member 36.
  • Starting point is the first state of the passive resistive storage cell 22 (state 0 of the cell).
  • a positive readout-voltage (being higher than a first voltage limit V t h, ⁇ for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit V t h,2 for switching the corresponding second of the two resistive switching storage members in the high resistive state) is applied to the resistive storage cell 22 (being in the state 0) resulting in no readable current;
  • a negative write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 to the high impedance state and the second resistive switching storage member 36 to the corresponding low impedance state resulting in a negative current peak (and the state 1 of the cell).
  • a positive readout- voltage (below the write voltage-threshold) is applied to the resistive storage cell 22 switching the cell to the third state (state ON) resulting in a measurable readout-current.
  • a negative write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 to the high impedance state and the second resistive switching storage member 36 to the corresponding low impedance state resulting in a negative current peak (and the state 1 of the cell).
  • a positive write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 from the high impedance state to the low impedance state and the second resistive switching storage member 36 from the low impedance state to the corresponding high impedance state resulting in a negative current peak (and the state 0 of the cell).
  • a following sixth time interval 50 is equivalent to the first time interval 40.
  • Fig. 3 shows the resistive random access memory device 10 with the crossbar array circuit 12 being a passive crossbar array circuit comprising only passive resistive storage cells 22.
  • the passive crossbar array circuit 12 is devoid of any active switching device being actuatable independently from a current through the wiring elements 14, 16 for wiring the passive resistive storage cells 22.
  • the first wiring elements 14 are bit lines electrically switchable inter- connected with a first decoder unit 52 and the second wiring elements 16 are word lines electrically switchable (by switches 56) interconnected with a second decoder unit 54 build by at least one control and/or sensing circuit.
  • the resistive random access memory devicelO preferably is a hybrid CMOS/nanoelectronic memory.
  • the hybrid CMOS/nanoelectronic memory consists of a nanoelectronic crossbar array circuit (memory matrix) stacked on top of CMOS logic circuits.
  • the most efficient realisation of a nanoelectronics memory matrix in terms of area and scalability is the passive cross point topology.
  • This topology consists of crossed bit lines (first wiring elements 14) and word lines (second wiring elements 16). Each intersection (or crosspoint 24) of a word and a bit line 14, 16 forms a resistive storage cell 22 (memory cell) with minimum cell area (4 F 2 ).
  • Each passive resistive storage cell 22 is a resistive storage cell 22 comprising an anti-serial connection of two switching storage members 34, 36 (two terminal device) only connected to one of the bit lines 14 and one of the word lines 16.
  • the absence of any active devices like transistors makes the cross point topology completely passive.
  • CMOS part of the hybrid memory The needed control and/or sensing circuit(s) is/are located in the CMOS part of the hybrid memory.
  • Fig. 3 shows a schematic of a possible hybrid memory implementation.
  • the cross point memory concept is directly associated with suitable resistive storage cells 22 (two terminal memory cells).
  • Hysteretic resistors with two stable resistance states are proposed to fit as well as resistive storage cells (memory cells) with cell sizes smaller than 10 nm by 10 nm feasible.
  • resistive storage cells memory cells
  • Each bit line 14 is connected directly with each word line 16 by one corresponding resistive storage cell 22.
  • said bit line is further on connected to said word line via different parasitic current paths 58, 60 including at least one other bit and/or word line and a plurality of other corresponding resistive storage cells 22.
  • the crossbar array concept (cross point matrix concept) according to the invention is based on the passive resistive storage cell 22 comprising a pair of two at least functionally identical resistive switching storage members 34, 36, said two resistive switching storage members 34, 36 are connected in series in a serial connection path 32 and are electrically anti-parallel orientated within the serial connection path 32 (also called RDS: resistive double switches) to avoid parasitic current paths, pattern dependencies and static power dissipation.
  • RDS resistive double switches
  • passive resistive switching cells 22 are used, especially bipolar resistive switching cells 38, comprising two resistive switching storage members 34, 36 in a serial, electrical anti- parallel, configuration as a new memory cell - the resistive double switch (RDS).
  • RDS resistive double switch
  • a 512 x 512 array of resistive storage cells 22 comprising a pair of two at least functionally identical resistive switching storage members 34, 36 leads to voltage swing of 86,7% V dd ,when a typical resistivity of 10 8 ⁇ is assumed in the high resistive state and 2 k ⁇ in the low resistive state.
  • the bipolar passive resistive storage cell 38 or resistive double switch (RDS) consists of two serial connected bipolar resistive switching members, as depicted in Fig. 6A - 6C.
  • the first member A (equates to the first resistive switching storage member 34) is poled in positive direction
  • the second member other cell B (equates to the second resistive switching storage member 36) in negative direction.
  • Both cells A, B are assumed be equal in terms of switching voltage, off-resistance and on-resistance.
  • the resulting RDS is again a "two terminal device" and so suitable to be implemented into a passive crossbar array circuit 12.
  • Fig 6A shows the characteristic I-V-curve (first switching curve) of a positive poled first single cell A corresponding to a triangular voltage being applied to said positive poled single first cell A according to the inset voltage- vs-time (V-t) diagram.
  • the first cell A is initially in a high resistive state H corresponding to section Al of the first switching curve and switches at a voltage limit V th to the low resistive state L corresponding to section A2 of the first curve.
  • the cell stays in this low resistive state L also if the applied voltage becomes negative (corresponding to section A3) and switches back to the high resistive state H at the negative value of the voltage limit (-V th ) corresponding to section A4.
  • Fig 6B shows the characteristic I-V-curve (second switching curve) of a negative poled second single cell B corresponding to a triangular voltage being applied to said negative poled single first cell B according to the inset V-t-diagram.
  • Cell B is initially in the low resistive state L (corresponding to section Bl) and switches at the voltage limit V th to the high resistive state H (corresponding to section B2).
  • the cell B stays in this high resistive state H also if the applied voltage becomes negative (corresponding to section B3) and switches back to the low resistive state L the negative value of the voltage limit (-V t h) corresponding to section B4.
  • Fig 6C shows the characteristic I-V-curve (third curve) of resistive storage cell 22 corre- sponding to a triangular voltage being applied to said resistive storage cell 22 according to the inset V-t- diagram.
  • the first switching storage member 34 of the resistive storage cell 22 (corresponding to cell A) is initially in the high resistive state H
  • the second switching storage member 36 of the resistive storage cell 22 (corresponding to cell B) is initially in the low re- sistive state L. Because of the series connection the overall state is high resistive H' at the first section Cl of the curve. Almost all voltage drops over the first switching storage member 34 until a first voltage limit V th, i is reached and said first switching storage member 34 switches to the low resistive state L.
  • the overall state of the resistive storage cell 22 is the low resistive state L' at section C2 because the second switching storage member 36 stays at the low resistive state L.
  • the second switching storage member 36 switches to high resistive state H which leads to an overall high resistive state H' at region C3.
  • the first switching storage member 34 stays at the low resistive state L and the second switching storage member 36 stays at high resistive state H (corresponding to section C4).
  • the triangular voltage becomes negative the first switching storage member 34 stays at low resistive state L and the second switching storage member 36 at the high resistive state H corresponding to section C5 until a negative first voltage limit -V t h,i is reached.
  • the second switching storage member 36 over which almost all voltage drops, then switches to the low resistive state L and the first switching storage member 34 stays at the low resistive state L, which leads again to an overall low resistive state L' corresponding to section C6. If the voltage reaches a negative second voltage limit -V th , 2 the first switching storage member 34 switches back to the high resistive state H and the overall state becomes a high resistive state H' again (Corresponding to section C7 and C8).
  • the information is binary coded and there are four states. Both single cells can be in a high resistive state denoted as HH, one in a low resistive state and the other in a high resistive state HL or LH and both can be in the low resistive state denoted LL. HH is only possible as initial state and can be left with an initial write step.
  • HL and LH are the binary states. HL e.g. represents a logical T and LH a logical O'. LL is the read state and is only reached when reading a ' 1 '.
  • RDS cells resistive switching storage members
  • a read voltage pulse larger than V t h,i but smaller than V t h, 2 is applied (compare Fig. 6C). If the RDS is in state T and the read voltage is applied, the resistance of cell A changes from high to low. Because both cells are now low resistive (LL), the form a voltage divider with equal voltage drops. This means that the voltage drop over cell B does not exceed the threshold voltage which prevents cell B from becoming high resistive. This configuration leads to a significant current flow through the device which can easily be sensed. To restore the information after reading, a write pulse must be applied (-V th , 2 ) to write the information back.
  • a voltage pulse larger than +V t h, 2 (for writing to state '0') or -V th,2 (for writing to state T) must be applied.
  • the double switch Independent from the initial state of the cells, the double switch can be brought to a well defined state by applying a write pulse.
  • the voltage drop over not accessed is lowered to 1/3 V dd for symmetric devices by application of a special voltage scheme (Fig. 5).
  • Fig. 8 an exemplary pulse sequence and the resulting read currents are shown.
  • RDS-RAM All not accessed RDS have the same large resistance which leads to a very strong parasitic path reduction and static power dissipation reduction. The interaction between not accessed cells is reduced to a minimum, so very large arrays can be built. No pattern dependencies occur in RDS-RAM which simplifies external CMOS circuits. Due to cross point organisation cell areas 4 F 2 /n (n stacks) are possible (3D stacked RDS-RAM).
  • Fig. 8 exemplary shows applied voltage pulse to RDS cells in a cross point array. The resulting current flows are also shown.
  • the accessed RDS is in state '0' initially. Following operations are performed: read, write T, read, write back, write '0' and read. Only if the RDS was in state ' 1 ' a relevant current can be measured in the read phase.
  • the voltage over not accessed RDS cells in the cross point array is always below the first threshold voltage. This is achieved by the application of the writing scheme.
  • the present invention further relates to a method for writing information into one of a plurality of aforementioned bipolar passive resistive storage cells, the method comprising: applying a writing voltage pulse of a first polarity to the resistive storage cells to switch said cells into a first state; and afterwards - applying a second writing voltage pulse of the first polarity or the corresponding second polarity to the resistive storage cell, wherein the magnitude of each of the writing voltage pulses is higher than a writing voltage threshold (second voltage limit V t h,2).
  • a writing voltage threshold second voltage limit V t h,2).
  • the bipolar passive resistive storage cells are arranged in a crossbar array circuit of a resistive random access memory device comprising said bipolar resistive storage cells.
  • the present invention further relates to a method for reading information stored in one of a plurality of bipolar passive resistive storage cells, especially of the aforementioned bipolar passive resistive storage cells, the method comprising: applying a writing voltage pulse of a first polarity to the resistive storage cells to switch said cells into a first state, and afterwards applying a reading voltage pulse of the corresponding second polarity to the one resistive storage cell and detecting the resulting current, wherein the magnitude of the writing voltage pulse is higher than a writing voltage threshold (second voltage limit V t h, 2 ) and the magnitude of the reading voltage pulse is lower than a writing voltage threshold.
  • a writing voltage threshold second voltage limit V t h, 2

Abstract

The invention relates to a resistive storage cell. According to the invention said resistive storage cell is a passive resistive storage cell (22) comprising a pair of two at least functionally identical resistive switching storage members (34, 36), said two resistive switching storage members (34, 36) are connected in series in a serial connection path (32) and are electrically anti-parallel orientated within the serial connection path (32). The invention further relates to a corresponding crossbar array circuit (12) comprising a plurality of said resistive storage cells (22), a corresponding resistive random access memory device (10) and a method for reading out information from a bipolar resistive storage cell.

Description

Resistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method
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The invention relates to a resistive storage cell, a crossbar array circuit, a resistive random access memory device comprising said resistive storage cells and a method for reading out information from a bipolar resistive storage cell.
15
In recent years several new concepts of random-access memories (RAM) arise. One of these concepts is a memory device based on ECM memory cells (ECM: electrochemical metallization), wherein these cells sometimes were termed PMC memory cells (PMC: programmable metallization cell) as well. The ECM based memory was developed to replace conventional 0 memories based on charge, like the flash memory, providing higher memory density. An ECM memory cell is in general made of two solid metal electrodes, wherein one electrode is a relatively inert first electrode and the other electrode is an electrochemically active second electrode. The ECM memory cell further comprises a thin film of an electrolyte located between said two electrodes. The ECM technology is based on the physical re-location of ions 5 within a solid electrolyte.
The dedicated random-access memory is called RRAM (RRAM: resistive random-access memory), like for example the conductive-bridging RAM (CBRAM). Each of the memory units of a CBRAM device comprises a ECM memory cell and a control transistor. 0 The basic idea of the storage cells of RRAM devices is that the storage cell comprises a dielectric material, which is normally insulating. This dielectric material can be made to conduct through at least one internal conduction path formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms, including defects, metal migration or others. Once the conduction path is formed, it can be reset by cutting of the path which results in high resistance, or can be set, resulting in lower resistance. The adjustment of the corresponding resistivity can be carried out by applying an appropriately voltage or by changes of a related interface.
In a first known crossbar array-concept, the RRAM device comprises passive storage cells, each consisting of a current path with a single resistive switching storage member. In this concept a noticeable parasitic current occurs. In a second concept, each of the passive storage cells of the RRAM device comprises a current path with single resistive switching storage member and a passive but nonlinear member, e. g. a diode, both members connected in series within the current path to reduce the parasitic current, but even in this second concept a non- negligible parasitic current occurs.
WO 2006/037432 depicts a CBRAM memory circuit with a ECM memory cell (lTIR-cell) and an evaluation circuit for evaluation of a read out process by means of a reference memory cell, said memory cell comprising a resistance memory element, an active switching element and said reference memory cell comprising a reference resistance, wherein the memory cell is mounted between a ground connection and a capacitor and the reference memory cell is mounted between the ground connection and a reference capacitor.
It is an object of the present invention to provide a non-volatile resistive storage cell, corresponding crossbar array circuit and corresponding resistive random access memory device with improved read-out performance. The object of the invention is achieved by the features of claims 1 , 9 and 1 1.
The resistive storage cell is a passive resistive storage cell comprising a pair of two at least functionally identical resistive switching storage members, said two switching storage mem- bers are connected in series in a serial connection (current) path and are electrically anti- parallel orientated within the serial connection path. In the following, the connection of the anti-parallel oriented two switching storage members within the serial connection path of the passive storage cell is called an "anti-serial connection" as well. Because of this "anti-serial connection" the intensity of the parasitic current in the serial connection path is drastically reduced.
With respect to the present invention, the term "passive storage cell" relates to a storage cell which is devoid of an additional active switching device, like for example a transistor, beneath the switching storage member or switching storage members and the term "passive crossbar array circuit" relates to a crossbar array circuit comprising interconnected passive storage cells.
Preferably, the passive resistive storage cell consists of the serial connection path comprising the pair of two resistive switching storage members. The passive resistive storage cell com- prises nothing but one current path, which is said serial connection path.
Generally, the passive resistive storage cell can be a unipolar switchable passive resistive storage cell and/or a bipolar switchable passive resistive storage cell. The unipolar switchable passive resistive storage cell is called unipolar passive resistive storage cell, the bipolar switchable passive resistive storage cell is called bipolar passive resistive storage cell and the unipolar and bipolar switchable passive resistive storage cell is called nonpolar passive resistive storage cell. The terms "unipolar", "bipolar" and "nonpolar" relate to the current direction through the serial connection path. According to a first embodiment of the invention, the passive resistive storage cell is a bipolar passive resistive storage cell. In comparison to the unipolar passive resistive storage cell, the bipolar passive resistive storage cell needs lower currents and therefore has a lower static power dissipation or power loss and better scaling characteristics.
Without external voltage supply one of the resistive switching storage members is in a high resistive state and the other is in a low resistive state, for reading out information a readout- voltage is applied to the resistive storage cell, wherein the readout-voltage is higher than a first voltage limit Vth,i for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit Vth,2 for switching the corresponding second of the two resistive switching storage members in the high resistive state. Preferably, if the first resistive switching storage member is the one resistive storage member being in the high resistive state before the read-out, the information is written back by apply- ing a negative write-voltage with an absolute value greater than the second voltage limit Vth)2.
According to another embodiment of the invention, the passive resistive storage cell comprises at least two electrodes for external wiring of an arrangement of at least two elements made of active materials (active element) and an additional electrode arranged between said electrodes. The arrangement and at least parts of the two electrodes represents the two storage members. Preferably, the arrangement is a stack of layers, wherein a first layer is the first active element; a second layer is the additional electrode and a third layer is the second active element.
The electrodes are preferably made of one of the following materials: Au, Cu, Ag, Pt, W, Ti, Al, Ni, TiN, Pd, Ir, Os, IrO2, RuO2, SrRuO3 and polycrystalline Si. The active materials are at least one of the following materials: GexSeι-x, TiOx, SiOx, CuOx, ZnOx, ZrOx, NiOx, HfOx, WOx, Si3N4, SrZrO3 :Cr, Ba,-xSrxTi03, MSQ (methyl silsesquioxane or methylated-hydrogen silsesquoxane), HSQ (Hydrogen Silsesquioxane), Cu:TCNQ (Copper: Tetra-Cyanoquinodimethane), (Pr5Ca)MnO3, (La5Ca)MnO3, Cu2S, Ag2S, (Zn5Cd)S, Al2O3, FeO, CoO, MnO2, In2O3, Ta2O5, Nb2O5 and VO2.
Generally, each of the resistive switching storage members comprises a solid electrolyte being the active material (bipolar resistive switching material) for performing the active switching. According to yet another embodiment of the invention, the two resistive switching storage members of the bipolar passive resistive storage cell are composed of a linear bipolar resistive switching material. Linear bipolar resistive switching materials are for example: silicon dioxide (SiO2), Methyl silsesquioxane (MSQ) or methylated Hydrogen Silsesquioxane and tungsten oxide (WO3).
Preferably, the bipolar resistive switching storage member is based on at least one of the following active materials: silicon dioxide (SiO2),
Methyl silsesquioxane (MSQ) or methylated Hydrogen Silsesquioxane, tungsten oxide (WO3), especially tungsten(VI) oxide (WO3), - germanium selenide (GeSe), titanium dioxide (TiO2) and strontium titanate (SrTiO3).
According to another embodiment of the invention, the resistive storage cell is adapted for an implementation in a crossbar array circuit of a resistive random access memory device. According to yet another embodiment of the invention, the passive resistive storage cell further comprises a resistive element arranged in the serial connection path for symmetrisation of the characteristic curve of the resistive storage cell.
The present invention further relates to a crossbar array circuit of a resistive random access memory device comprising a plurality of aforementioned storage cells, wherein the crossbar array circuit comprises first wiring elements in a first plane, second wiring elements in a second plane and wherein the storage cells are arranged at the cross points arising from a top view on the arrangement of the first and second wiring elements. Preferably the wiring ele- ments are electrodes of the passive resistive storage cells. Especially the wiring elements are formed as bars each bar connecting a group of passive resistive storage cells. The size of the crossbar array is e.g. 4F2. The feature size F is preferably not higher than 10 nanometres (F < 10 nm). Preferably, the first wiring elements are arranged in parallel with each other in the first plane and the second wiring elements arranged in parallel with each other in the second plane.
According to another preferred embodiment of the invention, the crossbar array circuit is a three dimensional crossbar array circuit.
The present invention further relates to a resistive random access memory device comprising an aforementioned crossbar array circuit, wherein said crossbar array circuit comprises a plurality of aforementioned resistive storage cells. The resistive random access memory further comprises an external circuit for driving the resistive storage cells.
According to a preferred embodiment of the invention, the external circuit for driving the resistive storage cells is based on CMOS technology. Preferably the bipolar passive resistive storage cells are arranged in a crossbar array circuit of a resistive random access memory device comprising said bipolar resistive storage cells.
Preferably, the cross-bar array circuit is a passive crossbar array circuit comprising only pas- sive resistive storage cells and is devoid of any active switching device being actuatable independently from a current through the wiring elements for wiring the passive resistive storage cells. The first wiring elements are electrically switchable interconnected with a first decoder and the second wiring elements are electrically switchable interconnected with a second decoder.
The present invention further relates to a method for reading out information from a bipolar resistive storage cell. According to the invention the cell comprises a pair of two at least functionally identical resistive switching storage members being connected in series in a serial connection path and electrically anti-parallel orientated within said serial connection path, wherein without external voltage supply one of the resistive switching storage members is in a high resistive state and the other is in a low resistive state, the method comprising the step of applying a readout- voltage to the passive resistive storage cell, wherein the readout-voltage is higher than a first voltage limit Vth,i suitable for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit Vth,2 suit- able for switching the corresponding second of the two resistive switching storage members in the high resistive state.
According to a preferred embodiment of the invention, the method further comprises the following step of writing back the information by applying a negative write- voltage with an ab- solute value greater than the second voltage limit Vth,2, if the first resistive switching storage member is the one resistive storage member being in the high resistive state before the readout. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
In the drawings:
Fig. 1 shows a cross bar array of a random access memory according to an embodiment of the invention in a perspective view;
Fig. 2 shows the applied voltage and the resulting current in the serial connection path of the passive resistive storage cell for several read/write cycles in a voltage-time-diagram and a current-time diagram respectively;
Fig. 3 shows the cross bar array together with its periphery;
Fig. 4 shows parasitic paths within the cross bar array;
Fig. 5 shows a write scheme for writing symmetric RDS cells (resistive double switch cells or passive resistive storage cells);
Fig. 6 shows the characteristic I-V-curves of (6A) a positive poled first single cell A (switching storage member), (6B) a negative poled single cell B (second switching storage member) and (6C) the RDS cell (resistive double switch or passive resistive storage cell);
Fig. 7 shows the measured characteristic I-V-curve of two GeSe switching members in RDS configuration; and Fig. 8 shows the applied voltage and the resulting current in the serial connection path of the passive resistive storage cell embedded in a cross bar array; the voltage and current for several read/write cycles in a voltage-time-diagram and a current-time diagram respectively.
Fig. 1 is a perspective view of a resistive random access memory (RRAM) device 10 according to a preferred embodiment of the invention. The RRAM device 10 is a multi- layer cross point RRAM device comprising a crossbar array circuit 12. Referring to Fig. 1, first wiring elements 14 shaped as bars are formed at distances to each other in a first plane on a substrate (not shown) and second wiring elements 16 shaped as bars are formed at distances to each other in a second plane at a predetermined distance from the first plane of the first wiring elements 14. The first wiring elements 14 are first electrodes 18 and the second wiring elements 16 are second electrodes 20 of passive resistive storage cells 22 arranged at the cross points 24 arising from the arrangement of the first and second wiring elements 14, 16 (e.g. bit line 14 and word line 16). For example the first wiring elements 14 are bit-lines of the crossbar array circuit 12 and the second wiring elements 16 are word-lines of the crossbar array circuit 12. The passive resistive storage cells 22 are called RDS cells (resistive double switch cells) as well.
Each of the resistive storage cells 22 comprises a stack of layers 26, 28, 30 between the first and second electrodes 18, 20.
In a first embodiment of the invention the stack shows a first sequence of layers, wherein the first electrode 18 is an inert electrode (e.g. a platinum electrode), the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first layer 26 is an active electrode layer (e.g. Cu layer: Copper layer), the third layer 30 on top of the second layer 28 is a second active layer (e.g. a GeSe layer: Germanium Selenid layer) and the second electrode 20 on top of the third layer is an inert electrode (e.g. a platinum electrode).
In a second embodiment of the invention the stack shows a second sequence of layers, wherein the first electrode 18 is an active electrode (e.g. a copper electrode), the first layer 26 on top of the first electrode 18 is a first active layer (e.g. a GeSe layer: Germanium Selenid layer), the second layer 28 on top of the first layer 26 is an inert electrode layer (e.g. Pt layer: platinum layer), the third layer 30 on top of the second layer 28 is a second active layer (e.g. a
GeSe layer: Germanium Selenid layer) and the second electrode 20 on top of the third layer is an active electrode (e.g. a copper electrode).
The stack of the resistive storage cells 22 in both embodiments can be depicted in an equivalent circuit as a serial connection path 32 comprising two at least functionally identical resistive switching storage members 34, 36 as shown in the inlay of Fig. 2. Said two resistive switching storage members 34, 36 are electrically anti-parallel orientated but connected in series within the serial connection path 32 (anti-serial interconnected). The first storage member 34 comprises the first electrode 18, the first layer 26 and the second layer 28; the second storage member 36 comprises the second layer 28 and the third layer 30 and the second electrode 20. Each of the resistive storage cells 22 is a passive bipolar resistive storage cell 38, devoid of any additional active switching device beneath the switching storage members.
Regarding to the anti-serial interconnection of the resistive switching storage members 34, 36, each storage cell 22 is in a high impedance state without external energising as well as with an external energising associated with a voltage higher than a write voltage threshold.
The assembling of the passive resistive storage cell 22 results in four different possible states of the cell: 1. only the first resistive switching storage members 34 is in the low resistive state (cell in state O);
2. only the second resistive switching storage members 36 is in the low resistive state (cell in state 1); 3. both resistive switching storage members 34, 36 are in a low resistive state (cell in state ON); and 4. both resistive switching storage members 34, 36 are in the high resistive state.
Fig. 2 shows an applied voltage V and the resulting readout current I in the serial connection path 32 of the passive resistive storage cell 38 for several read/write cycles in a voltage-time- diagram (F-t-diagram) and a current-time diagram (/-/-diagram) respectively. The inlay of Fig. 2 shows the equivalent circuit of the passive resistive storage cell 22 comprising the first storage member 34 and the second storage member 36.
Starting point is the first state of the passive resistive storage cell 22 (state 0 of the cell). In a first time interval 40 a positive readout-voltage (being higher than a first voltage limit Vth,ι for switching a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit Vth,2 for switching the corresponding second of the two resistive switching storage members in the high resistive state) is applied to the resistive storage cell 22 (being in the state 0) resulting in no readable current; in a second time interval 42 a negative write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 to the high impedance state and the second resistive switching storage member 36 to the corresponding low impedance state resulting in a negative current peak (and the state 1 of the cell). In a third time interval 44 a positive readout- voltage (below the write voltage-threshold) is applied to the resistive storage cell 22 switching the cell to the third state (state ON) resulting in a measurable readout-current. In a following fourth time interval 46 ("write back interval") again a negative write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 to the high impedance state and the second resistive switching storage member 36 to the corresponding low impedance state resulting in a negative current peak (and the state 1 of the cell). In a following fifth time interval 48 a positive write-voltage is applied to the resistive storage cell 22 switching the first resistive switching storage member 34 from the high impedance state to the low impedance state and the second resistive switching storage member 36 from the low impedance state to the corresponding high impedance state resulting in a negative current peak (and the state 0 of the cell). At the same time the starting point is reached again. A following sixth time interval 50 is equivalent to the first time interval 40.
Other advantages will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description of further aspects of the invention.
Fig. 3 shows the resistive random access memory device 10 with the crossbar array circuit 12 being a passive crossbar array circuit comprising only passive resistive storage cells 22. The passive crossbar array circuit 12 is devoid of any active switching device being actuatable independently from a current through the wiring elements 14, 16 for wiring the passive resistive storage cells 22. The first wiring elements 14 are bit lines electrically switchable inter- connected with a first decoder unit 52 and the second wiring elements 16 are word lines electrically switchable (by switches 56) interconnected with a second decoder unit 54 build by at least one control and/or sensing circuit.
The resistive random access memory devicelO preferably is a hybrid CMOS/nanoelectronic memory. The hybrid CMOS/nanoelectronic memory consists of a nanoelectronic crossbar array circuit (memory matrix) stacked on top of CMOS logic circuits. The most efficient realisation of a nanoelectronics memory matrix in terms of area and scalability is the passive cross point topology. This topology consists of crossed bit lines (first wiring elements 14) and word lines (second wiring elements 16). Each intersection (or crosspoint 24) of a word and a bit line 14, 16 forms a resistive storage cell 22 (memory cell) with minimum cell area (4 F2). Each passive resistive storage cell 22 is a resistive storage cell 22 comprising an anti-serial connection of two switching storage members 34, 36 (two terminal device) only connected to one of the bit lines 14 and one of the word lines 16. The absence of any active devices like transistors makes the cross point topology completely passive.
The needed control and/or sensing circuit(s) is/are located in the CMOS part of the hybrid memory. Fig. 3 shows a schematic of a possible hybrid memory implementation. The cross point memory concept is directly associated with suitable resistive storage cells 22 (two terminal memory cells). Hysteretic resistors with two stable resistance states are proposed to fit as well as resistive storage cells (memory cells) with cell sizes smaller than 10 nm by 10 nm feasible. But the implementation of hysteretic resistors in passive cross point matrices leads to a plurality of problems.
Each bit line 14 is connected directly with each word line 16 by one corresponding resistive storage cell 22. Within the passive crossbar array circuit said bit line is further on connected to said word line via different parasitic current paths 58, 60 including at least one other bit and/or word line and a plurality of other corresponding resistive storage cells 22.
Because of the parasitic current paths 58, 60 shown in Fig. 4, the measureable voltage swing in the read phase at the sense amplifier lowers with raising array size and is very much pattern depended. In a worst case scenario, an eight by eight (8 x 8) array of resistive storage cells consisting of only one resistive switching storage member leads to voltage swing of only 10% Vdd- Low voltages swings and pattern dependencies necessitate large sense amplifier and control overhead and restrict deployable cross point memories to small sizes and limit access time. Also static power dissipation (in read and write phase) through parasitic current paths makes this approach unattractive. The crossbar array concept (cross point matrix concept) according to the invention is based on the passive resistive storage cell 22 comprising a pair of two at least functionally identical resistive switching storage members 34, 36, said two resistive switching storage members 34, 36 are connected in series in a serial connection path 32 and are electrically anti-parallel orientated within the serial connection path 32 (also called RDS: resistive double switches) to avoid parasitic current paths, pattern dependencies and static power dissipation. Instead of using single resistive switching cells (consisting of only one resistive switching storage member), passive resistive switching cells 22 are used, especially bipolar resistive switching cells 38, comprising two resistive switching storage members 34, 36 in a serial, electrical anti- parallel, configuration as a new memory cell - the resistive double switch (RDS). A 512 x 512 array of resistive storage cells 22 comprising a pair of two at least functionally identical resistive switching storage members 34, 36 leads to voltage swing of 86,7% Vdd ,when a typical resistivity of 108 Ω is assumed in the high resistive state and 2 kΩ in the low resistive state.
The bipolar passive resistive storage cell 38 or resistive double switch (RDS) consists of two serial connected bipolar resistive switching members, as depicted in Fig. 6A - 6C. The first member A (equates to the first resistive switching storage member 34) is poled in positive direction, the second member other cell B (equates to the second resistive switching storage member 36) in negative direction. Both cells A, B are assumed be equal in terms of switching voltage, off-resistance and on-resistance. The resulting RDS is again a "two terminal device" and so suitable to be implemented into a passive crossbar array circuit 12.
Fig 6A shows the characteristic I-V-curve (first switching curve) of a positive poled first single cell A corresponding to a triangular voltage being applied to said positive poled single first cell A according to the inset voltage- vs-time (V-t) diagram. The triangular voltage starts at V = 0, goes up to a maximum + Vmaχ, down to a minimum -Vmax and back to V = 0. The first cell A is initially in a high resistive state H corresponding to section Al of the first switching curve and switches at a voltage limit Vth to the low resistive state L corresponding to section A2 of the first curve. The cell stays in this low resistive state L also if the applied voltage becomes negative (corresponding to section A3) and switches back to the high resistive state H at the negative value of the voltage limit (-Vth) corresponding to section A4.
The inclination of sections Al and A4 respectively corresponds to the high resistive state H and the inclination of sections A2 and A3 respectively corresponds to the low resistive state L of the first single cell A.
Fig 6B shows the characteristic I-V-curve (second switching curve) of a negative poled second single cell B corresponding to a triangular voltage being applied to said negative poled single first cell B according to the inset V-t-diagram. Cell B is initially in the low resistive state L (corresponding to section Bl) and switches at the voltage limit Vth to the high resistive state H (corresponding to section B2). The cell B stays in this high resistive state H also if the applied voltage becomes negative (corresponding to section B3) and switches back to the low resistive state L the negative value of the voltage limit (-Vth) corresponding to section B4.
The inclination of sections Bl and B4 respectively corresponds to the low resistive state L and the inclination of sections B2 and B3 respectively corresponds to the high resistive state H of the second single cell B.
Fig 6C shows the characteristic I-V-curve (third curve) of resistive storage cell 22 corre- sponding to a triangular voltage being applied to said resistive storage cell 22 according to the inset V-t- diagram. The first switching storage member 34 of the resistive storage cell 22 (corresponding to cell A) is initially in the high resistive state H, the second switching storage member 36 of the resistive storage cell 22 (corresponding to cell B) is initially in the low re- sistive state L. Because of the series connection the overall state is high resistive H' at the first section Cl of the curve. Almost all voltage drops over the first switching storage member 34 until a first voltage limit Vth,i is reached and said first switching storage member 34 switches to the low resistive state L. The overall state of the resistive storage cell 22 is the low resistive state L' at section C2 because the second switching storage member 36 stays at the low resistive state L. When the triangular voltage reaches a second voltage limit Vth,2 the second switching storage member 36 switches to high resistive state H which leads to an overall high resistive state H' at region C3. For all applied positive voltages the first switching storage member 34 stays at the low resistive state L and the second switching storage member 36 stays at high resistive state H (corresponding to section C4). When the triangular voltage becomes negative the first switching storage member 34 stays at low resistive state L and the second switching storage member 36 at the high resistive state H corresponding to section C5 until a negative first voltage limit -Vth,i is reached. The second switching storage member 36, over which almost all voltage drops, then switches to the low resistive state L and the first switching storage member 34 stays at the low resistive state L, which leads again to an overall low resistive state L' corresponding to section C6. If the voltage reaches a negative second voltage limit -Vth,2 the first switching storage member 34 switches back to the high resistive state H and the overall state becomes a high resistive state H' again (Corresponding to section C7 and C8).
In the RDS the information is binary coded and there are four states. Both single cells can be in a high resistive state denoted as HH, one in a low resistive state and the other in a high resistive state HL or LH and both can be in the low resistive state denoted LL. HH is only possible as initial state and can be left with an initial write step. HL and LH are the binary states. HL e.g. represents a logical T and LH a logical O'. LL is the read state and is only reached when reading a ' 1 '. Note that for either state '0' or state T the overall resistance of the RDS is the same: Rtotai = RH+RL~ RH- This property of hidden information is a main feature of RDS. The principle functionality of a resistive double switch is shown by measurements of GeSe RDS-cells. In Fig. 7 such measured curve can be seen.
The reading behaviour of RDS cells (resistive switching storage members) in a cross point array is very advantageous compared to cross point arrays with single cells.
In the first step a read voltage pulse larger than Vth,i but smaller than Vth,2 is applied (compare Fig. 6C). If the RDS is in state T and the read voltage is applied, the resistance of cell A changes from high to low. Because both cells are now low resistive (LL), the form a voltage divider with equal voltage drops. This means that the voltage drop over cell B does not exceed the threshold voltage which prevents cell B from becoming high resistive. This configuration leads to a significant current flow through the device which can easily be sensed. To restore the information after reading, a write pulse must be applied (-Vth,2) to write the information back.
If the RDS is in state O', no switching occurs when the read voltage is applied. Cell B remains high resistive so that the total resistance remains large. This only leads to a very small current flow. In this case no write back operation is required.
For writing the RDS to a well defined state a voltage pulse larger than +Vth,2 (for writing to state '0') or -Vth,2 (for writing to state T) must be applied. Independent from the initial state of the cells, the double switch can be brought to a well defined state by applying a write pulse. To prevent not accessed cells from switching, the voltage drop over not accessed is lowered to 1/3 Vdd for symmetric devices by application of a special voltage scheme (Fig. 5).
In Fig. 8 an exemplary pulse sequence and the resulting read currents are shown.
All not accessed RDS have the same large resistance which leads to a very strong parasitic path reduction and static power dissipation reduction. The interaction between not accessed cells is reduced to a minimum, so very large arrays can be built. No pattern dependencies occur in RDS-RAM which simplifies external CMOS circuits. Due to cross point organisation cell areas 4 F2/n (n stacks) are possible (3D stacked RDS-RAM).
Fig. 8 exemplary shows applied voltage pulse to RDS cells in a cross point array.The resulting current flows are also shown. The accessed RDS is in state '0' initially. Following operations are performed: read, write T, read, write back, write '0' and read. Only if the RDS was in state ' 1 ' a relevant current can be measured in the read phase. The voltage over not accessed RDS cells in the cross point array is always below the first threshold voltage. This is achieved by the application of the writing scheme.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
The present invention further relates to a method for writing information into one of a plurality of aforementioned bipolar passive resistive storage cells, the method comprising: applying a writing voltage pulse of a first polarity to the resistive storage cells to switch said cells into a first state; and afterwards - applying a second writing voltage pulse of the first polarity or the corresponding second polarity to the resistive storage cell, wherein the magnitude of each of the writing voltage pulses is higher than a writing voltage threshold (second voltage limit Vth,2).
Preferably the bipolar passive resistive storage cells are arranged in a crossbar array circuit of a resistive random access memory device comprising said bipolar resistive storage cells. The present invention further relates to a method for reading information stored in one of a plurality of bipolar passive resistive storage cells, especially of the aforementioned bipolar passive resistive storage cells, the method comprising: applying a writing voltage pulse of a first polarity to the resistive storage cells to switch said cells into a first state, and afterwards applying a reading voltage pulse of the corresponding second polarity to the one resistive storage cell and detecting the resulting current, wherein the magnitude of the writing voltage pulse is higher than a writing voltage threshold (second voltage limit Vth,2) and the magnitude of the reading voltage pulse is lower than a writing voltage threshold. Especially the magnitude of the reading voltage pulse is higher than a first voltage limit Vth.i.
Other variations to be disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope.

Claims

Claims
1. A resistive storage cell, said resistive storage cell is a passive resistive storage cell (22) comprising a pair of two at least functionally identical resistive switching storage members
5 (34, 36), said two resistive switching storage members (34, 36) are connected in series in a serial connection path (32) and are electrically anti-parallel orientated within the serial connection path (32).
2. The resistive storage cell according to claim 1, wherein the passive resistive storage 10 cell is a bipolar passive resistive storage cell (38).
3. The resistive storage cell according to claim 1 or 2, wherein the passive resistive storage cell (22) comprises at least two electrodes (18, 20) for external wiring of an arrangement of at least two elements (26, 30) made of active materials and an additional electrode (28)
15 arranged between said electrodes (18, 20).
4. The resistive storage cell according to one of claims 2 and 3, wherein the two resistive switching storage members (34, 36) of the bipolar passive resistive storage cell (38) are com-
I posed of a linear bipolar resistive switching material.
20
5. The resistive storage cell according to claim 4, wherein the linear bipolar resistive switching material is based on at least one of the following active materials: silicon dioxide; methyl silsesquioxane or methylated-hydrogen silsesquioxane; 25 - tungsten oxide; germanium selenide; titanium dioxide; and strontium titanate.
6. The resistive storage cell according to claim 1 , wherein the passive resistive storage cell (22) is adapted for an implementation in a crossbar array circuit (12) of a resistive random access memory device (10).
5
7. The resistive storage cell according to any of claims 1 to 6, wherein the passive resistive storage cell (22) further comprises a resistive element arranged in the serial connection
, path (32).
10 8. Use of the resistive storage cell according to any of claims 1 to 7 in a crossbar array circuit (12) of a resistive random access memory device (10).
9. A crossbar array circuit of a resistive random access memory device (10) comprising resistive storage cells (22) according to any of claims 1 to 8, wherein the crossbar array circuit 15 (12) comprises first wiring elements (14) arranged in a first plane, second wiring elements (16) arranged in a second plane and wherein the resistive storage cells (22) are arranged at the cross points (24) arising from the arrangement of the first and second wiring elements (14, 16).
20 10. The crossbar array circuit according to claim 9, wherein the first wiring elements (14) are arranged in parallel with each other and the second wiring elements (16) arranged in parallel with each other.
11. The crossbar array circuit according to claim 9 or 10, wherein the crossbar array cir- 25 cuit (12) is a three dimensional crossbar array circuit.
12. A resistive random access memory device comprising a crossbar array circuit (12) according any of claims 9 to 1 1.
13. The resistive random access memory device according to claim 12, wherein the crossbar array circuit (12) is a passive crossbar array circuit (12) comprising only passive resistive storage cells (22) and is devoid of any active switching device being actuatable independently from a current through the wiring elements (14, 16) for wiring the passive resistive storage cells (22).
14. A method for reading out information from a bipolar resistive storage cell, the cell comprising a pair of two at least functionally identical resistive switching storage members being connected in series in a serial connection path and electrically anti-parallel orientated within said serial connection path, wherein without external voltage supply one of the resistive switching storage members is in a high resistive state and the other is in a low resistive state, the method comprising the step of applying a readout-voltage to the passive resistive storage cell, wherein the readout-voltage is higher than a first voltage limit (Vth,i) for switch- ing a first of the two resistive switching storage members in the low resistive state and lower than a second voltage limit (Vth,2) for switching the corresponding second of the two resistive switching storage members in the high resistive state.
15. The method according to claim 14, further comprising the following step of writing back the information by applying a negative write-voltage with an absolute value greater than the second voltage limit (Vth,2), if the first resistive switching storage member is the one resistive storage member being in the high resistive state before the read-out.
PCT/EP2009/006015 2009-05-29 2009-08-19 Resistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method WO2010136056A1 (en)

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PCT/DE2010/000514 WO2010136007A2 (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operation
EP10724255.4A EP2436011B1 (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operation
CN201080023633.4A CN102449702B (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operation
EP17001319.7A EP3273444A1 (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operating
US13/261,044 US8587988B2 (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operation
KR1020117026795A KR101725361B1 (en) 2009-05-29 2010-05-08 Memory element, stacking, memory matrix and method for operation
JP2012512199A JP5551769B2 (en) 2009-05-29 2010-05-08 Memory device, stacked body, memory matrix, and operation method thereof
US13/943,141 US20130301342A1 (en) 2009-05-29 2013-07-16 Memory element, stacking, memory matrix and method for operation

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