WO2011014174A1

WO2011014174A1 - Time keeping and time stamping device and method therefor

Info

Publication number: WO2011014174A1
Application number: PCT/US2009/052264
Authority: WO
Inventors: David B. Kramer; James E. Innis; Harold M. Martin
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2009-07-30
Filing date: 2009-07-30
Publication date: 2011-02-03

Abstract

A time keeping module (841) maintains a first time reference at a storage location (320). Another time keeping module (842) maintains a second time reference at another storage location (320). A time stamping module (851) is coupled to each time keeping module. The time stamping module (851) provides a time stamp in response to an event based on the first time reference during a first mode of operation (920) and provides a time stamp based on the second time reference during a second mode of operation (930).

Description

TIME KEEPING AND TIME STAMPING DEVICE AND METHOD THEREFOR

FIELD OF THE DISCLOSURE

The present disclosure is related generally to data processing devices, and more particularly to data processing devices that maintain time information. DESCRIPTION OF THE RELATED ART

Information processed by data processing devices can be associated with time information (a time stamp) that identifies when information is created, transmitted, or received, or to record a time associated with another event. A timer module includes a time base that maintains the time information. It is sometimes useful to synchronize time information maintained at one timer module with time information maintained at another timer module, such as to support deterministic operation of real-time processes distributed across two or more data processing devices. A large-scale integrated circuit, such as a multiple-core microprocessor integrated circuit, may include multiple timer modules. For example, each processor core of a multiple-core microprocessor may include one or more network interface devices. Each network interface device can include a timer module to associate time information with information exchanged by the network interface. Timer modules may be logically partitioned into one or more time domains. Timer modules included in a common time domain utilize a mechanism to synchronize time information maintained at their respective time bases so that each timer module has a consistent view of the current time. Maintenance and synchronization of time information at multiple timer modules can be provided using software techniques, however hardware-enhanced techniques can provide greater timing precision than software techniques. For example, the Precision Time Protocol (PTP), defined by the Institute of Electrical and Electronic Engineering (IEEE) 1588 technical standard, is a time- transfer protocol that can be implemented, in part, with hardware. The 1588 technical standard can be used to support synchronization of time information at data processing devices that are interconnected by a packet-based network (e.g. Ethernet).

Time information maintained at timer modules that are part of a common time domain can be synchronized using a hand-shaking technique whereby a sequence of data messages are exchanged between the corresponding timer modules in accordance with a suitable protocol.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. FIG. 1 is a block diagram illustrating an information handling system having timer modules in accordance with a specific embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a daisy chain configuration of timer modules in accordance with a specific embodiment of the present disclosure.

FIG. 3 is a block diagram illustrating a time keeping module (TKM) in accordance with a specific embodiment of the present disclosure. FIG. 4 is a block diagram illustrating a time stamping module (TSM) in accordance with a specific embodiment of the present disclosure.

FIG. 5 is a block diagram illustrating a daisy chain configuration of timer modules in accordance with a specific embodiment of the present disclosure.

FIG. 6 is a block diagram illustrating another view of the daisy chain configuration of timer modules of FIG. 5 in accordance with a specific embodiment of the present disclosure.

FIG. 7 is a block diagram illustrating an integrated circuit having multiple processor cores in accordance with a specific embodiment of the present disclosure.

FIG. 8 is a block diagram illustrating a mesh configuration of timer modules in accordance with a specific embodiment of the present disclosure. FIG. 9 is a flow diagram illustrating a method in accordance with a specific embodiment of the present disclosure.

DETAILED DESCRIPTION

A specific embodiment of a device, such as an integrated circuit, is disclosed having two or more time keeping modules, each time keeping module operable to maintain an associated time reference. The integrated circuit can be configured to time-stamp information based on the time reference associated with one time keeping module when operating in one mode, and to time-stamp information based on another time reference associated with another time keeping module when operating in another mode. Various aspects of the present disclosure will be better understood with reference to FIGs. 1-9.

FIG. 1 is a block diagram illustrating an information handling device 100 having timer modules in accordance with a specific embodiment. For the purpose of illustration, information handling device 100 is described in an example context including networks 70 and 71. The techniques described herein can be applied in other information handling device contexts that utilize timer modules without departing from the scope of the present disclosure.

Information handling device 100 includes an integrated circuit 10, a remote link partner 60, a remote link partner 61, and a remote link partner 62. Integrated circuit 10 includes timer modules 20, including timer modules 21-26, and a global configuration module (GCM) 30. Timer module (TM) 21 includes a time keeping module (TKM) 41 and a time stamping module (TSM) 51. TM 22 includes a TKM (not shown) and a TSM 52. TM 23 includes a TKM (not shown) and a TSM 53. TM 24 includes a TKM 44 and a TSM 54. TM 25 includes a TKM 45 and a TSM 55. TM 26 includes a TKM (not shown) and a TSM 56. Remote link partner 60 includes TM 27, remote link partner 61 includes TM 28, and remote link partner 62 includes TM 29. TM 27 includes TKM 47 and TSM 57, TM 28 includes TKM 48 and TSM 58, and TM 29 includes TKM 49 and TSM 59. TM 21, TM 22, TM23, and remote link partner 60 are included at a time domain 80. TM 24 and remote link partner 61 are included at a time domain 81. TM 25, TM 26, and remote link partner 62 are included at a time domain 82.

Each TM of TMs 21-26 is connected to global configuration module 30. Each TM of TMs 21-24 has a network interface connected to a network 70. Remote link partner 60 and remote link partner 61 each include a network interface connected to network 70. Each TM of TM 25-26 has a network interface connected to network 71. Remote link partner 62 includes a network interface connected to network 71. TMs 21 -26 are connected in a daisy chain wherein TM 21 has an output connected to an input at TM 22, TM 22 has an output connected to an input at TM 23, TM 23 has an output connected to an input at TM 24, TM 24 has an output connected to an input at TM 25, TM 25 has an output connected to an input at TM 26, and TM 26 has an output connected to an input at TM 21. A TSM, such as any of TSMs 51-56, is configured to associate a time stamp with corresponding information. A time stamp includes a value representing a time at which the time stamp was associated with the information, and is based on a time reference maintained at a time base such as TKM 41. For example, a TSM, such as TSM 51 can associate a time stamp with a packet of information that is exchanged by data processing devices via a packet network, for example, by transmitting the time stamp with the packet of information. Each TSM can be associated with a corresponding TKM that provides the time reference to the TSM. Furthermore, a synchronization procedure can be performed whereby the time reference maintained at one TKM can be synchronized with a time reference maintained at one or more additional TKMs included in a common time domain, wherein each of the associated TKMs maintains a substantially similar time reference. Over time, the time information maintained at a timer module may drift relative to time information maintained at another timer module included at a common time domain, so the synchronization process is typically repeated periodically.

A TKM, such as TKM 41, is configured to maintain a time reference. A TKM can be conceptualized as a clock that can be initially set to a particular time and that subsequently keeps track of time. A TKM can be implemented as a counter, and GCM 30 can initialize the counter with a time reference. Thereafter, the TKM advances the time reference based on a clock signal that increments the included counter. A TSM, such as TSM 51, can be configured to receive a time reference from an associated TKM, such as TKM 41, and provide a time stamp to selected information based on the time reference.

Two or more TMs can be organized in a daisy chain configuration. Three or more TMs can be organized in a mesh configuration, whereby each TM can communicate with any other TM without the restrictions imposed by the explicit connectivity of the daisy chain configuration. So organized, GCM 30 is operable to configure each TM whereby each TSM is associated with a corresponding TKM. For example, as illustrated at FIG. 1, each TSM of

TSM 51-53 is configured by GCM 30 to be associated with TKM 41. Thus, time stamps provided by TSM 51, TSM 52, and TSM 53 are based on a time reference maintained at TKM 41. TSM 54 is associated with TKM 44. TSM 55 and TSM 56 are each associated with TKM 46. The time keeping modules TKM 41, TKM 44, and TKM 46 are associated with disparate time domains. Thus, only three TKMs of integrated circuit 10 are required to actively maintain the time references associated with each of the six TSMs. The daisy chain configuration of the timer modules illustrated at FIG. 1 enables GCM 30 to associate a TSM of one timer module with a TKM of a different timer module. As described herein, TSMs that receive a time reference from the same TKM need to be interconnected immediately adjacent to one another and to the TKM within the daisy chain; though it will be appreciated in other embodiments, such as a mesh configuration, this limitation may not be necessary. A timer module that includes a TKM that is actively maintaining a time reference is a supervisor timer module of integrated circuit 10, and a timer module that is configured to receive a time reference from a supervisor timer module is a subordinate timer module of the integrated circuit. As illustrated, TM 21, TM 24, and TM 25 are supervisor timer modules, and TM 22, TM 23, and TM 26 are subordinate timer modules. A TKM of a supervisor timer module is initialized, e.g. an initial time reference is stored at a counter included at the TKM, and the TKM is configured to increment the counter to represent the advancing of time.

GCM 30 is operable to configure each TM of TMs 21-26 as a supervisor timer module or a subordinate timer module, to associate each subordinate timer module with a corresponding supervisor timer module, and to initialize the TKM at each supervisor timer module with a time reference. GCM 30 is further operable to access a TKM to retrieve a time reference maintained therein. GCM 30 is also operable to administer a synchronization procedure whereby the time references at two or more TKMs (at supervisor timer modules) are synchronized.

Remote link partner 60 is configured to exchange information with integrated circuit 10 via network 70. Remote link partner 60 is included at time domain 80, as is each TM of TMs 21-23. Accordingly, a time reference maintained at TKM 41 can be synchronized with TKM 47 included at TM 27 of remote link partner 60. Thus, TSM 51, TSM 52, and TSM 53 can provide time stamps representative of a time reference maintained at TKM 41, while TSM 57 at remote link partner 60 receives a substantially similar time reference from TKM 47 included at TM 27 of remote link partner 60. TMs 21-23 are included in time domain 80 because each of TSMs 51-53 is configured to provide time stamps based on the same time reference, maintained at TKM 41. TM 27 of remote link partner 60 is included in time domain 80 because it provides time stamps based on TKM 47 that is synchronized with TKM 41. In a similar manner, remote link partner 61 and TM 24 are included at time domain 81 and therefore TKM 44 can be synchronized with TKM 48 included at TM 28 of remote link partner 61. One TKM, of all TKMs included in a time domain, can maintain a time reference from which the other TKMs are synchronized. TM 25, TM 26, and remote link partner 62 are included at time domain 82. Remote link partner 62 may be a data processing device included on the same printed circuit board as integrated circuit 10. TSM 55 and TSM 56 each receive a time reference from TKM 45, and TKM 45 can be synchronized with TKM 49 included at TM 29 of remote link partner 62. Link partners include devices that are configured to exchange information via a network (a link). While FIG. 1 illustrates timer modules associated with a network for providing a time stamp to information exchanged via the network, a timer module can also be associated with any device wherein it is desired to associate a time stamp with information. For example, a timer module can be configured to associate a time stamp with a file stored at a memory device (not shown), a data value stored at a register (not shown), or the like. Furthermore, by synchronizing time references maintained at two or more time keeping modules, time stamps representative of a single time domain can be associated with information at two or more timer modules in response to separate events.

FIG. 2 is a block diagram illustrating a daisy chain configuration 200 of timer modules in accordance with a specific embodiment. Daisy chain configuration 200 includes a timer module 221, a timer module 222, and a timer module 223. TM 221 includes a TKM 241, a local control module (LCM) 261, a latch 271, a multiplexor 281, and an interface module (IM) 291. IM 291 includes a TSM 251. TM 222 includes a TKM 242, a LCM 262, a latch 272, a multiplexor 282, and an IM 292. IM 292 includes a TSM 252. TM 223 includes a TKM 243, a LCM 263, a latch 273, a multiplexor 283, and an IM 292. IM 293 includes a TSM 253. FIG. 2 also includes GCM 230, which configures each TM of TMs 221 -223.

LCM 261 has an input connected to GCM 230, an output to provide a signal labeled "TA" to TKM 241, an output to provide a signal labeled "SUPERVISOR" to a select input at multiplexor 281, and an output to provide a signal labeled "SA" to TSM 251. TKM 241 has a bidirectional terminal labeled "CT" connected to GCM 230, and an output labeled "BTOUT" connected to a data input of multiplexor 281. Latch 271 has a data input connected to an output at TM 221 labeled "IN", and a data output connected to another data input of multiplexor 281.

Multiplexor 281 has an output connected to an input terminal at TSM 251 labeled "BTIN" and to an output terminal at TM 221 labeled "OUT". The connectivity of components included at TM 222 and TM 223 is the same as that just described with regard to TM 221. Terminal OUT at TM 221 is connected to terminal IN at TM 222, terminal OUT at TM 222 is connected to terminal IN at TM 223, and terminal OUT at TM 223 is connected to terminal IN at TM 221.

GCM 230 is configured to designate each TM of TMs 221- 223 as a master timer module or subordinate timer module, and to provide a time reference to each TKM of TKMs 241-243 that are associated with a supervisor timer module. The time reference is representative of a current time associated with a time domain to which the TKM belongs. GCM 230 provides the time reference to the TKM(s) associated with supervisor timer modules via terminal CT (current time). GCM 230 also provides the supervisor/subordinate information to each LCM of LCMs 261-263. GCM 230 is further configured to read the time reference maintained at a TKM associated with a supervisor timer module. The TKM included at a TM designated as a subordinate timer module is disabled during operation of the associated TM.

LCM 261 is configured to provide signal SUPERVISOR to multiplexor 281, to provide signal TA (timer adjustment) to TKM241, and to provide signal SA (stamper adjustment) to TSM 251. IfTM 221 is configured as a supervisor timer module, LCM 261 asserts signal SUPERVISOR, which configures multiplexor 281 to select a sixty- four bit biased time reference provided from output BTOUT (biased time output) of TKM 241. IfTM 221 is configured as a subordinate timer module, LCM 261 negates signal SUPERVISOR, which configures multiplexor 281 to select a sixty-four bit biased time reference provided at the output of latch 271, the biased time reference is this case being provided by another TM that is designated as a supervisor timer module. Multiplexor 281 provides the selected biased time reference to TSM 251. Signal TA specifies an adjustment amount that is added to the time reference maintained at TKM 241 to generate a biased time reference provided at output BTOUT of TKM 241. Signal SA specifies how many clock cycles to further delay receipt of the biased time reference received at input BTIN of TSM 251. The adjustment amount (TA and SA) that LCM 261 provides to TKM 241 and to TSM 251 is based on the number TMs within daisy chain configuration 200, and the positions of TMs within daisy chain configuration 200 relative to a designated supervisor timer module, and is described with reference to FIGs. 3-6. The operation of TM 222 and TM 223 is similar to the preceding description of TM 221. Additional TMs may be included at daisy chain configuration 200. At least one TM included at daisy chain 200 is designated as a supervisor timer module by GCM 230. TMs that are designated as subordinate timer modules and which are included at a common time domain, are arranged to be immediately adjacent to each other within daisy chain configuration 200, and downstream from their associated supervisor timer module. For example, if TM 221 is designated as a supervisor timer module, TM 222, or TM 223 can be designated as subordinate timer modules associated with the same time domain as TM 221. Accordingly, TSMs 251-253 can each provide a time stamp based on the time reference maintained at TKM 241.

GCM 230 can modify the designation of which TMs are supervisor timer modules and which are subordinate timer modules, and can synchronize the time reference maintained at the TKM of a supervisor timer module with the time reference maintained at the TKM associated with another supervisor timer module.

FIG. 3 is a block diagram illustrating a TKM 300 in accordance with a specific embodiment of the present disclosure. TKM 300 is representative of a specific embodiment of the TKMs of FIGs. 1-2, such as TKM 41 and TKM 241. TKM 300 includes a sealer 310, a counter 320, and an adder 330. Sealer 310 has an input to receive a periodic signal, labeled "CLOCK," and an output to provide a periodic signal, labeled "ADVANCE CLOCK," to counter 320. Counter 320 has a bidirectional interface terminal labeled R/W connected to a node labeled "CT," and an output connected to an input at adder 330, which is also referred to as an adjustment module. Adder 330 has another input connected to receive signal TA and an output to provide a biased time signal connected to a node labeled "BTOUT."

Counter 320 is a sixty-four bit binary counter that is configured to receive and maintain a time reference. Counter 320 can be initialized by a GCM, such as GCM 30 of FIG. 1, with a sixty- four bit binary value representative of a time reference associated with a time domain. Counter 320 can also be read by the GCM to determine the time reference currently maintained at counter 320. Once counter 320 has been initialized, the time reference stored therein is incremented by signal ADVANCE CLOCK. The period of signal ADVANCE CLOCK represents a minimum interval of time maintained at counter 320, and thus a minimum resolution of a time stamp value that can be associated with information by a TSM, such as TSM 51. Signal ADVANCE CLOCK is provided by sealer 310. Sealer 310 is configured to divide the frequency of signal CLOCK by a desired amount. The scaling value provide by sealer 310 can be altered and may include an integer or non-integer value, including a value of one. In another embodiment, sealer 310 can be omitted and counter 320 can be incremented directly by signal CLOCK. Signal CLOCK represents a clock available at integrated circuit 10 of FIG. 1. Adder 330 is configured to adjust the time reference provided by counter 320 by an adjustment amount determined by a LCM, such as LCM 261 of FIG. 2. The LCM determines the adjustment amount based on the number of subordinate timer modules associated with TKM 300 and the configuration in which the subordinate timer modules are connected as defined by the GCM. For example, if more than one TM is connected in a daisy chain configuration, such as illustrated at FIG. 2, the adjustment amount is based upon to the number of subordinate timer modules associated with TKM 300. If there are no subordinate timer modules associated with TKM 300, no adjustment is provided by adder 330. Thus, TKM 300 is configured to maintain a time reference representing a current time at counter 320, and provides a biased time to one or more TSMs associated with TKM 300. In the absence of a subordinate timer module associated with TKM 300, the adjustment amount added by adjustment module 330 is equal to zero.

In an embodiment, the reference time initialized and maintained at counter 320 may be compensated to include an epoch time offset. An epoch time offset can provide a translation between two time references having different initial points of reference (epoch times). For example, a time reference used by the UNIX operating system has an epoch time (corresponding to when the time reference has a value of zero) corresponding to midnight on January 1st, 1970. Another time domain may operate pursuant to another epoch. Therefore, translation between time references having different epochs can be accomplished by adding or subtracting a suitable epoch time offset from each time references based on the difference between the epochs associated with each time domain. In another embodiment, the time reference maintained at counter 320 can be adjusted local to TKM 300 to compensate for a particular epoch time offset using one or more adder or subtracter modules (not shown at FIG. 3).

FIG. 4 is a block diagram illustrating a TSM 400 in accordance with a specific embodiment of the present disclosure. TSM 400 is representative of a specific embodiment the TSMs of FIGs. 1-2, such as TSM 51. TSM 400 includes a delay module 410 and stamp units 420-422. Delay module 410 includes latches 411-414, and multiplexor 415. Latch 411 has a data input connected to a node labeled "BTIN" and to a first input of multiplexor 415, a clock input to receive signal ADVANCE CLOCK, and a data output connected to a data input of latch 412 and to a second input at of multiplexor 415. Latch 412 has a clock input to receive signal ADVANCE CLOCK, and a data output connected to a data input of latch 413 and to a third input of multiplexor 414. Latch 413 has a clock input to receive signal ADVANCE CLOCK, and a data output connected to a data input of latch 414 and to a fourth input at multiplexor 415. Latch 414 has a clock input to receive signal ADVANCE CLOCK, and a data output connected to a fifth input at multiplexor 415. Multiplexor 415 further has a select input to receive signal SA and an output to provide a delayed adjusted time reference connected to stamp units 420-422. Each stamp unit of stamp units 420- 422 has an input for receiving information and an output for providing time-stamped information. Delay module 410 is configured to delay the presentation of a biased time value to stamp units 420-422.

The amount of delay provided by delay module 410 is selected by signal SA received from a LCM, such as LCM 261 of FIG. 2, and corresponds to a number of cycles of signal ADVANCE CLOCK. The LCM determines the amount of delay based on the delay associated with a number of subordinate timer modules associated with a supervisor timer module and the location of the TSM in a daisy chain or a mesh configuration relative to the supervisor timer module. Delay provided by delay module 410 compensates for delay introduced by latches, such as latches 271-273 of FIG. 2, in the data path connecting a respective TKM to a corresponding TSM, and is described later with reference to FIGs. 5 and 6. In another embodiment of the present disclosure, delay module 410 can be implemented using an adjustment module similar to adjustment module 330 of TKM 300, whereby the biased time is numerically adjusted by an amount specified by signal SA.

Each stamp unit of stamp units 420-422 is configured to associate a time stamp to information received at the stamp unit. The time stamp indicates the current time represented by a time reference maintained at an associated supervisor timer module at the time an event occurred. For example, if TSM 400 is associated with an Ethernet network interface, stamp unit 420 can be configured to combine a time stamp with each set of packetized data. TSM 300 illustrated at FIG. 4 includes three stamp units, however a greater or fewer number of stamp units can be implemented based on the number of unique information streams associated with TSM 300. It will also be appreciated that operation of the time stamp units 420-422 will typically be controlled by a system clock, which can be faster than the advance clock.

FIG. 5 is a block diagram illustrating a daisy chain configuration 500 of timer modules in accordance with a specific embodiment. Daisy chain configuration 500 includes timer modules 521-524. Timer module 521 includes latch 571, TKM 541, multiplexor 581, and TSM 551. Timer module 522 includes latch 572, TKM 542, multiplexor 582, and TSM 552. Timer module 523 includes latch 573, TKM 543, multiplexor 583, and TSM 553. Timer module 524 includes latch 574, TKM 544, multiplexor 584, and TSM 554.

Latch 571 has an output connected to a data input of multiplexor 581. TKM 541 has an input to receive a signal representing an adjustment amount, and an output connected to another data input of multiplexor 581.

Multiplexor 581 has a select input and an output connected to TSM 551 and a data input of latch 572. TSM 551 has an input to receive a signal representing an adjustment amount. Latch 572 has an output connected to a data input of multiplexor 582. TKM 542 has an input to receive a signal representing an adjustment amount, and an output connected to another data input of multiplexor 582. Multiplexor 582 has a select input and an output connected to TSM 552 and a data input of latch 573. TSM 552 has an input to receive a signal representing an adjustment amount. Latch 573 has an output connected to a data input of multiplexor 583. TKM 543 has an input to receive a signal representing an adjustment amount, and an output connected to another data input of multiplexor 583.

Multiplexor 583 has a select input and an output connected to TSM 553 and a data input of latch 574. TSM 553 has an input to receive a signal representing an adjustment amount. Latch 574 has an output connected to a data input of multiplexor 584. TKM 544 has an input to receive a signal representing an adjustment amount, and an output connected to another data input of multiplexor 584. Multiplexor 584 has a select input and an output connected to TSM 554 and a data input of latch 571. TSM 554 has an input to receive a signal representing an adjustment amount. Each latch and TSM has an input to receive signal ADVANCE CLOCK.

Timer module 521 is configured as a supervisor timer module, and timer modules 522-524 are configured as subordinate timer modules. Also illustrated at FIG. 5 are adjustment amounts and multiplexor select values determined for each timer module's respective TKM and TSM. Because there are three subordinate timer modules associated with supervisor timer module TM 521 and the TMs are organized as a daisy chain configuration, the GCM will configure the LCM associated with TM 521 to configure the adjustment module included at TKM 541

(not shown) to add a value of three to the time reference provided by TKM 541. Because TM 521 is configured as a supervisor timer module, multiplexor 581 is configured to select the biased time signal provided by TKM 541 by asserting signal SUPERVISOR provided to multiplexor 581.

TSM 551 is associated with TKM 541 at TM 521 and receives a biased time signal that has not been delayed by a latch associated with the data path formed by the daisy chain interconnection of timer modules (such as latches 571-574). Thus, the biased time reference received at TSM 551 indicates a time value that is three counts in advance of the time reference maintained at TKM 541. Therefore, the delay module included at TSM 551 (not shown) is configured to delay the arrival of the biased time signal by three cycles of signal ADVANCE CLOCK (SA=3). Thus, at the time that TSM 551 associates a time stamp with information, the value of the time stamp matches the time reference maintained at the counter of TKM 541. Because each of TMs 522-524 are configured as subordinate timer modules, TKMs 542-544 are deactivated, and multiplexors 582-584 are each configured by a corresponding LCM to propagate the biased time signal provided by TKM 541 to each successive subordinate timer module (by negating signal SUPERVISOR provided to each corresponding multiplexor select input). The biased time signal received at TM 522, labeled "SUBORDINATE1," is delayed by one cycle of signal ADANCE CLOCK by latch 572, so the delay module at TSM 552 (not shown) is configured to delay the arrival of the biased time signal by two additional cycles of signal ADVANCE CLOCK (SA=2). Thus, at the time that TSM 552 associates a time stamp with information, the value of the time stamp matches time reference maintained at the counter of TKM 541. The biased time signal received at TM 523, labeled "SUBORDINATE2," is delayed by an additional cycle of signal ADVANCE CLOCK by latch 573, so the delay module at TSM 553 (not shown) is configured to delay the biased time signal by one additional cycle of signal ADVANCE CLOCK (SA=I). The biased time signal received at TM 524, labeled

"SUBORDINATES," is delayed by an additional cycle of signal ADVANCE CLOCK by latch 574, so the delay module at TSM 554 (not shown) is configured to provide no additional delay to the biased time signal (SA=O). Thus, the value of a time stamp that is associated with information by any of TSMs 521-524 is the same as the time reference maintained at TKM 541 at the time that the time stamp is provided. FIG. 6 is a block diagram illustrating another view 600 of daisy chain configuration 500 of timer modules of FIG. 5 in accordance with a specific embodiment of the present disclosure. View 600 illustrates a data path, e.g. the pipeline between a counter at a time keeping module of a supervisor timer module and a time stamping module that provides a time stamp based on a time reference maintained at the counter, and provides a snapshot of time information associated with nodes of the data path at a particular moment in time. View 600 includes TKM 541 (included at TM 521), latches 572-574, and TSMs 551-554 (included at TMs 522-524, respectively) interconnected and previously described with reference to FIG. 5. Additionally, components included at TSM 551-554 are illustrated and correspond to components illustrated at TSM 400 of FIG. 4. For example, latches labeled "Ll" correspond to latch 411, latches labeled "L2" correspond to latch 412, latches labeled "L3" correspond to latch 413, multiplexors labeled "Ml" correspond to multiplexor 415, and stamp units labeled "Sl" correspond to stamp unit 420. In a similar manner, components included at TKM 541 are illustrated and correspond to components illustrated at TKM 300 of FIG. 3. For example, counter 620 corresponds to counter 320, and adjustment module 630 correspond to adjustment module 330. FIG. 6 also includes annotations (included within parenthesis) depicting the value of the time information at a plurality of nodes at an example moment in time. In particular, view 600 corresponds to a current time, represented by a time reference maintained at counter 620 of TKM 541, having a value of decimal 100. The time reference (current time) is adjusted by adjustment module 630 to provide a biased time equal to decimal 103. An adjustment amount of value three is selected by the LCM associated with TKM 541 based on there being three subordinate timer modules associated with TKM 541 and configured as a daisy chain. Latches 572-574 provide a data pipeline, wherein the value of the time information provided at the output of latch 572, decimal 102, represents the biased time provided by TKM 541 during the previous cycle of signal ADVANCE CLOCK. The time information provided at the output of latch 573, decimal 101, represents the biased time provided by TKM 541 two cycles previous to the current time, and time information provided at the output of latch 574, decimal 100, represents the biased time provided by TKM 541 three cycles previous to the current time.

TSM 551 is included at supervisor timer module TM 521. The LCM associated with TM 521 configures the delay module at TSM to delay the delivery of time information to an associated stamp unit by 3 cycles. Latches L1-L3 provide another data pipeline, similar to that provided by latches 572-574. Thus, the value of the time information provided at the output of latch L3 of TSM 551 is decimal 100, and a time stamp of value decimal 100 would be provided by stamp unit Sl of TSM 551 at this moment in time. Furthermore, GCM 30 will receive a value of decimal 100 in response to an inquiry, such as a register read, to determine the value of the time reference maintained at counter 620 at this particular moment in time.

Subordinate timer module TM 522 (SUBORDINATE 1) is adjacent to supervisor timer module TM 521 in daisy chain configuration 500 and receives time information from the output of latch 572. The delay module associated with TSM 552 is configured to delay the delivery of time information to an associated stamp unit by two additional cycles. Subordinate timer module TM 523 (SUBORDINATE2) is adjacent to subordinate timer module TM 522 in daisy chain configuration 500 and receives time information from the output of latch 573. The delay module associated with TSM 553 is configured to delay the delivery of time information to an associated stamp unit by one additional cycle. Subordinate timer module TM 524 (SUBORDINATES) is adjacent to subordinate timer module TM 523 in daisy chain configuration 500 and receives time information from the output of latch 573. The delay module associated with TSM 554 is configured to provide no additional delay and the time information provided by latch 574 is delivered directly to an associated stamp unit.

Thus, each TSM is configured to provide a time stamp of value decimal 100 at this moment in time (current time), which corresponds to the time reference maintained at TKM 541 of supervisor timer module TM 521 (which also has a value of decimal 100). In an embodiment, the adjustment module and delay module can be configured to compensate for additional pipeline delay that may be introduced if adjacent TMs are separated by more than one latch, e.g. in the case where TMs are physically separated by a distance that prevents the propagation of time information from one TM to the next TM in a daisy chain. FIG. 7 is a block diagram illustrating an integrated circuit 700 having multiple processor cores in accordance with a specific embodiment of the present disclosure. Integrated circuit 700 includes processor cores 711, 712, 713, and 714. Processor core 711 includes core arithmetic logic unit (ALU) 721, memory 731, TKM 741, and TSM 751. Processor core 712 includes core ALU 722, memory 733, a TKM (not shown) and TSM 752.

Processor core 713 includes core ALU 723, memory 733, a TKM (not shown) and TSM 753. Processor core 714 includes core ALU 724, memory 734, a TKM (not shown) and TSM 754.

Each respective TSM of TSMs 751-754 can be configured to provide time stamps to respective information at each processor core, wherein the time information represented by the time stamp is provided by a time reference maintained at TKM 741. In other embodiments, integrated circuit 700 can include more than one time domain, multiple TMs and associated TKMs for maintaining corresponding time references, and additional TSMs. A GCM (not shown) can configure the plurality of TMs as supervisor timer modules and subordinate timer modules, and the configuration can be changed as desired. FIG. 8 is a block diagram illustrating a mesh configuration 800 of timer modules in accordance with a specific embodiment of the present disclosure. Mesh configuration 800 includes TM 821, TM 822, TM 823, TM 824, mesh multiplexor 811, mesh multiplexor 812, mesh multiplexor 813, and mesh multiplexor 814. TM 821 includes latch 871, TKM 841, multiplexor 881, and TSM 851. TM 822 includes latch 872, TKM 842, multiplexor 882, and TSM 852. TM 823 includes latch 873, TKM 843, multiplexor 883, and TSM 853. TM 824 includes latch 874, TKM 844, multiplexor 884, and TSM 854.

TMs 821-824 are interconnected in a mesh configuration by multiplexors 811-814 so that a GCM (not shown) can designate any one TM, or more than one TM, as a supervisor timer module or a subordinate timer module. A mesh configuration, such as mesh configuration 800, removes the restriction present in a daisy chain configuration wherein subordinate timer modules must be located physically adjacent to each other and to an associated supervisor timer module. A greater or less number of TMs can be organized in a mesh configuration using a corresponding number of mesh multiplexors to interconnect associated TMs.

FIG. 9 is a flow diagram illustrating a method 900 in accordance with a specific embodiment of the present disclosure. Method 900 is described in the context of the mesh configuration of timer modules at FIG. 8, but is equally applicable to another configuration of timer modules, such as the daisy chain configuration of timer modules at FIG. 2. The flow begins at decision block 910 where a mode of operation is determined. If the set of timer modules is configured to operate in a first mode, the flow proceeds to block 920 where TSM 851 and TSM 852 are both configured to determine a time stamp based on a time reference maintained at TKM 841. If the set of timer modules is configured to operate in a second mode, the flow proceeds to block 930 where TSM 851 and TSM 852 are both configured to determine a time stamp based on a time reference maintained at TKM 842. If the set of timer modules is configured to operate in a third mode, the flow proceeds to block 940 where TSM 851 is configured to determine a time stamp based on a time reference maintained at TKM 841, and TSM 852 is configured to determine a time stamp based on a time reference maintained at TKM 842.

The illustrated modes of operation are only a few examples of the many configurations that can be established. For example, TSMs 851-854 can be configured to determine respective time stamps based on a time reference maintained at TKM 842. Thus, four TSMs can be associated with the same time domain, while maintaining time synchronization at only one TKM instead of at four TKMs. Other embodiments, uses, and advantages of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The specification and drawings should be considered exemplary only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof. Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities may be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed.

Also, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

For example, wherein time references illustrated herein include sixty-four bits of information, a time reference can include a greater or a fewer number of bits of information, e.g. 128 bits, thirty-two bits, or another number of bit. Furthermore a biased time reference, or a delayed time reference can be represented by a fewer number of bits of information than the number of bits of information maintained at a time keeping module. The timer modules illustrated at FIG. 2 require that a time stamping module included at a supervisor timer module provide a time stamp based on the time reference maintained at the time keeping module included at the same supervisor timer module. In another embodiment, a timer module can be configured as a supervisor timer module and the time stamping module included therein can be configured to provide a time stamp based on a time reference maintained at a time keeping module included at another supervisor timer module.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.

Claims

WHAT IS CLAIMED IS:

1. A device comprising:

a first time keeping module (841) operable to maintain a first time reference at a first storage location (320);

a second time keeping module (842) operable to maintain a second time reference at a second storage location (320); and

a first time stamping module (851) coupled to the first time keeping module (841) and to the second time keeping module (842) operable to provide a first time stamp to be transmitted with a first packet of information, during a first mode of operation (920) the first time stamp is based on the first time reference and, alternatively, during a second mode of operation (930) the first time stamp is based on the second time reference.

2. The device of claim 1 further comprising:

a second time stamping module (852) coupled to the first time keeping module (841) and to the second time keeping module (842) operable to provide a second time stamp to be provided with a second packet of information, during the first mode of operation (920) the second time stamp is based on the first time reference and, alternatively, during the second mode of operation (930) the second time stamp is based on the second time reference.

3. The device of claim 2 wherein during a third mode of operation (940) the first time stamping module (851) is operable to provide the first time stamp based on the first time reference, and the second time stamping module (852) is operable to provide the second time stamp based on the second time reference.

4. The device of claim 3 wherein the first time keeping module (300) further comprises an adjustment module (330) comprising:

a first input to receive the first time reference;

a second input to receive an adjustment amount having a first value in response to the first mode of operation and, alternatively, having a second value in response to the third mode of operation; and

an output to provide an adjusted time reference based on the first time reference and the adjustment amount, and wherein the first time stamp provided by the first time stamping module (851) based on the first time reference further comprises the first time stamping module (851) basing the first time stamp on the adjusted time reference.

5. The device of claim 4 wherein the first time stamp module (400) further comprises a delay module (410) comprising:

a first input to receive the adjusted time reference;

a second input to receive a delay amount having a first delay value in response to the first mode of operation and having a second delay value in response to the third mode of operation; and

an output to provide a delayed time reference representing the adjusted time reference delayed by the delay amount, and wherein the first time stamp provided by the first time stamping module (851) based on the first time reference further comprises the first time stamping module (851) basing the first time stamp on the delayed time reference.

6. The device of claim 1 wherein the first time stamping module (751) is included at a first processor core (711) of a multiple-core processor (700) and the second time stamping module (752) is included at a second processor core (712) of the multiple-core processor (700).

7. A method comprising:

initializing a time keeping module of a first timer module (21) of a plurality of timer modules at an integrated circuit (10), each timer module (21) including a time keeping module

(41) and a time stamping module (51); and

determining a time stamp provided by a time stamping module of a second timer module (22) of the plurality of timer modules based on a time reference maintained at the time keeping module of the first timer module (21).

8. The method of claim 7 further comprising:

determining a time stamp provided by a time stamping module of a third timer module (23) of the plurality of timer modules based on the time reference maintained at the time keeping module of the first timer module (21).

9. The method of claim 7 wherein determining the time stamp provided by the time stamping module of the second timer module (22) based on the time reference comprises determining the time stamp based on an adjusted time reference, the adjusted time reference determined by adjusting (330) the time reference by a first amount, the first amount based on a number of time stamp modules providing time stamps based upon the time reference.

10. The method of claim 9 further comprising:

delaying (410) the adjusted time reference by a second amount to provide a delayed adjusted time reference, and wherein determining the time stamp provided by the time stamping module of the second timer module (22) based on the time reference comprises determining the time stamp based on the delayed adjusted time reference.

11. The method of claim 7 further comprising:

initializing a time keeping module of a third timer module (25) of the plurality of timer

modules; and

determining a time stamp provided by a time stamping module of a fourth timer module (26) of the plurality of timer modules with a time reference maintained at the time keeping module of the third timer module (25).

12. The method of claim 7 further comprising:

determining a time stamp provided by a time stamping module of the first timer module (21) with the time reference maintained at the time keeping module of the first timer module (21).

14. The method of claim 7 wherein the time reference maintained at the time keeping module of the first timer module (21) is determined based on a time reference maintained at a time keeping module of a third timer module (27)

15. The method of claim 7 wherein determining the time stamp provided by the time stamping module (400) comprises associating the time stamp with a packet of information.

16. The method of claim 15 wherein the plurality of timer modules are included at two or more processor cores of a multiple-core processor (700).