WO2011014434A2 - Bond and probe pad distribution and package architecture - Google Patents

Bond and probe pad distribution and package architecture Download PDF

Info

Publication number
WO2011014434A2
WO2011014434A2 PCT/US2010/043137 US2010043137W WO2011014434A2 WO 2011014434 A2 WO2011014434 A2 WO 2011014434A2 US 2010043137 W US2010043137 W US 2010043137W WO 2011014434 A2 WO2011014434 A2 WO 2011014434A2
Authority
WO
WIPO (PCT)
Prior art keywords
probe
pads
integrated circuit
disposed
probe pads
Prior art date
Application number
PCT/US2010/043137
Other languages
French (fr)
Other versions
WO2011014434A3 (en
Inventor
William Y. Hata
Original Assignee
Altera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/534,002 external-priority patent/US9267985B2/en
Priority claimed from US12/533,997 external-priority patent/US8148813B2/en
Application filed by Altera Corporation filed Critical Altera Corporation
Priority to CN201080045527.6A priority Critical patent/CN102576685B/en
Publication of WO2011014434A2 publication Critical patent/WO2011014434A2/en
Publication of WO2011014434A3 publication Critical patent/WO2011014434A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Definitions

  • some integrated circuits may be designed to function with another device, e.g., a memory chip, a co-processor, etc.
  • another device e.g., a memory chip, a co-processor, etc.
  • Different combinations of the two devices are possible, e.g., different amounts of memory, operating frequencies, or even the ability to function without the secondary device.
  • Packages for the different combinations tend to add to the overall cost and as such, there are continual efforts to reduce the costs for the packaging.
  • One exemplary application is with regard to programmable logic devices and the configuration stored in an external device, such as one or more non-volatile memory chips.
  • the different package formats for the devices, or combination of devices add to the inventory management overhead, in addition to requiring customized bills of materials for the owner of the programmable logic device.
  • different testing requirements are incurred further adding to costs. It is desirable to reduce the inventory overhead yet maintain the flexibility offered through alternative package formats.
  • the embodiments described herein provide an integrated circuit having a surface with a probe pad distribution pattern that enables efficient testing of the integrated circuit. It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method on a computer readable medium. Several inventive embodiments of the present invention are described below.
  • an integrated circuit includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC. Each of the plurality of probe pads is in electrical communication with corresponding bond pads.
  • the plurality of probe pads are linearly configured across the surface of the die. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface.
  • the die may be tested through automated test equipment where the tester includes a probe card that has probe pins which align with the probe pads diagonally disposed along the surface of the die or dies being tested.
  • a method of testing a semiconductor device begins with orienting a plurality of devices under test so that probe pads disposed along diagonally opposing vertices of successive devices under test are substantially linear.
  • the method includes contacting the probe pads with probe pins of a probe card and transmitting electrical signals to the probe pads through the probe pins.
  • the probe card is a cantilevered probe card.
  • a packaging architecture for an integrated circuit includes a printed circuit board and a package substrate disposed on the printed circuit board.
  • a first integrated circuit is disposed on a first surface of the package substrate.
  • the package substrate is capable of supporting a second integrated circuit.
  • the second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit. Consequently, the second integrated circuit communicates with the first integrated circuit, solely through the printed circuit board.
  • the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration utilized by the programmable logic device.
  • the second integrated circuit is disposed above the first integrated circuit.
  • a method of packaging an integrated circuit begins with coupling a first integrated circuit to a package substrate and then coupling a second integrated circuit to the package substrate.
  • the second integrated circuit is disposed over the first integrated circuit in one embodiment.
  • the method includes coupling the package substrate to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board prior to being delivered to the first integrated circuit.
  • the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration utilized by the programmable logic device.
  • Figure 1 is a simplified schematic diagram illustrating a surface of a die having the diagonally distributed probe pads in accordance with one embodiment of the invention.
  • Figure 2A is a simplified schematic of the interconnection between the bond pads and the probe pads in accordance with one embodiment of the invention.
  • Figures 2B and 2C illustrate cross sectional side views of possible
  • Figure 3 is a simplified schematic diagram illustrating a two die testing pattern without the diagonal probe pad distribution.
  • Figure 4A is a simplified schematic diagram illustrating a multiple die testing pattern with the diagonal probe pad distribution in accordance with one embodiment of the invention.
  • Figure 4B is a side view of the multi die testing apparatus of Figure 4A
  • Figure 5 is simplified schematic diagram illustrating an automated test system for testing multiple dies contemporaneously in accordance with one embodiment of the invention.
  • Figure 6 is a flowchart diagram illustrating method operations for testing a semiconductor device in accordance with one embodiment of the invention.
  • FIGS 7A through 7C illustrate schematics showing different views for the integrated circuit and package substrate in accordance with one embodiment of the invention.
  • Figure 8 is a simplified schematic diagram illustrating a standalone layout where landing pads on the package substrate designated for a second integrated circuit are exclusively in communication with a printed circuit board in accordance with one embodiment of the invention.
  • Figures 9A and 9B are simplified schematic diagrams illustrating the stacked layout of the integrated circuit and the corresponding configuration device in accordance with one embodiment of the invention.
  • Figure 10 is a simplified schematic diagram illustrating the stacked layout of
  • FIGS. 9A and 9B coupled to a printed circuit board in accordance with one embodiment of the invention.
  • Figure 11 is a flow chart diagram illustrating the method operations for packaging and integrated circuit in accordance with one embodiment of the invention.
  • the embodiments described herein provide a diagonal redistribution pattern for probe pads in a die to be packaged through wire bonding.
  • the diagonal redistribution pattern enables low-cost schemes for multi-die probing to be performed.
  • the redistributed probe pads are arranged in a diagonal across a surface of the die. Under this arrangement, multiple die can be probed with a linear arrangement of probe pins, by aligning the wafer diagonally.
  • the embodiments enable the use of linear probe cards, which are less expensive and produce more reliable measurements.
  • cantilever probe technology may be utilized for the probe cards performing the testing.
  • cantilever probe technology has a fixed dimension in one planar direction, but is capable of moving in an orthogonal direction to the plane of the fixed dimension.
  • Figure 1 is a simplified schematic diagram illustrating a surface of a die having the diagonally distributed probe pads in accordance with one embodiment of the invention.
  • Die 100 may be any semiconductor die prepared through known semiconductor
  • the integrated circuit may be a microprocessor, a programmable logic device (PLD), or other integrated circuits
  • the surface of die 100 includes a plurality of bond pads 102 disposed along a perimeter of the four sides of die 100. Bond pads 102 are subsequently bonded to a package substrate through wire bonds. Prior to the wire bonding process, die 100 may undergo testing to verify the integrity of the pathways and logic within the integrated circuit. During the testing, the probe pads are contacted through probe pins of a probe card housed within automated testing equipment to stimulate signals into the integrated circuit. The responses to these signals are then captured in order to ensure integrity of die 100.
  • the probe pad distribution illustrated in Figure 1 enables the efficient testing of die 100. As will be discussed further below multiple dies may be aligned so as to utilize cantilevered probe cards in order to complete the testing. Bond pads 102 are in electrical communication with probe pads 104 through traces 106.
  • Figure 2A is a simplified schematic of the interconnection between the bond pads and the probe pads in accordance with one embodiment of the invention.
  • Die 100 includes bond pad 102 and probe pad 104 disposed on a surface of die 100.
  • Probe pad 104 is in electrical communication with bond pad 102 through trace 106.
  • trace 106 may be disposed along a surface of die 100.
  • an insulative or passivation material may be disposed over the surface of die 100 between probe pad 104 and bond pad 102.
  • Figures 2B and 2C illustrate cross sectional side views of possible interconnections for the bond pads and probe pads of Figures 1 and 2A in accordance with one embodiment of the invention.
  • Figure 2B illustrates yet another embodiment where trace 106 is disposed on a surface of die 100 to connect probe pad 104 and bond pad 102.
  • Passivation layer 107 is disposed over the die surface and the surface of trace 106, leaving access to probe pad 104 and bond pad 102.
  • Figures 2A-C are exemplary and not meant to be limiting as alternative interconnections techniques are possible.
  • multiple techniques may be included in a single die, i.e., some connections may be defined below the surface of the die and others may be defined on the surface.
  • Figure 2C illustrates trace 106 disposed below the surface of die 100 for connecting bond pad 102 and probe pad 104.
  • trace 106 connects bond pad 102 and probe pad 104 through the metallization layers within die 100.
  • Passivation layer 107 is disposed over the top surface of die 100 and openings are defined in passivation layer 107 the enable access to a surface of each of bond pad 102 and probe pad 104.
  • shape of the bond pads and the probe pads while depicted as either square or rectangular, is not meant to be limiting. That is, any suitable geometric shape may be used for the bond pads or probe pads.
  • Figure 3 is a simplified schematic diagram illustrating a two die testing pattern without the diagonal probe pad distribution.
  • Probe card 110 is disposed above dies IOOA through lOOC.
  • Probe pins 112 contact pads 102 in order to perform the testing.
  • die IOOB disposed between die IOOA and IOOC is skipped. That is, the probe card is unable to access each bond pad for adjacent dies when the distribution pattern is along the periphery of the four sides.
  • Figure 4A is a simplified schematic diagram illustrating a multiple die testing pattern with the diagonal probe pad distribution in accordance with one embodiment of the invention.
  • Dies IOOA and IOOB are aligned so that the diagonally distributed probe pads 104 are linearly arranged.
  • probe pads 104 are separate from bond pads 102, yet corresponding probe pads and bond pads are in electrical communication.
  • Probe card 110 contacts the corresponding dies through probe pins 112.
  • the linear arrangement avoids the necessity for skipping dies and thus provides a more efficient testing technique where throughput is improved and relatively inexpensive probe cards may be utilized. It should be appreciated that while two dies IOOA and IOOB are illustrated, the embodiments are not limited to two dies.
  • Figure 4B illustrates a side view of the multi die testing apparatus of Figure 4A.
  • Probe card 110 contacts the die 100 through probe pins 112.
  • probe pins 112 are cantilevered probe pins. It should be appreciated that the illustration of the probe pins as being curved is for illustrative purposes and that the probe pins, such as cantilevered probe pins are typically linear, i.e., being straight, and may even have a bend defined therein. As illustrated in Figures 4A and 4B, the diagonal distribution enables a linear probe card to efficiently test the dies even with the compact probe pad distribution.
  • FIG. 5 is simplified schematic diagram illustrating an automated test system utilizing the embodiments described herein.
  • the testing system includes integrated circuit tester 200 is in communication with test head manipulator 210, which controls test head 212.
  • Probe card 110 is affixed to test head 212.
  • Wafer handler/die support 214 supports the wafers or dies to be tested.
  • a plurality of dies 100 are arranged in a linear arrangement where the probe pads disposed diagonally along a surface of each die are linearly aligned.
  • Test head 212 is lowered so that probe card 110 contacts the dies 100 to be tested through corresponding probe pins.
  • One skilled in the art will appreciate that alternative configurations depending on the manufacturer of the test system may be utilized and that the embodiments are not limited to the exemplary test system described herein.
  • FIG. 6 is a flowchart diagram illustrating method operations for testing a semiconductor device in accordance with one embodiment of the invention.
  • the method initiates with operation 300 where a plurality of devices under test are oriented so that probe pads disposed along diagonally opposing vertices of successively adjacent devices under test are substantially linear, as illustrated in Figures 4A and 4B.
  • the probe card is disposed over the diagonally aligned dies without the need for skipping any of the dies.
  • a cantilevered probe card may be employed in the testing of the semiconductor devices.
  • the method then advances to operation 302 where the probe pads of the die are contacted with the probe pins from the probe card.
  • electric signals are transmitted from the probe card to the probe pads.
  • the responses to the electric signals transmitted to the probe pads are captured or recorded in operation 306.
  • the captured data can be analyzed to verify the integrity of the semiconductor device or integrated circuit being tested.
  • FIG. 7A- 11 Further embodiments described below provide a package architecture for an integrated circuit, which may incorporate the bond and probe pads described above.
  • the embodiments described with regard to Figures 7A- 11 provide for a package layout that is compatible with external configuration devices without complicating inventory management for the package.
  • a package on package (POP) solution is utilized for the package architecture.
  • the POP solution is capable of functioning in a standalone design as explained further below.
  • the configuration device can be supplied and attached by the owner of the integrated circuit.
  • the customer or end user may supply the configuration device. Irrespective of whether the configuration device is supplied by the owner of the integrated circuit or the customer, the configuration device can be either pre-programmed or programmed at a later time.
  • Figures 7A through 7C illustrate schematics showing different views for the package layout in accordance with one embodiment of the invention.
  • Figure 7A is a simplified schematic diagram of the package layout from a top view.
  • Integrated circuit 702 is disposed over package substrate 700.
  • Package substrate 700 may include a plurality of landing pads 704 for a POP layout in accordance with one embodiment of the invention.
  • integrated circuit 702 may be coupled to package substrate 700 through a plurality of solder balls, such as, a ball and grid array configuration.
  • solder balls such as, a ball and grid array configuration.
  • alternative coupling techniques, besides the ball and grid array may be utilized as the ball and grid array is exemplary and not meant to be limiting.
  • a memory chip is disposed over the top of package configuration of Figure 7 as illustrated in Figures 9A- 10.
  • Figure 7B illustrates a side view of the integrated circuit and package substrate in accordance with one embodiment of the invention. As illustrated in Figure 7B landing pads 704 are in electrical communication with a corresponding solder ball 708 disposed on an opposing surface of package 700.
  • the embodiments described herein provide for a configuration device to be disposed over integrated circuit 702.
  • configuration device disposed over integrated circuit 702 does not include any
  • pathway 706 through package substrate 700 is a plated through hole.
  • pathway 706 through package substrate 700 utilizes the metallization layers defined within the package substrate.
  • Figure 7C is a bottom illustration of package substrate 700 in accordance with one embodiment of the invention. The bottom surface of package 700 provides a ball and grid array for communication with a printed circuit board in one embodiment.
  • FIG. 8 is a simplified schematic diagram illustrating an exemplary package layout in accordance with one embodiment of the invention.
  • package substrate 700 has integrated circuit 702 disposed thereon.
  • This layout is referred to as a standalone layout since the corresponding configuration device is not disposed over integrated circuit 702.
  • the connections for the landing pads 704 through package substrate 700 and into printed circuit board 710 may be grounded to prevent any damage.
  • the connections may be floating.
  • I/Os are all out board of the package on package (POP) design for simplified printed circuit board routing.
  • POP package on package
  • Figures 9A and 9B are simplified schematic diagrams illustrating the stacked layout of the integrated circuit and the corresponding configuration device in accordance with one embodiment of the invention.
  • a top view of the package layout is provided.
  • Configuration device 712 is disposed over package substrate 700.
  • configuration device 712 may be a memory chip that stores a configuration for integrated circuit 702.
  • integrated circuit 702 may be any integrated circuit, such as a microprocessor or a programmable logic device (PLD), and configuration device 712 may be any suitable integrated circuit.
  • Figure 9B illustrates a side view of the stacked layout.
  • Package substrate 700 includes a plurality of solder balls disposed on a bottom surface and is in communication with configuration device 712 through corresponding solder ball 714 and landing pad 704. Disposed between the bottom surface of configuration device 712 and the top surface of package substrate 700 is integrated circuit 702. As mentioned above integrated circuit 702 may be coupled to package substrate 700 through a ball and grid array as is known in the art. The electrical pathways connecting landing pad 704 and solder ball 708 proceeds through package substrate 700 without providing an electrical pathway to integrated circuit 702 through package substrate 700. That is, communication between configuration device 712 and integrated circuit 702 proceeds through a printed circuit board, or other external device, coupled to package substrate 700 through solder balls 708.
  • Figure 10 is a simplified schematic diagram illustrating the stacked layout of
  • FIGS 9A and 9B coupled to a printed circuit board in accordance with one embodiment of the invention.
  • Configuration device 712 is disposed over package substrate 700.
  • Configuration device 712 is in electrical communication with package substrate 700 through solder ball 714 and landing pad 704.
  • Printed circuit board 710 is in communication with corresponding solder balls 708 of package substrate through pads 716. It should be appreciated that the configuration device 712 will communicate with integrated circuit 702 through pathways within printed circuit board 710 or IO pins of printed circuit board 710 that are in communication with an external device.
  • configuration device 712 is a memory storing a configuration for an integrated circuit, such a PLD
  • configuration device 712 can be programmed prior to placement on package substrate 700, through direct connect pins after placement on package substrate 700, or on the printed circuit board as is conventionally done for in system programming.
  • FIG 11 is a flow chart diagram illustrating the method operations for packaging and integrated circuit in accordance with one embodiment of the invention.
  • the method initiates with operations 800 where a first integrated circuit is coupled to a package.
  • a programmable logic device may be coupled to a package substrate through conventional techniques known in the art in one embodiment of the invention.
  • the method then advances to operation 802 where a second integrated circuit is coupled to the package substrate.
  • the second integrated circuit is disposed over the first integrated circuit in accordance with one embodiment. It should be appreciated that the second integrated circuit may be alternatively disposed to a side of the first integrated circuit if the package substrate is large enough.
  • the second integrated circuit is disposed over the first integrated circuit in a package on package configuration.
  • the method then advances to operation 804 for where the package substrate is coupled to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board. That is, the second integrated circuit does not communicate with the first integrated circuit directly through the package substrate since there are no pathways defining such communication between integrated circuit 702, package substrate 700 and configuration device 712.
  • the second integrated circuit may be coupled to the printed circuit board by a through via.
  • programmable logic device and a secondary device being a configuration device for the programmable logic device.
  • a memory chip such as flash memory
  • processor for a mobile device or any other small form factor device.
  • the embodiments described herein enable the design of different amounts of memory without changing the package configuration to possibly differentiate product price points.
  • Another application for the embodiments include with the use of a central processing unit (CPU), or any other suitable processor, and static random access memory (SRAM) cache for the two devices.
  • CPU central processing unit
  • SRAM static random access memory
  • Other exemplary applications include a CPU and co-processor.
  • one of the devices does not necessarily have to be a memory chip.
  • the embodiments are applicable to a primary device that can be used both with and without a secondary device.
  • the secondary device communicates to the primary device exclusively through a printed circuit board and not the package substrate supporting the primary and secondary devices, the package architecture is simplified.
  • the inventory management is also simplified by having a single package architecture capable of supporting distinguishable combinations.
  • Exemplary claims for the alternate embodiment of the package architecture include an integrated circuit (IC) package, comprising a printed circuit board, a package substrate disposed on the printed circuit board, and a first integrated circuit disposed on a first surface of the package substrate, wherein the package substrate is capable of supporting a second integrated circuit, wherein the second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate, and wherein each of the plurality of pads are in electrical communication with the printed circuit board without communicating with the first integrated circuit.
  • the second integrated circuit may be disposed over the first integrated circuit in a package on package configuration, and the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration for the programmable logic device.
  • the footprint of the second integrated circuit is larger than a footprint of the first integrated circuit.
  • one of a length or a width of the footprint of the second integrated circuit is substantially similar to a corresponding length or width of a footprint of the package substrate.
  • a gap may exist between opposing surfaces of the first and second integrated circuits.
  • Another exemplary claim includes an integrated circuit package comprising a package substrate, a first integrated circuit coupled to the package substrate, and a second integrated circuit coupled to the package substrate and disposed over the first integrated circuit, wherein the second integrated stores a configuration for operation of the first integrated circuit.
  • all signal traces coupling the second integrated circuit with the package are routed through the printed circuit board prior to coupling with the first integrated circuit.
  • Another exemplary claim includes a method of packaging an integrated circuit, comprising coupling a first integrated circuit to a package substrate, coupling a second integrated circuit to the package substrate, the second integrated circuit disposed over the first integrated circuit, and coupling the package substrate to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board prior to being delivered to the first integrated circuit.
  • the first integrated circuit is a programmable logic device and the second integrated circuit is a memory device storing a configuration for operation of the first integrated circuit and the second integrated circuit is programmed with the configuration prior to being coupled to the package substrate.
  • the method may include shorting coupling traces from the second integrated circuit to dual purpose VO pins of the first integrated circuit and routing each landing pad on the package substrate designated for coupling with the second integrated circuit directly to the printed circuit board.
  • the embodiments provide for a distribution pattern for probe pads disposed on a surface of an integrated circuit.
  • the integrated circuit may be a processor or a programmable logic device in one embodiment.
  • the distribution pattern provides for a linear arrangement of the probe pads along a diagonal extending between opposing vertices of the surface of the integrated circuit.
  • the embodiments describe a packaging architecture in which a package on package architecture is applied where the stacked integrated circuits do not directly communicate with each other through the package substrate supporting the stacked integrated circuits. The embodiments enable a single unit
  • programmable logic device and configuration module which assists in the management of inventory and allows for the utilization of third party configuration devices.
  • embodiments reduce costs for the package layout by reducing customized bills of material and inventory, thereby reducing the costs associated with this overhead.
  • economies of scale are improved through a standalone design or a POP design. It should be appreciated that the capability of having the design either in the standalone format or the stacked or adjacent format further reduces the inventory and the customized bills of materials.
  • the embodiments may be utilized for any integrated circuit and are not limited to programmable logic devices. However, where the embodiments are applied to a
  • the programmable logic device may be part of a data processing system that includes one or more of the following components; a processor; memory; VO circuitry; and peripheral devices.
  • the data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable.
  • the programmable logic device can be used to perform a variety of different logic functions.
  • the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor.
  • the programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system.
  • the programmable logic device can be configured as an interface between a processor and one of the other components in the system.
  • any of the operations described herein that form part of the invention are useful machine operations.
  • the invention also relates to a device or an apparatus for performing these operations.
  • the apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer.
  • various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
  • programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed.
  • PLDs programmable logic arrays
  • PAL programmable array logic
  • FPGA field programmable gate arrays
  • CPLDs complex programmable logic devices
  • PLDs complex programmable logic devices

Abstract

An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. In addition a packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Description

BOND AND PROBE PAD DISTRIBUTION AND PACKAGE
ARCHITECTURE
BACKGROUND
[0001] Improvements in semiconductor processing technology have resulted in integrated circuit chips which are more densely populated with microelectronic elements and which provide more functionality than ever before. Furthermore, the aggressive development of semiconductor technology and the accompanying need for higher device integration has enabled current state-of-the-art chips to integrate entire systems on a single small
semiconductor die. The need to provide all the possible interconnections to these feature laden chips remains a challenge in the packaging industry, as all the required pads compete for the small peripheral space around the die. The interconnection issue has become even more challenging as these chips are utilizing newer technology nodes to achieve smaller die sizes that are pad limited.
[0002] It is conventional to test semiconductor integrated circuits during manufacture to ensure the integrity of the integrated circuits. In one testing technique integrated circuits or dies are tested by establishing electrical current between test equipment such as a tester and each integrated circuit or die. The ability to test the dies in an efficient manner is constantly being reviewed for improvements. It is desirable to be able to increase the throughput of the testing as the die size is shrinking and the pad density is increasing, both of which tend to cause constraints for the testing throughput.
[0003] In addition, some integrated circuits may be designed to function with another device, e.g., a memory chip, a co-processor, etc. Different combinations of the two devices are possible, e.g., different amounts of memory, operating frequencies, or even the ability to function without the secondary device. Packages for the different combinations tend to add to the overall cost and as such, there are continual efforts to reduce the costs for the packaging.
[0004] One exemplary application is with regard to programmable logic devices and the configuration stored in an external device, such as one or more non-volatile memory chips. The different package formats for the devices, or combination of devices, add to the inventory management overhead, in addition to requiring customized bills of materials for the owner of the programmable logic device. Along with the different package formats, different testing requirements are incurred further adding to costs. It is desirable to reduce the inventory overhead yet maintain the flexibility offered through alternative package formats.
[0005] It is within this context that the embodiments described below arise.
SUMMARY
[0006] The embodiments described herein provide an integrated circuit having a surface with a probe pad distribution pattern that enables efficient testing of the integrated circuit. It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method on a computer readable medium. Several inventive embodiments of the present invention are described below.
[0007] In one aspect of the invention, an integrated circuit (IC) is provided. The integrated circuit includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface of the die. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. The die may be tested through automated test equipment where the tester includes a probe card that has probe pins which align with the probe pads diagonally disposed along the surface of the die or dies being tested.
[0008] In another aspect of the invention, a method of testing a semiconductor device is provided. The method initiates with orienting a plurality of devices under test so that probe pads disposed along diagonally opposing vertices of successive devices under test are substantially linear. The method includes contacting the probe pads with probe pins of a probe card and transmitting electrical signals to the probe pads through the probe pins.
Responses initiated by the electrical signals are captured to verify the integrity of the device. In one embodiment, the probe card is a cantilevered probe card.
[0009] In one aspect of the invention, a packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit. Consequently, the second integrated circuit communicates with the first integrated circuit, solely through the printed circuit board. In one embodiment, the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration utilized by the programmable logic device. In another embodiment, the second integrated circuit is disposed above the first integrated circuit.
[0010] In another aspect of the invention, a method of packaging an integrated circuit is provided. The method initiates with coupling a first integrated circuit to a package substrate and then coupling a second integrated circuit to the package substrate. The second integrated circuit is disposed over the first integrated circuit in one embodiment. The method includes coupling the package substrate to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board prior to being delivered to the first integrated circuit. In one embodiment, the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration utilized by the programmable logic device.
[0011] Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
[0013] Figure 1 is a simplified schematic diagram illustrating a surface of a die having the diagonally distributed probe pads in accordance with one embodiment of the invention.
[0014] Figure 2A is a simplified schematic of the interconnection between the bond pads and the probe pads in accordance with one embodiment of the invention.
[0015] Figures 2B and 2C illustrate cross sectional side views of possible
interconnections for the bond pads and probe pads of Figures 1 and 2A in accordance with one embodiment of the invention.
[0016] Figure 3 is a simplified schematic diagram illustrating a two die testing pattern without the diagonal probe pad distribution.
[0017] Figure 4A is a simplified schematic diagram illustrating a multiple die testing pattern with the diagonal probe pad distribution in accordance with one embodiment of the invention. [0018] Figure 4B is a side view of the multi die testing apparatus of Figure 4A
[0019] Figure 5 is simplified schematic diagram illustrating an automated test system for testing multiple dies contemporaneously in accordance with one embodiment of the invention.
[0020] Figure 6 is a flowchart diagram illustrating method operations for testing a semiconductor device in accordance with one embodiment of the invention.
[0021] Figures 7A through 7C illustrate schematics showing different views for the integrated circuit and package substrate in accordance with one embodiment of the invention.
[0022] Figure 8 is a simplified schematic diagram illustrating a standalone layout where landing pads on the package substrate designated for a second integrated circuit are exclusively in communication with a printed circuit board in accordance with one embodiment of the invention.
[0023] Figures 9A and 9B are simplified schematic diagrams illustrating the stacked layout of the integrated circuit and the corresponding configuration device in accordance with one embodiment of the invention.
[0024] Figure 10 is a simplified schematic diagram illustrating the stacked layout of
Figures 9A and 9B coupled to a printed circuit board in accordance with one embodiment of the invention.
[0025] Figure 11 is a flow chart diagram illustrating the method operations for packaging and integrated circuit in accordance with one embodiment of the invention.
DETAILED DESCRIPTION
[0026] The embodiments described herein provide a pad layout for probe pads and wire bonding pads of an integrated circuit. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
[0027] The embodiments described herein provide a diagonal redistribution pattern for probe pads in a die to be packaged through wire bonding. The diagonal redistribution pattern enables low-cost schemes for multi-die probing to be performed. As explained in more detail below the redistributed probe pads are arranged in a diagonal across a surface of the die. Under this arrangement, multiple die can be probed with a linear arrangement of probe pins, by aligning the wafer diagonally. The embodiments enable the use of linear probe cards, which are less expensive and produce more reliable measurements. In one embodiment, cantilever probe technology may be utilized for the probe cards performing the testing. One skilled in the art will appreciate that cantilever probe technology has a fixed dimension in one planar direction, but is capable of moving in an orthogonal direction to the plane of the fixed dimension.
[0028] Figure 1 is a simplified schematic diagram illustrating a surface of a die having the diagonally distributed probe pads in accordance with one embodiment of the invention. Die 100 may be any semiconductor die prepared through known semiconductor
manufacturing processes. It should be appreciated that the integrated circuit may be a microprocessor, a programmable logic device (PLD), or other integrated circuits
manufactured through semiconductor manufacturing techniques. The surface of die 100 includes a plurality of bond pads 102 disposed along a perimeter of the four sides of die 100. Bond pads 102 are subsequently bonded to a package substrate through wire bonds. Prior to the wire bonding process, die 100 may undergo testing to verify the integrity of the pathways and logic within the integrated circuit. During the testing, the probe pads are contacted through probe pins of a probe card housed within automated testing equipment to stimulate signals into the integrated circuit. The responses to these signals are then captured in order to ensure integrity of die 100. The probe pad distribution illustrated in Figure 1 enables the efficient testing of die 100. As will be discussed further below multiple dies may be aligned so as to utilize cantilevered probe cards in order to complete the testing. Bond pads 102 are in electrical communication with probe pads 104 through traces 106.
[0029] Figure 2A is a simplified schematic of the interconnection between the bond pads and the probe pads in accordance with one embodiment of the invention. Die 100 includes bond pad 102 and probe pad 104 disposed on a surface of die 100. Probe pad 104 is in electrical communication with bond pad 102 through trace 106. In one embodiment, trace 106 may be disposed along a surface of die 100. In this instance, an insulative or passivation material may be disposed over the surface of die 100 between probe pad 104 and bond pad 102. Figures 2B and 2C illustrate cross sectional side views of possible interconnections for the bond pads and probe pads of Figures 1 and 2A in accordance with one embodiment of the invention. Figure 2B illustrates yet another embodiment where trace 106 is disposed on a surface of die 100 to connect probe pad 104 and bond pad 102. Passivation layer 107 is disposed over the die surface and the surface of trace 106, leaving access to probe pad 104 and bond pad 102. It should be appreciated that the various interconnections provided in Figures 2A-C are exemplary and not meant to be limiting as alternative interconnections techniques are possible. In addition, multiple techniques may be included in a single die, i.e., some connections may be defined below the surface of the die and others may be defined on the surface. Figure 2C illustrates trace 106 disposed below the surface of die 100 for connecting bond pad 102 and probe pad 104. On skilled in the art will appreciate that trace 106 connects bond pad 102 and probe pad 104 through the metallization layers within die 100. Passivation layer 107 is disposed over the top surface of die 100 and openings are defined in passivation layer 107 the enable access to a surface of each of bond pad 102 and probe pad 104. It should be appreciated that the shape of the bond pads and the probe pads, while depicted as either square or rectangular, is not meant to be limiting. That is, any suitable geometric shape may be used for the bond pads or probe pads.
[0030] Figure 3 is a simplified schematic diagram illustrating a two die testing pattern without the diagonal probe pad distribution. Probe card 110 is disposed above dies IOOA through lOOC. Probe pins 112 contact pads 102 in order to perform the testing. As illustrated in this embodiment, die IOOB disposed between die IOOA and IOOC is skipped. That is, the probe card is unable to access each bond pad for adjacent dies when the distribution pattern is along the periphery of the four sides.
[0031] Figure 4A is a simplified schematic diagram illustrating a multiple die testing pattern with the diagonal probe pad distribution in accordance with one embodiment of the invention. Dies IOOA and IOOB are aligned so that the diagonally distributed probe pads 104 are linearly arranged. In addition, probe pads 104 are separate from bond pads 102, yet corresponding probe pads and bond pads are in electrical communication. Probe card 110 contacts the corresponding dies through probe pins 112. As illustrated, the linear arrangement avoids the necessity for skipping dies and thus provides a more efficient testing technique where throughput is improved and relatively inexpensive probe cards may be utilized. It should be appreciated that while two dies IOOA and IOOB are illustrated, the embodiments are not limited to two dies. That is, more or less than two dies may be tested through the embodiments described herein. Figure 4B illustrates a side view of the multi die testing apparatus of Figure 4A. Probe card 110 contacts the die 100 through probe pins 112. In one embodiment, probe pins 112 are cantilevered probe pins. It should be appreciated that the illustration of the probe pins as being curved is for illustrative purposes and that the probe pins, such as cantilevered probe pins are typically linear, i.e., being straight, and may even have a bend defined therein. As illustrated in Figures 4A and 4B, the diagonal distribution enables a linear probe card to efficiently test the dies even with the compact probe pad distribution. [0032] Figure 5 is simplified schematic diagram illustrating an automated test system utilizing the embodiments described herein. The testing system includes integrated circuit tester 200 is in communication with test head manipulator 210, which controls test head 212. Probe card 110 is affixed to test head 212. Wafer handler/die support 214 supports the wafers or dies to be tested. In one embodiment a plurality of dies 100 are arranged in a linear arrangement where the probe pads disposed diagonally along a surface of each die are linearly aligned. Test head 212 is lowered so that probe card 110 contacts the dies 100 to be tested through corresponding probe pins. One skilled in the art will appreciate that alternative configurations depending on the manufacturer of the test system may be utilized and that the embodiments are not limited to the exemplary test system described herein.
[0033] Figure 6 is a flowchart diagram illustrating method operations for testing a semiconductor device in accordance with one embodiment of the invention. The method initiates with operation 300 where a plurality of devices under test are oriented so that probe pads disposed along diagonally opposing vertices of successively adjacent devices under test are substantially linear, as illustrated in Figures 4A and 4B. The probe card is disposed over the diagonally aligned dies without the need for skipping any of the dies. In one embodiment a cantilevered probe card may be employed in the testing of the semiconductor devices. The method then advances to operation 302 where the probe pads of the die are contacted with the probe pins from the probe card. In operation 304 electric signals are transmitted from the probe card to the probe pads. The responses to the electric signals transmitted to the probe pads are captured or recorded in operation 306. One skilled in the art will appreciate that the captured data can be analyzed to verify the integrity of the semiconductor device or integrated circuit being tested.
[0034] Further embodiments described below provide a package architecture for an integrated circuit, which may incorporate the bond and probe pads described above. The embodiments described with regard to Figures 7A- 11 provide for a package layout that is compatible with external configuration devices without complicating inventory management for the package. In one embodiment, a package on package (POP) solution is utilized for the package architecture. The POP solution is capable of functioning in a standalone design as explained further below. In another embodiment, the configuration device can be supplied and attached by the owner of the integrated circuit. In yet another embodiment, the customer or end user may supply the configuration device. Irrespective of whether the configuration device is supplied by the owner of the integrated circuit or the customer, the configuration device can be either pre-programmed or programmed at a later time. [0035] Figures 7A through 7C illustrate schematics showing different views for the package layout in accordance with one embodiment of the invention. Figure 7A is a simplified schematic diagram of the package layout from a top view. Integrated circuit 702 is disposed over package substrate 700. Package substrate 700 may include a plurality of landing pads 704 for a POP layout in accordance with one embodiment of the invention. It should be appreciated that integrated circuit 702 may be coupled to package substrate 700 through a plurality of solder balls, such as, a ball and grid array configuration. One skilled in the art will appreciate that alternative coupling techniques, besides the ball and grid array may be utilized as the ball and grid array is exemplary and not meant to be limiting. In one embodiment, a memory chip is disposed over the top of package configuration of Figure 7 as illustrated in Figures 9A- 10. Figure 7B illustrates a side view of the integrated circuit and package substrate in accordance with one embodiment of the invention. As illustrated in Figure 7B landing pads 704 are in electrical communication with a corresponding solder ball 708 disposed on an opposing surface of package 700. The embodiments described herein provide for a configuration device to be disposed over integrated circuit 702. The
configuration device disposed over integrated circuit 702 does not include any
communication pathways with integrated circuit 702 through package substrate 700. Thus, the communication pathway is between an integrated circuit disposed over the package layout of Figure 7B and a printed circuit board affixed to the package substrate or some other external device in communication with the package substrate. In one embodiment, pathway 706 through package substrate 700 is a plated through hole. In another embodiment, pathway 706 through package substrate 700 utilizes the metallization layers defined within the package substrate. Figure 7C is a bottom illustration of package substrate 700 in accordance with one embodiment of the invention. The bottom surface of package 700 provides a ball and grid array for communication with a printed circuit board in one embodiment.
[0036] Figure 8 is a simplified schematic diagram illustrating an exemplary package layout in accordance with one embodiment of the invention. In the package layout of Figure 8, which may be referred to as a standalone layout, package substrate 700 has integrated circuit 702 disposed thereon. This layout is referred to as a standalone layout since the corresponding configuration device is not disposed over integrated circuit 702. In this embodiment the connections for the landing pads 704 through package substrate 700 and into printed circuit board 710 may be grounded to prevent any damage. In another embodiment the connections may be floating. It should be appreciated that in the layout illustrated with respect to Figure 8, the Input/Outputs (I/Os) are all out board of the package on package (POP) design for simplified printed circuit board routing. One skilled in the art will appreciate that the embodiments are not limited to a POP configuration, as another chip, e.g., a memory chip, may be disposed adjacent to integrated circuit 702 as long as package substrate 700 is large enough to enable the side by side layout.
[0037] Figures 9A and 9B are simplified schematic diagrams illustrating the stacked layout of the integrated circuit and the corresponding configuration device in accordance with one embodiment of the invention. In Figure 9A a top view of the package layout is provided. Configuration device 712 is disposed over package substrate 700. As mentioned above, configuration device 712 may be a memory chip that stores a configuration for integrated circuit 702. However, the embodiments are not limited to this specific design, as integrated circuit 702 may be any integrated circuit, such as a microprocessor or a programmable logic device (PLD), and configuration device 712 may be any suitable integrated circuit. Figure 9B illustrates a side view of the stacked layout. Package substrate 700 includes a plurality of solder balls disposed on a bottom surface and is in communication with configuration device 712 through corresponding solder ball 714 and landing pad 704. Disposed between the bottom surface of configuration device 712 and the top surface of package substrate 700 is integrated circuit 702. As mentioned above integrated circuit 702 may be coupled to package substrate 700 through a ball and grid array as is known in the art. The electrical pathways connecting landing pad 704 and solder ball 708 proceeds through package substrate 700 without providing an electrical pathway to integrated circuit 702 through package substrate 700. That is, communication between configuration device 712 and integrated circuit 702 proceeds through a printed circuit board, or other external device, coupled to package substrate 700 through solder balls 708.
[0038] Figure 10 is a simplified schematic diagram illustrating the stacked layout of
Figures 9A and 9B coupled to a printed circuit board in accordance with one embodiment of the invention. Configuration device 712 is disposed over package substrate 700.
Configuration device 712 is in electrical communication with package substrate 700 through solder ball 714 and landing pad 704. Printed circuit board 710 is in communication with corresponding solder balls 708 of package substrate through pads 716. It should be appreciated that the configuration device 712 will communicate with integrated circuit 702 through pathways within printed circuit board 710 or IO pins of printed circuit board 710 that are in communication with an external device. Thus, where configuration device 712 is a memory storing a configuration for an integrated circuit, such a PLD, configuration device 712 can be programmed prior to placement on package substrate 700, through direct connect pins after placement on package substrate 700, or on the printed circuit board as is conventionally done for in system programming.
[0039] Figure 11 is a flow chart diagram illustrating the method operations for packaging and integrated circuit in accordance with one embodiment of the invention. The method initiates with operations 800 where a first integrated circuit is coupled to a package. As illustrated above, a programmable logic device may be coupled to a package substrate through conventional techniques known in the art in one embodiment of the invention. The method then advances to operation 802 where a second integrated circuit is coupled to the package substrate. The second integrated circuit is disposed over the first integrated circuit in accordance with one embodiment. It should be appreciated that the second integrated circuit may be alternatively disposed to a side of the first integrated circuit if the package substrate is large enough. In one embodiment, the second integrated circuit is disposed over the first integrated circuit in a package on package configuration. The method then advances to operation 804 for where the package substrate is coupled to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board. That is, the second integrated circuit does not communicate with the first integrated circuit directly through the package substrate since there are no pathways defining such communication between integrated circuit 702, package substrate 700 and configuration device 712. In one embodiment, the second integrated circuit may be coupled to the printed circuit board by a through via.
[0040] It should be appreciated that the embodiments for the package architecture are not meant to be limited to the exemplary references to a primary device being a
programmable logic device and a secondary device being a configuration device for the programmable logic device. For example, one skilled in the art will appreciate that the embodiments may be incorporated with a memory chip, such as flash memory, and a processor, for a mobile device or any other small form factor device. The embodiments described herein enable the design of different amounts of memory without changing the package configuration to possibly differentiate product price points. Another application for the embodiments include with the use of a central processing unit (CPU), or any other suitable processor, and static random access memory (SRAM) cache for the two devices. Other exemplary applications include a CPU and co-processor. Thus, one of the devices does not necessarily have to be a memory chip. In essence, the embodiments are applicable to a primary device that can be used both with and without a secondary device. Through the embodiments described above where the secondary device communicates to the primary device exclusively through a printed circuit board and not the package substrate supporting the primary and secondary devices, the package architecture is simplified. In turn, the inventory management is also simplified by having a single package architecture capable of supporting distinguishable combinations.
[0041] Exemplary claims for the alternate embodiment of the package architecture include an integrated circuit (IC) package, comprising a printed circuit board, a package substrate disposed on the printed circuit board, and a first integrated circuit disposed on a first surface of the package substrate, wherein the package substrate is capable of supporting a second integrated circuit, wherein the second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate, and wherein each of the plurality of pads are in electrical communication with the printed circuit board without communicating with the first integrated circuit. The second integrated circuit may be disposed over the first integrated circuit in a package on package configuration, and the first integrated circuit is a programmable logic device and the second integrated circuit stores a configuration for the programmable logic device. In one embodiment, the footprint of the second integrated circuit is larger than a footprint of the first integrated circuit. In another embodiment, one of a length or a width of the footprint of the second integrated circuit is substantially similar to a corresponding length or width of a footprint of the package substrate. A gap may exist between opposing surfaces of the first and second integrated circuits. Another exemplary claim includes an integrated circuit package comprising a package substrate, a first integrated circuit coupled to the package substrate, and a second integrated circuit coupled to the package substrate and disposed over the first integrated circuit, wherein the second integrated stores a configuration for operation of the first integrated circuit. In one embodiment, all signal traces coupling the second integrated circuit with the package are routed through the printed circuit board prior to coupling with the first integrated circuit. Another exemplary claim includes a method of packaging an integrated circuit, comprising coupling a first integrated circuit to a package substrate, coupling a second integrated circuit to the package substrate, the second integrated circuit disposed over the first integrated circuit, and coupling the package substrate to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board prior to being delivered to the first integrated circuit. In one embodiment, the first integrated circuit is a programmable logic device and the second integrated circuit is a memory device storing a configuration for operation of the first integrated circuit and the second integrated circuit is programmed with the configuration prior to being coupled to the package substrate. The method may include shorting coupling traces from the second integrated circuit to dual purpose VO pins of the first integrated circuit and routing each landing pad on the package substrate designated for coupling with the second integrated circuit directly to the printed circuit board.
[0042] In summary, the embodiments provide for a distribution pattern for probe pads disposed on a surface of an integrated circuit. The integrated circuit may be a processor or a programmable logic device in one embodiment. The distribution pattern provides for a linear arrangement of the probe pads along a diagonal extending between opposing vertices of the surface of the integrated circuit. In addition, the embodiments describe a packaging architecture in which a package on package architecture is applied where the stacked integrated circuits do not directly communicate with each other through the package substrate supporting the stacked integrated circuits. The embodiments enable a single unit
programmable logic device and configuration module, which assists in the management of inventory and allows for the utilization of third party configuration devices. The
embodiments reduce costs for the package layout by reducing customized bills of material and inventory, thereby reducing the costs associated with this overhead. In addition, economies of scale are improved through a standalone design or a POP design. It should be appreciated that the capability of having the design either in the standalone format or the stacked or adjacent format further reduces the inventory and the customized bills of materials.
[0043] The embodiments may be utilized for any integrated circuit and are not limited to programmable logic devices. However, where the embodiments are applied to a
programmable logic device, the programmable logic device may be part of a data processing system that includes one or more of the following components; a processor; memory; VO circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system.
[0044] Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
[0045] As used herein programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
[0046] Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. In the claims, elements and/or steps do not imply any particular order of operation, unless explicitly stated in the claims.
What is claimed is:

Claims

1. An integrated circuit (IC), comprising:
a plurality of bond pads disposed on a surface of the IC;
a plurality of probe pads disposed on the surface of the IC, each of the plurality of probe pads in electrical communication with corresponding bond pads, wherein the plurality of probe pads are linearly configured across the surface.
2. The IC of claim 1, wherein the plurality of probe pads are disposed diagonally along the surface of the IC.
3. The IC of claim 1, wherein the plurality of bond pads are disposed along each peripheral edge of the surface.
4. The IC of claim 1, wherein each of the plurality of probe pads and the corresponding bond pads are in electrical communication through a conductive trace.
5. The IC of claim 4, wherein the conductive trace is disposed one of below the surface of the IC or above the surface of the IC.
6. The IC of claim 2, wherein the plurality of probe pads are distributed along multiple rows.
7. A testing system, comprising:
a support for supporting a plurality of dies for testing, the plurality of dies linearly oriented such that probe pads diagonally disposed along a surface of each of the plurality of dies are substantially aligned,; and
a probe card disposed over the plurality of dies, the probe card having a plurality of probe pins aligned with the probe pads diagonally disposed along the surface of each of the plurality of dies.
8. The system of claim 7, wherein the plurality of probe pins are cantilevered.
9. The system of claim 7, wherein the plurality of dies include multiple rows of probe pads diagonally disposed.
10. The system of claim 7, wherein the plurality of dies include bond pads in electrical communication with corresponding probe pads.
11. The system of claim 10, wherein the bond pads are disposed along a perimeter of the die.
12. The system of claim 9, wherein the plurality of probe pins are arranged in multiple rows.
13. The system of claim 10, wherein the bond pads are in communication with the plurality of probe pads through a conductive trace disposed below the surface.
14. A method of testing a semiconductor device, comprising:
orienting a plurality of devices under test so that probe pads disposed along diagonally opposing vertices of successive devices under test are substantially linear;
contacting the probe pads with probe pins of a probe card;
transmitting electrical signals to the probe pads through the probe pins; and capturing responses initiated by the electrical signals.
15. The method of claim 14, wherein each of the probe pads are in electrical communication with a corresponding bond pad.
16. The method of claim 15, wherein each bond pad is disposed along an outer perimeter of each of the devices under test.
17. The method of claim 15, further comprising:
transmitting the electrical signals along a conductive trace disposed below a surface of the probe pads and corresponding bond pad.
18. The method of claim 14 wherein the capturing includes storing the responses on a computer readable storage medium.
PCT/US2010/043137 2009-07-31 2010-07-23 Bond and probe pad distribution and package architecture WO2011014434A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201080045527.6A CN102576685B (en) 2009-07-31 2010-07-23 Engage and probe pad distribution and encapsulating structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/534,002 US9267985B2 (en) 2009-07-31 2009-07-31 Bond and probe pad distribution
US12/533,997 2009-07-31
US12/533,997 US8148813B2 (en) 2009-07-31 2009-07-31 Integrated circuit package architecture
US12/534,002 2009-07-31

Publications (2)

Publication Number Publication Date
WO2011014434A2 true WO2011014434A2 (en) 2011-02-03
WO2011014434A3 WO2011014434A3 (en) 2011-04-28

Family

ID=43529919

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/043137 WO2011014434A2 (en) 2009-07-31 2010-07-23 Bond and probe pad distribution and package architecture

Country Status (2)

Country Link
CN (1) CN102576685B (en)
WO (1) WO2011014434A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581392B (en) * 2015-04-09 2017-05-01 上海兆芯集成電路有限公司 Electronic package assembly
US9788425B2 (en) 2015-04-09 2017-10-10 Via Alliance Semiconductor Co., Ltd. Electronic package assembly

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6437364B1 (en) * 2000-09-26 2002-08-20 United Microelectronics Corp. Internal probe pads for failure analysis
US20020135055A1 (en) * 2001-03-23 2002-09-26 Samsung Electronics Co., Ltd. Semiconductor device having a fuse connected to a pad and fabrication method thereof
US6605951B1 (en) * 2000-12-11 2003-08-12 Lsi Logic Corporation Interconnector and method of connecting probes to a die for functional analysis
JP2005209882A (en) * 2004-01-22 2005-08-04 Renesas Technology Corp Semiconductor package and semiconductor device
US20070241330A1 (en) * 1999-01-22 2007-10-18 Asao Nishimura Semiconductor integrated circuit device and manufacture thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399983A (en) * 1991-08-08 1995-03-21 Tokyo Electron Yamanashi Limited Probe apparatus
JP4592634B2 (en) * 2005-06-17 2010-12-01 パナソニック株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070241330A1 (en) * 1999-01-22 2007-10-18 Asao Nishimura Semiconductor integrated circuit device and manufacture thereof
US6437364B1 (en) * 2000-09-26 2002-08-20 United Microelectronics Corp. Internal probe pads for failure analysis
US6605951B1 (en) * 2000-12-11 2003-08-12 Lsi Logic Corporation Interconnector and method of connecting probes to a die for functional analysis
US20020135055A1 (en) * 2001-03-23 2002-09-26 Samsung Electronics Co., Ltd. Semiconductor device having a fuse connected to a pad and fabrication method thereof
JP2005209882A (en) * 2004-01-22 2005-08-04 Renesas Technology Corp Semiconductor package and semiconductor device

Also Published As

Publication number Publication date
WO2011014434A3 (en) 2011-04-28
CN102576685A (en) 2012-07-11
CN102576685B (en) 2017-03-08

Similar Documents

Publication Publication Date Title
CN107564894B (en) Method of manufacturing semiconductor package
KR101411565B1 (en) Apparatus and method of testing singulated dies
JP5308086B2 (en) Socket and inspection apparatus and method having the same
US8120024B2 (en) Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same
US9423423B2 (en) Probe card for testing wafers
US20100314740A1 (en) Semiconductor package, stack module, card, and electronic system
US8202764B2 (en) Method of manufacturing semiconductor package
US10062668B2 (en) Semiconductor electronic device with improved testing features and corresponding packaging method
US20080079455A1 (en) IC Chip Package, Test Equipment and Interface for Performing a Functional Test of a Chip Contained Within Said Chip Package
JP2004138405A (en) Probe for measuring semiconductor device
CN103887193A (en) Apparatus for three dimensional integrated circuit testing
TW201532160A (en) Method for testing semiconductor wafers using temporary sacrificial bond pads
US20150162318A1 (en) Chip, chip package and die
US10541185B2 (en) Semiconductor devices with bump allocation
KR20170034178A (en) Semiconductor package device
WO2011014434A2 (en) Bond and probe pad distribution and package architecture
US9267985B2 (en) Bond and probe pad distribution
US6774483B2 (en) Semiconductor assembly with a semiconductor module
JP2004138391A (en) Method for manufacturing semiconductor device
US8044498B2 (en) Interposer, semiconductor chip mounted sub-board, and semiconductor package
US20070063311A1 (en) Rewiring Substrate Strip Having a Plurality of Semiconductor Component Positions
CN112786529A (en) High density pillar interconnect conversion with stack-to-substrate connection
US8148813B2 (en) Integrated circuit package architecture
US11769700B2 (en) Semiconductor substrate, semiconductor package including semiconductor substrate, and test method of semiconductor substrate
CN113921514A (en) Test wafer, chip forming method and chip testing method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080045527.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10804920

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase in:

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10804920

Country of ref document: EP

Kind code of ref document: A2