WO2011014434A3 - Bond and probe pad distribution and package architecture - Google Patents

Bond and probe pad distribution and package architecture Download PDF

Info

Publication number
WO2011014434A3
WO2011014434A3 PCT/US2010/043137 US2010043137W WO2011014434A3 WO 2011014434 A3 WO2011014434 A3 WO 2011014434A3 US 2010043137 W US2010043137 W US 2010043137W WO 2011014434 A3 WO2011014434 A3 WO 2011014434A3
Authority
WO
WIPO (PCT)
Prior art keywords
disposed
integrated circuit
pads
package substrate
bond
Prior art date
Application number
PCT/US2010/043137
Other languages
French (fr)
Other versions
WO2011014434A2 (en
Inventor
William Y. Hata
Original Assignee
Altera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/534,002 external-priority patent/US9267985B2/en
Priority claimed from US12/533,997 external-priority patent/US8148813B2/en
Application filed by Altera Corporation filed Critical Altera Corporation
Priority to CN201080045527.6A priority Critical patent/CN102576685B/en
Publication of WO2011014434A2 publication Critical patent/WO2011014434A2/en
Publication of WO2011014434A3 publication Critical patent/WO2011014434A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Abstract

An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. In addition a packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.
PCT/US2010/043137 2009-07-31 2010-07-23 Bond and probe pad distribution and package architecture WO2011014434A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201080045527.6A CN102576685B (en) 2009-07-31 2010-07-23 Engage and probe pad distribution and encapsulating structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/534,002 US9267985B2 (en) 2009-07-31 2009-07-31 Bond and probe pad distribution
US12/533,997 2009-07-31
US12/533,997 US8148813B2 (en) 2009-07-31 2009-07-31 Integrated circuit package architecture
US12/534,002 2009-07-31

Publications (2)

Publication Number Publication Date
WO2011014434A2 WO2011014434A2 (en) 2011-02-03
WO2011014434A3 true WO2011014434A3 (en) 2011-04-28

Family

ID=43529919

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/043137 WO2011014434A2 (en) 2009-07-31 2010-07-23 Bond and probe pad distribution and package architecture

Country Status (2)

Country Link
CN (1) CN102576685B (en)
WO (1) WO2011014434A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581392B (en) * 2015-04-09 2017-05-01 上海兆芯集成電路有限公司 Electronic package assembly
US9788425B2 (en) 2015-04-09 2017-10-10 Via Alliance Semiconductor Co., Ltd. Electronic package assembly

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6437364B1 (en) * 2000-09-26 2002-08-20 United Microelectronics Corp. Internal probe pads for failure analysis
US20020135055A1 (en) * 2001-03-23 2002-09-26 Samsung Electronics Co., Ltd. Semiconductor device having a fuse connected to a pad and fabrication method thereof
US6605951B1 (en) * 2000-12-11 2003-08-12 Lsi Logic Corporation Interconnector and method of connecting probes to a die for functional analysis
JP2005209882A (en) * 2004-01-22 2005-08-04 Renesas Technology Corp Semiconductor package and semiconductor device
US20070241330A1 (en) * 1999-01-22 2007-10-18 Asao Nishimura Semiconductor integrated circuit device and manufacture thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399983A (en) * 1991-08-08 1995-03-21 Tokyo Electron Yamanashi Limited Probe apparatus
JP4592634B2 (en) * 2005-06-17 2010-12-01 パナソニック株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070241330A1 (en) * 1999-01-22 2007-10-18 Asao Nishimura Semiconductor integrated circuit device and manufacture thereof
US6437364B1 (en) * 2000-09-26 2002-08-20 United Microelectronics Corp. Internal probe pads for failure analysis
US6605951B1 (en) * 2000-12-11 2003-08-12 Lsi Logic Corporation Interconnector and method of connecting probes to a die for functional analysis
US20020135055A1 (en) * 2001-03-23 2002-09-26 Samsung Electronics Co., Ltd. Semiconductor device having a fuse connected to a pad and fabrication method thereof
JP2005209882A (en) * 2004-01-22 2005-08-04 Renesas Technology Corp Semiconductor package and semiconductor device

Also Published As

Publication number Publication date
WO2011014434A2 (en) 2011-02-03
CN102576685A (en) 2012-07-11
CN102576685B (en) 2017-03-08

Similar Documents

Publication Publication Date Title
WO2009048154A1 (en) Semiconductor device and method for designing the same
TW200511453A (en) Methods and apparatus for packaging integrated circuit devices
WO2005004195A3 (en) Method and apparatus for packaging integrated circuit devices
TW200802789A (en) Stackable molded packages and methods of making the same
SG130055A1 (en) Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
TW200419760A (en) Wafer level package, multi-package stack, and method of manufacturing the same
TW200703599A (en) Offset integrated circuit package-on-package stacking system
TW200703616A (en) Stacked type semiconductor device
AU2001249169A1 (en) Electronic module having a three dimensional array of carrier-mounted integratedcircuit packages
WO2011071603A3 (en) Module package with embedded substrate and leadframe
TW200731438A (en) Flip chip MLP with conductive ink
WO2002033752A3 (en) Electronic module having canopy-type carriers
TW200746383A (en) Component stacking for integrated circuit electronic package
EP2743979A3 (en) Chip thermal dissipation structure
TW200608551A (en) Electronic component package
TW200612526A (en) Chip package structure, package substrate and manufacturing method thereof
WO2009004870A1 (en) Semiconductor package
EP2472616A3 (en) Light-emitting device package and method of manufacturing the same
WO2011014434A3 (en) Bond and probe pad distribution and package architecture
WO2009032506A3 (en) Systems and methods for ball grid array (bga) escape routing
TW200713617A (en) Chip package and substrate thereof
KR20130101192A (en) Semiconductor package having pcb multi-substrate and method for manufacturing same
WO2007050774A3 (en) Universal pad arrangement for surface mounted semiconductor devices
US20090267206A1 (en) Stacked semiconductor package
WO2009035972A3 (en) Packaged integrated circuits and methods to form a stacked integrated circuit package

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080045527.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10804920

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10804920

Country of ref document: EP

Kind code of ref document: A2