WO2011028409A3 - Multi-port memory and operation - Google Patents

Multi-port memory and operation Download PDF

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Publication number
WO2011028409A3
WO2011028409A3 PCT/US2010/045751 US2010045751W WO2011028409A3 WO 2011028409 A3 WO2011028409 A3 WO 2011028409A3 US 2010045751 W US2010045751 W US 2010045751W WO 2011028409 A3 WO2011028409 A3 WO 2011028409A3
Authority
WO
WIPO (PCT)
Prior art keywords
control bus
ports
port memory
command received
additional control
Prior art date
Application number
PCT/US2010/045751
Other languages
French (fr)
Other versions
WO2011028409A2 (en
Inventor
J. Thomas Pawlowski
Dan Skinner
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020127006499A priority Critical patent/KR101327665B1/en
Priority to JP2012526841A priority patent/JP5549897B2/en
Priority to CN201080037507.4A priority patent/CN102483724B/en
Priority to EP10814163.1A priority patent/EP2470999B1/en
Publication of WO2011028409A2 publication Critical patent/WO2011028409A2/en
Publication of WO2011028409A3 publication Critical patent/WO2011028409A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
PCT/US2010/045751 2009-08-24 2010-08-17 Multi-port memory and operation WO2011028409A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020127006499A KR101327665B1 (en) 2009-08-24 2010-08-17 Multi-port memory and operation
JP2012526841A JP5549897B2 (en) 2009-08-24 2010-08-17 Multiport memory and its operation
CN201080037507.4A CN102483724B (en) 2009-08-24 2010-08-17 Multiport memory and operation
EP10814163.1A EP2470999B1 (en) 2009-08-24 2010-08-17 Multi-port memory and operation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/546,258 2009-08-24
US12/546,258 US8769213B2 (en) 2009-08-24 2009-08-24 Multi-port memory and operation

Publications (2)

Publication Number Publication Date
WO2011028409A2 WO2011028409A2 (en) 2011-03-10
WO2011028409A3 true WO2011028409A3 (en) 2011-06-03

Family

ID=43606198

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/045751 WO2011028409A2 (en) 2009-08-24 2010-08-17 Multi-port memory and operation

Country Status (7)

Country Link
US (2) US8769213B2 (en)
EP (1) EP2470999B1 (en)
JP (1) JP5549897B2 (en)
KR (1) KR101327665B1 (en)
CN (1) CN102483724B (en)
TW (2) TWI537976B (en)
WO (1) WO2011028409A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8281395B2 (en) * 2009-01-07 2012-10-02 Micron Technology, Inc. Pattern-recognition processor with matching-data reporting module
KR101781617B1 (en) * 2010-04-28 2017-09-25 삼성전자주식회사 System on chip including unified input/output memory management unit
US9275699B2 (en) 2012-08-17 2016-03-01 Rambus Inc. Memory with alternative command interfaces
JP5998814B2 (en) * 2012-10-03 2016-09-28 株式会社ソシオネクスト Semiconductor memory device
US10019402B2 (en) 2016-05-12 2018-07-10 Quanta Computer Inc. Flexible NVME drive management solution via multiple processor and registers without multiple input/output expander chips

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070035209A (en) * 2005-09-27 2007-03-30 삼성전자주식회사 Apparatus and method for access controlling multi-port SDRAM
KR20070113493A (en) * 2006-05-24 2007-11-29 엠텍비젼 주식회사 Multi-port memory device having register logic for providing access authority and control method thereof
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory
US20090175114A1 (en) * 2005-12-22 2009-07-09 Samsung Electronics Co., Ltd. Multi-port semiconductor memory device having variable access paths and method therefor

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JPH07160655A (en) * 1993-12-10 1995-06-23 Hitachi Ltd Memory access system
US6370605B1 (en) 1999-03-04 2002-04-09 Sun Microsystems, Inc. Switch based scalable performance storage architecture
KR100582821B1 (en) * 2003-08-29 2006-05-23 주식회사 하이닉스반도체 Multi-port memory device
US7006402B2 (en) * 2003-08-29 2006-02-28 Hynix Semiconductor Inc Multi-port memory device
US20070150667A1 (en) * 2005-12-23 2007-06-28 Intel Corporation Multiported memory with ports mapped to bank sets
US7949863B2 (en) * 2006-03-30 2011-05-24 Silicon Image, Inc. Inter-port communication in a multi-port memory device
JP2008117109A (en) * 2006-11-02 2008-05-22 Renesas Technology Corp Semiconductor integrated circuit device
WO2009089301A1 (en) * 2008-01-07 2009-07-16 Rambus Inc. Variable-width memory module and buffer
JP5599969B2 (en) * 2008-03-19 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル Multi-port memory and computer system including the multi-port memory
US8161209B2 (en) * 2008-03-31 2012-04-17 Advanced Micro Devices, Inc. Peer-to-peer special purpose processor architecture and method
US8171181B2 (en) 2008-05-05 2012-05-01 Micron Technology, Inc. Memory module with configurable input/output ports
US8407427B2 (en) * 2008-10-29 2013-03-26 Silicon Image, Inc. Method and system for improving serial port memory communication latency and reliability

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7421559B1 (en) * 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory
KR20070035209A (en) * 2005-09-27 2007-03-30 삼성전자주식회사 Apparatus and method for access controlling multi-port SDRAM
US20090175114A1 (en) * 2005-12-22 2009-07-09 Samsung Electronics Co., Ltd. Multi-port semiconductor memory device having variable access paths and method therefor
KR20070113493A (en) * 2006-05-24 2007-11-29 엠텍비젼 주식회사 Multi-port memory device having register logic for providing access authority and control method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2470999A4 *

Also Published As

Publication number Publication date
CN102483724A (en) 2012-05-30
EP2470999A4 (en) 2013-01-23
EP2470999A2 (en) 2012-07-04
US20110047311A1 (en) 2011-02-24
TW201447912A (en) 2014-12-16
TWI537976B (en) 2016-06-11
JP2013506890A (en) 2013-02-28
TW201120907A (en) 2011-06-16
TWI456584B (en) 2014-10-11
CN102483724B (en) 2015-08-19
US8769213B2 (en) 2014-07-01
US8930643B2 (en) 2015-01-06
EP2470999B1 (en) 2016-11-16
JP5549897B2 (en) 2014-07-16
KR20120055673A (en) 2012-05-31
US20140289482A1 (en) 2014-09-25
WO2011028409A2 (en) 2011-03-10
KR101327665B1 (en) 2013-11-12

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