WO2011046979A2

WO2011046979A2 - Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead

Info

Publication number: WO2011046979A2
Application number: PCT/US2010/052395
Authority: WO
Inventors: Marios C. Papaefthymiou; Alexander Ishii
Original assignee: Cyclos Semiconductor, Inc.
Priority date: 2009-10-12
Filing date: 2010-10-12
Publication date: 2011-04-21
Also published as: WO2011046980A2; US20110090018A1; WO2011046985A2; JP2013507887A; WO2011046981A2; US8358163B2; WO2011046977A3; US20140002175A1; US8339209B2; WO2011046987A2; US20110084773A1; WO2011046984A2; WO2011046977A2; KR20120093954A; US20110084775A1; US20110084772A1; WO2011046974A3; WO2011046984A3; US8593183B2; US20140015585A1

Abstract

An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network by selective decoupling of inductors, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Description

METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS WITH NO INDUCTOR OVERHEAD CROSS-REFERENCE TO RELATED APPLICATIONS

[0001 ] This patent application is a conversion of and claims priority to U.S. Provisional Patent Application No. 61/250,830, entitled SYSTEMS AND METHODS FOR RESONANT CLOCKING INTEGRATED CIRCUITS, filed October 12, 2009, which is incorporated herein in its entirety. This patent application is related to the technologies described in the following patents and applications, all of which are incorporated herein in their entireties:

U.S. Patent Application No. 12/125,009, entitled RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS, filed October 12, 2009, which claims priority to U.S. Provisional

Patent Application No. 60/931 ,582, entitled Resonant Clock and Interconnect Architecture for Programmable Logic Devices, filed May 23, 2007;

U.S. Patent Application No. , entitled RESONANT CLOCK DISTRIBUTION

NETWORK ARCHITECTURE WITH PROGRAMMABLE DRIVERS, filed concurrently herewith;

U.S. Patent Application No. , entitled Architecture FOR CONTROLLING

CLOCK CHARACTERISTICS, filed concurrently herewith;

U.S. Patent Application No. , entitled ARCHITECTURE FOR ADJUSTING

NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed concurrently herewith;

U.S. Patent Application No. , entitled ARCHITECTURE FOR FREQUENCY- SCALED OPERATION IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed concurrently herewith; U.S. Patent Application No. , entitled ARCHITECTURE FOR SlNGLE-

STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS, filed concurrently herewith;

U.S. Patent Application No. , entitled ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE, filed concurrently herewith; and

U.S. Patent Application No. , entitled RESONANT CLOCK DISTRIBUTION

NETWORK ARCHITECTURE FOR TRACKING PARAMETER VARIATIONS IN CONVENTIONAL CLOCK DISTRIBUTION NETWORKS filed concurrently herewith.

FIELD OF INVENTION

[0002] This disclosure relates generally to clock distribution network architectures for digital devices with multiple clock networks and various clock frequencies such as microprocessors, application-specific integrated circuits (ASICs), and System-on-a-Chip (SOC) devices.

BACKGROUND OF THE INVENTION

[0003] Resonant clock distribution networks have been proposed for the energy- efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower- resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance. [0004] In practice, digital devices are often specified and designed to operate at multiple clock frequencies. For example, a high-performance microprocessor may be designed to operate at multiple clock frequencies ranging from 100MHz to 3 GHz. The technique of operating a clock signal at different clock frequencies over time is commonly referred to as frequency scaling and is motivated by the need to reduce power consumption in semiconductor devices. Power consumption in digital semiconductor devices grows in proportion with the rate at which these devices switch between their digital values. When performance requirements decrease, this rate can be reduced by reducing the frequency of the clock signal, thereby reducing power consumption. [0005] The operation of clock signals at more than a single frequency also arises in the context of device binning, that is, the practice of selling at a premium a device that, due to manufacturing variations, is capable of operating at a higher peak clock f equency than another device of identical design and functionality. For example, a batch of microprocessors that was fabricated on a "fast" semiconductor manufacturing corner may contain microprocessors capable of running at clock frequencies of up to 3GHz, while an identical-in-design batch of microprocessors that was fabricated on a "typical" semiconductor manufacturing corner may contain microprocessors that can run at clock frequencies of at most 2GHz. While of identical design, the microprocessors in the first "fast" batch can be sold at significantly higher prices, due to their better achieved performance.

[0006] The challenge with the deployment of resonant clock distribution networks in multi-frequency operation contexts is that these networks typically achieve their highest energy efficiency for a relatively narrow range of clock frequencies centered around the natural frequency of the resonant network. For clock frequencies outside this narrow range, energy efficiency degrades relatively quickly and to an extent that outweighs the inherent energy advantages of resonant clocking. For example, consider a microprocessor that has been designed with a target frequency of 3 GHz, but its digital logic can only achieve a peak clock rate of 2GHz after manufacturing. In a non-resonant clock implementation of the microprocessor, the clock network can be operated at 2GHz, consuming power in proportion to its 2GHz operating frequency. In a resonant clock design, however, if the resonant clock network operates at 2GHz, instead of its natural frequency of 3 GHz, its power consumption may significantly exceed the power consumption of the non-resonant design at 2GHz. [0007] In addition to excessive power consumption, when a resonant clock network operates away from its natural frequency, the shape of the clock waveform is increasingly deformed, as the mismatch between the natural and the operating frequency increases. In extreme situations, the peak clock frequency after manufacturing may be so far from the natural frequency of the resonant clock network that the clock waveform can become deformed to the extent that clocked elements are unable to function properly using it, and the overall function of the device subsequently fails.

[0008] It is possible to address the above challenges in a number of straightforward yet impractical ways. One such approach is to enable the adjustment of the natural frequency by providing for the selective introduction of capacitance to the resonant clock network. Since the energy efficiency of the resonant clock network decreases as its capacitance increases, however, adjusting the natural frequency by introducing capacitance compromises power savings at lower operating frequencies. Moreover, the area overhead of the spare capacitance may be prohibitively high.

[0009] Another approach to the adjustment of the natural frequency is the deployment of series or parallel combinations of inductors that can be selectively engaged. In general, such combinations require multiple inductors, or relatively complex inductor structures, resulting in potentially prohibitive area overheads, particularly when support for more than two natural frequencies is required.

[0010] Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including "A 225MHz Resonant Clocked ASIC Chip," by Ziesler C, et al., International Symposium on Low-Power Electronic Design, August 2003; "Energy Recovery Clocking Scheme and Flip-Flops forJJltra Low- Energy Applications," by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and "Resonant Clocking Using Distributed Parasitic Capacitance," by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; "900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading," by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; "A 0.8-1.2GHz frequency tunable single-phase resonant-clocked FIR filter," by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007; "A Resonant Global Clock Distribution for the Cell Broadband Engine Processor," by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. In all these articles, the resonant clock distribution networks are restricted to a single natural frequency. No attempt is made and no methods are proposed for adjusting the natural frequency of the resonant clock networks in a way that addresses the aforementioned challenges.

SUMMARY OF THE DESCRIPTION

[0011] An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network by selective decoupling of inductors, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. [0012] Disclosed is a resonant clock distribution network, comprising: a plurality resonant clock drivers electrically coupled with a clock distribution network, each resonant clock driver including: an inductive element electrically coupled with a clock node of the respective resonant clock driver; a decoupling switch corresponding to the inductive element, wherein the inductive element of each of the plurality of resonant clock drivers is configured to be selectively enabled by the corresponding decoupling switch; wherein each of the plurality of resonant clock drivers are electrically coupled with each of the other plurality of clock drivers at the clock distribution network; and wherein, a natural frequency of the resonant clock distribution network is a function of a total number of inductive elements enabled in the resonant clock distribution network and the natural frequency of the resonant clock distribution network is adjusted by selecting a number of inductive elements to be enabled in the resonant clock distribution network.

[0013] Further, wherein: the resonant clock distribution network, by adjusting the natural frequency to match a frequency of a reference clock, effectively increases the energy efficiency of the resonant clock distribution network without additional inductive element overhead; the decoupling switch is a transmission gate electrically coupled between the inductive element and a mid-point supply node; each of the plurality of inductive elements have equal inductance values; each of the plurality of resonant clock drivers includes one or more drive elements electrically coupled with the clock node, the one or more drive elements configured to receive and propagate a reference clock of the clock distribution network; each of the one or more drive elements includes a pull-up element and a pull-down element for driving the resultant clock signal; the reference clock includes a pull-up reference clock and a pull-down reference clock, wherein the pull-up reference clock is supplied to a pull-up element of each of the plurality of drive elements, and wherein the pull-down reference clock is supplied to a pull-down element of each of the plurality of drive elements; each of the one or more drive elements is coupled with an enable signal, the enable signal of a given drive element causing the given drive element to receive and propagate the reference clock; an overall drive strength of the resonant clock driver at a given instant is a function of a number of the plurality of drive elements enabled at the given instant; a frequency of the reference clock is set to a specific value by the clock distribution network prior to being supplied to the plurality of driver elements and the natural frequency of the resonant clock distribution network is adjusted to the frequency of the reference clock by selectively enabling a number of inductive elements in the resonant clock distribution network [0014] Further disclosed is a method of operation of a resonant clock distribution network, the method comprising: electrically coupling a plurality of resonant clock drivers with a clock distribution network, each resonant clock driver including: an inductive element electrically coupled with a clock node of the respective resonant clock driver; a decoupling switch corresponding to the inductive element, wherein the inductive element of each of the plurality of resonant clock drivers is configured to be selectively enabled by the corresponding decoupling switch; wherein, a natural frequency of the resonant clock distribution network is a function of a total number of inductive elements enabled in the resonant clock distribution network; and selectively adjusting the natural frequency of the resonant clock distribution network by selectively enabling a number of inductive elements in the resonant clock distribution network.

[0015] Further, wherein: each of the plurality of resonant clock drivers includes one or more drive elements electrically coupled with the clock node, the one or more drive elements configured to receive and propagate a reference clock of the clock distribution network; each of the plurality of drive elements are coupled with an enable signal, the enable signal of a given drive element causing the given drive element to receive and propagate the reference clock; an overall drive strength of the resonant clock distribution network at a given instant is a function of a number of the one or more drive elements enabled at the given instant; each of the one or more drive elements includes a pull-up drive elements and a pull-down drive element; each of the pull-up drive elements receives a first duty-adjusted version of the reference clock, and wherein each of the pull-down drive elements receives a second duty-adjusted version of the reference clock.

[0016] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Fig. 1 shows a typical architecture of a resonant clock distribution network. Fig. 2 shows a typical driver design for resonant clocking with the clock load modeled as a lumped capacitor.

Fig. 3 shows an approach to adjusting natural frequency by selective introduction of capacitance in parallel to the clock load.

Fig. 4 shows an approach to adjusting natural frequency by selective introduction of inductance in parallel to the original inductor.

Fig. 5 shows an embodiment of the proposed approach for adjusting natural frequency by selective decoupling of inductors in the resonant clock distribution network.

Fig. 6 shows an alternative embodiment of the proposed approach for adjusting natural frequency by selective decoupling of inductors in the resonant clock distribution network.

DETAILED DESCRIPTION OF THE INVENTION

[0018] Figure 1 shows a typical resonant clock distribution network architecture for a semiconductor device. In this network, a buffered distribution network is used to distribute a reference clock signal to multiple final resonant clock drivers that are used to drive the clock signal across an all-metal clock distribution network. Typically, this all- metal network has an approximately symmetric topology, delivering the clock signal to the clocked elements (for example, flip-flops and clock gaters) of the semiconductor device with very low skew. Each final resonant clock driver incorporates a buffer that directly drives the all-metal network, and an inductor that is used to provide additional drive strength with low energy consumption by resonating the parasitic capacitance of the load seen by the buffer. The resulting combination of the buffer, inductor, and other ancillary circuitry is typically referred to as a resonant clock driver. [0019] Figure 2 shows a typical resonant clock driver design, in which the clock distribution network is modeled as a lumped capacitor C in series with a lumped resistance R. This driver comprises a pull-up PMOS and a pull-down NMOS device that in conjunction constitute the buffer for driving the clock distribution network. The PMOS device is connected between the clock node and the power supply terminal. The NMOS device is connected between the clock node and the ground terminal. Both devices are driven by the reference clock signal. An inductor L is connected between the clock node and a supply node with voltage at approximately the mid-point of the clock signal oscillation. For example, if the clock signal oscillates between 0V and IV, the mid-point supply voltage is approximately 0.5V. In the driver of this figure, the mid-point is implemented using two capacitors Cdd and Css. Capacitor Cdd is connected between the mid-point and the power supply terminal. Capacitor Css is connected between the midpoint and the ground terminal. To maximize energy savings, the value of the inductor is approximately chosen so that the LC tank set up by the inductor and the parasitic capacitance of the clock distribution network has a natural frequency that is approximately equal to the frequency of the reference clock signal. The switch S can be used to selectively decouple the inductor from the mid-point supply, thus providing the option of driving the clock network in non-resonant mode. When the control signal EN turns the switch on, the driver operates in resonant mode. When the switch is off, then the driver operates in non-resonant mode. In this figure, the switch is shown as an NMOS gate. In general, this switch will be typically implemented as a transmission gate.

[0020] The energy efficiency of the resonant clock driver depends on various design and operating parameters. The quality factor Q of the resonant system is an indicator of its energy efficiency. This factor is proportional to (L / C)^m / R. In general, energy efficiency decreases as R increases, due to the I²R losses associated with the flow of the current / that charges and discharges the parasitic clock load C through the resistance R. Also, for a fixed natural frequency, energy efficiency decreases as capacitance C increases, since the current flowing through resistance R increases. [0021] The mismatch between the natural frequency of the resonant clock driver LC tank and the frequency of the reference clock signal is another important factor that affects the energy efficiency of the resonant clock network. As the frequency of the reference clock that drives the resonant clock driver moves further away from the natural frequency of the resonant clock driver, energy efficiency decreases. When the mismatch between the two frequencies becomes too large, the energy consumption of the resonant clock driver becomes excessive and impractically high. Moreover, the shape of the clock waveform can become so distorted that it cannot be reliably used to clock flip-flops or other clocked elements. Consequently, resonant clock drivers tend to have a narrower range of clock frequencies at which they operate efficiently, than the range of clock frequencies typically supported by a semiconductor device that uses frequency scaling. In practice, to support the broad range of operating frequencies used in a frequency-scaled semiconductor device, the resonant driver should be capable of operating at more than one natural frequency.

[0022] Fig. 3 shows a possible approach for supporting a second natural frequency through selective introduction of capacitance in parallel with the clock load. A switch P is used to selectively connect capacitor Cp in parallel to the parasitic capacitance C of the clock network. When switch P is turned off by control signal ENP, the total capacitance seen at the clock node is C, and the natural frequency fl of the resonant clock network is proportional to 1 / (L C)ⁱⁿ . When switch P is turned on, the total capacitance seen at the clock node increases to C + Cp, resulting in a lower natural frequency f2, which is proportional to 1 / (L (C + Cp) ) . The main drawback of this approach is that, due to the additional capacitance Cp and the resistance introduced by switch P, operation at f2 has a lower Q factor than at fl, thus resulting in decreased relative energy savings. Another drawback of this approach is that the implementation of capacitance Cp using an integrated capacitor results in significant area overheads. For example, to obtain f2 = fl^m , capacitance Cp must be approximately equal to the capacitance C of the clock distribution network.

[0023] Fig. 4 shows another possible approach for supporting a second natural frequency in a resonant clock driver. In this approach, an inductor Lp is selectively introduced in parallel to the original L of the resonant clock driver using a pair of switches PI and P2. When the two switches are turned off, the total inductance in the resonant clock network is L, and the natural frequency fl of the resonant clock network is proportional to 1 / (L C) . When the two switches are turned on, the total inductance decreases to L Lp / (L + Lp), resulting in a higher natural frequency f2, which is proportional to 1 / ((L+Lp) C) . The main drawback of this approach is that, due to the decrease in total inductance, and the additional resistance introduced by switches PI and P2, operation at f2 has a lower Q factor than at fl, thus resulting in decreased relative energy savings. For clock networks operating at GHz frequencies, this decrease in energy savings is exacerbated by the fact that total resistance at the higher operating frequency f2 will be higher than at fl, due to skin effect. Another drawback of this approach is that inductance Lp must be implemented using an inductor in parallel to L, resulting in significant area overheads. For example, to obtain f2 = flⁱⁿ , inductance Lp must be approximately equal to the original inductance L in the resonant clock driver. [0024] Fig. 5 shows an embodiment of the proposed approach for adjusting a resonant clock network so that it supports multiple natural frequencies by selective decoupling of inductors connected to the resonant clock network. This embodiment relies on the existing inductors and decoupling switches SI, ..., SM of the resonant clock drivers, thus incurring no additional overheads over the original resonant clock distribution network design. If all switches are turned on, the M inductors present an effective inductance of L / M, assuming that they all have equal inductance L. Moreover, the M clock loads present a total capacitance of M C. The resulting natural frequency fl is proportional to 1 / (LC) . The natural frequency can be modified by decoupling inductors from the resonant clock distribution network using the control signals EN1, .... ENM. For example, if M / 2 of the switches are turned off, only M / 2 inductors remain coupled to the resonant clock network, yielding an effective inductance L / M / 2 = 2 L / M and a natural frequency proportional to 1 / (2 L C)^1/2. If 3 M/4 of the switches are turned off, only M / 4 inductors remain coupled to the resonant clock network, resulting in an effective inductance equal to L / M / 4 = 4 L /

M and a natural frequency proportional to 1 / (4 L C) . [0025] In Fig. 5, switches SI,... SM are shown as NMOS devices. Alternatively, these switches can be implemented as transmission gates. Other alternative embodiments are possible, in which each switch is implemented by NMOS and PMOS devices.

[0026] In Fig. 5, switches SI,... SM are connected between the inductor and the mid- point node of their corresponding drivers. In alternative embodiments, these switches can be connected between the inductor and the clock node of their corresponding drivers.

[0027] The proposed approach can be generalized in a straightforward manner to yield multiple natural frequencies by decoupling the appropriate number of inductors from the resonant clock network. In general, the inductors are not restricted to have equal inductance values. Moreover, the corresponding clock loads are not restricted to have equal capacitance values. When only a subset of these inductors is coupled to the resonant clock network, the effective inductance is determined by their parallel combination. The effective capacitance of the resonant clock network is determined by the parallel combination of the individual capacitors. [0028] Fig. 6 shows an alternative embodiment of the proposed approach. In this embodiment, control signals ΕΝ , .,.,ΕΝΜ' are included to selectively enable the drivers in the resonant clock network. In this embodiment, the drivers are controlled independently of the switches SI,..., S that are used to selectively decouple the inductors from the clock network. Moreover, in this embodiment, the control signals EN1 .,ΕΝΜ' are connected to the pull-up and pull-down devices of the resonant clock drivers through OR and AND gates, respectively. Alternative embodiments for connecting the control signals EN1 ENM' to their corresponding drivers are possible, including embodiments in which the control signals are connected to pre-driver circuitry that is used to amplify the reference clock signal, so that it can drive the relatively large pull-up and pull-down devices of the resonant clock drivers.

[0029] In alternative embodiments of the resonant clock driver shown in Fig. 6, the strength of the pull-up and pull-down devices can be programmable. Furthermore, the pull-up and the pull-down devices can be controlled by different reference clocks with different duty cycles.

[0030] A key advantage of the proposed approach is that it requires no additional inductors over the original network with natural frequency fl. Moreover, it does not require any additional capacitors.

Claims

CLAIMS We claim:

1. A resonant clock distribution network, comprising: a plurality resonant clock drivers electrically coupled with a clock distribution network, each resonant clock driver including: an inductive element electrically coupled with a clock node of the respective resonant clock driver; a decoupling switch corresponding to the inductive element, wherein the inductive element of each of the plurality of resonant clock drivers is configured to be selectively enabled by the corresponding decoupling switch; wherein each of the plurality of resonant clock drivers are electrically coupled with each of the other plurality of clock drivers at the clock distribution network; and wherein, a natural frequency of the resonant clock distribution network is a function of a total number of inductive elements enabled in the resonant clock distribution network and the natural frequency of the resonant clock distribution network is adjusted by selecting a number of inductive elements to be enabled in the resonant clock distribution network.

2. The resonant clock distribution network of claim 1, wherein the resonant clock distribution network, by adjusting the natural frequency to match a frequency of a reference clock, effectively increases the energy efficiency of the resonant clock distribution network without additional inductive element overhead.

3. The resonant clock distribution network of claim 1, wherein the decoupling switch is a transmission gate electrically coupled between the inductive element and a mid-point supply node.

4. The resonant clock distribution network of claim 1 , wherein each of the plurality of inductive elements have equal inductance values.

5. The resonant clock distribution network of claim 1, wherein each of the plurality of resonant clock drivers includes one or more drive elements electrically coupled with the clock node, the one or more drive elements configured to receive and propagate a reference clock of the clock distribution network.

6. The resonant clock distribution network of claim 5, wherein each of the one or more drive elements includes a pull-up element and a pull-down element for driving the resultant clock signal.

7. The resonant clock distribution network of claim 6, wherein the reference clock includes a pull-up reference clock and a pull-down reference clock, wherein the pull-up reference clock is supplied to a pull-up element of each of the plurality of drive elements, and wherein the pull-down reference clock is supplied to a pull-down element of each of the plurality of drive elements.

8. The resonant clock distribution network of claim 7 wherein each of the one or more drive elements is coupled with an enable signal, the enable signal of a given drive element causing the given drive element to receive and propagate the reference clock.

9. The resonant clock distribution network of claim 8, wherein an overall drive strength of the resonant clock driver at a given instant is a function of a number of the plurality of drive elements enabled at the given instant.

10. The resonant clock distribution network of claim 5, wherein a frequency of the reference clock is set to a specific value by the clock distribution network prior to being supplied to the plurality of driver elements and the natural frequency of the resonant clock distribution network is adjusted to the frequency of the reference clock by selectively enabling a number of inductive elements in the resonant clock distribution network.

1 1. A method of operation of a resonant clock distribution network, the method comprising: electrically coupling a plurality of resonant clock drivers with a clock distribution network, each resonant clock driver including: an inductive element electrically coupled with a clock node of the respective resonant clock driver; a decoupling switch corresponding to the inductive element, wherein the inductive element of each of the plurality of resonant clock drivers is configured to be selectively enabled by the corresponding decoupling switch; wherein, a natural frequency of the resonant clock distribution network is a function of a total number of inductive elements enabled in the resonant clock distribution network; and selectively adjusting the natural frequency of the resonant clock distribution network by selectively enabling a number of inductive elements in the resonant clock distribution network.

12. The method of claim 11 , wherein each of the plurality of resonant clock drivers includes one or more drive elements electrically coupled with the clock node, the one or more drive elements configured to receive and propagate a reference clock of the clock distribution network.

13. The method of claim 12, wherein each of the plurality of drive elements are coupled with an enable signal, the enable signal of a given drive element causing the given drive element to receive and propagate the reference clock.

14. The method of claim 13, wherein an overall drive strength of the resonant clock distribution network at a given instant is a function of a number of the one or more drive elements enabled at the given instant.

15. The method of claim 14, wherein each of the one or more drive elements includes a pull-up drive elements and a pull-down drive element.

16. The method of claim 15, wherein each of the pull-up drive elements receives a first duty-adjusted version of the reference clock, and wherein each of the pull-down drive elements receives a second duty-adjusted version of the reference clock.