WO2011046980A3 - Architecture for adjusting natural frequency in resonant clock distribution networks - Google Patents

Architecture for adjusting natural frequency in resonant clock distribution networks Download PDF

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Publication number
WO2011046980A3
WO2011046980A3 PCT/US2010/052396 US2010052396W WO2011046980A3 WO 2011046980 A3 WO2011046980 A3 WO 2011046980A3 US 2010052396 W US2010052396 W US 2010052396W WO 2011046980 A3 WO2011046980 A3 WO 2011046980A3
Authority
WO
WIPO (PCT)
Prior art keywords
architecture
clock distribution
distribution networks
resonant clock
natural frequency
Prior art date
Application number
PCT/US2010/052396
Other languages
French (fr)
Other versions
WO2011046980A2 (en
Inventor
Marios C. Papaefthymiou
Alexander Ishii
Original Assignee
Cyclos Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cyclos Semiconductor, Inc. filed Critical Cyclos Semiconductor, Inc.
Publication of WO2011046980A2 publication Critical patent/WO2011046980A2/en
Publication of WO2011046980A3 publication Critical patent/WO2011046980A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06Clock generators producing several clock signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/04Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Abstract

An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of resonant clock distribution networks with integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
PCT/US2010/052396 2009-10-12 2010-10-12 Architecture for adjusting natural frequency in resonant clock distribution networks WO2011046980A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25083009P 2009-10-12 2009-10-12
US61/250,830 2009-10-12

Publications (2)

Publication Number Publication Date
WO2011046980A2 WO2011046980A2 (en) 2011-04-21
WO2011046980A3 true WO2011046980A3 (en) 2011-09-15

Family

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Family Applications (8)

Application Number Title Priority Date Filing Date
PCT/US2010/052401 WO2011046984A2 (en) 2009-10-12 2010-10-12 Architecture for single-stepping in resonant clock distribution networks
PCT/US2010/052405 WO2011046987A2 (en) 2009-10-12 2010-10-12 Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks
PCT/US2010/052402 WO2011046985A2 (en) 2009-10-12 2010-10-12 Architecture for operating resonant clock network in conventional mode
PCT/US2010/052395 WO2011046979A2 (en) 2009-10-12 2010-10-12 Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead
PCT/US2010/052396 WO2011046980A2 (en) 2009-10-12 2010-10-12 Architecture for adjusting natural frequency in resonant clock distribution networks
PCT/US2010/052393 WO2011046977A2 (en) 2009-10-12 2010-10-12 Architecture for controlling clock characteristics
PCT/US2010/052397 WO2011046981A2 (en) 2009-10-12 2010-10-12 Architecture for frequency-scaled operation in resonant clock distribution networks
PCT/US2010/052390 WO2011046974A2 (en) 2009-10-12 2010-10-12 Resonant clock distribution network architecture with programmable drivers

Family Applications Before (4)

Application Number Title Priority Date Filing Date
PCT/US2010/052401 WO2011046984A2 (en) 2009-10-12 2010-10-12 Architecture for single-stepping in resonant clock distribution networks
PCT/US2010/052405 WO2011046987A2 (en) 2009-10-12 2010-10-12 Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks
PCT/US2010/052402 WO2011046985A2 (en) 2009-10-12 2010-10-12 Architecture for operating resonant clock network in conventional mode
PCT/US2010/052395 WO2011046979A2 (en) 2009-10-12 2010-10-12 Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead

Family Applications After (3)

Application Number Title Priority Date Filing Date
PCT/US2010/052393 WO2011046977A2 (en) 2009-10-12 2010-10-12 Architecture for controlling clock characteristics
PCT/US2010/052397 WO2011046981A2 (en) 2009-10-12 2010-10-12 Architecture for frequency-scaled operation in resonant clock distribution networks
PCT/US2010/052390 WO2011046974A2 (en) 2009-10-12 2010-10-12 Resonant clock distribution network architecture with programmable drivers

Country Status (4)

Country Link
US (12) US8362811B2 (en)
JP (4) JP2013507888A (en)
KR (4) KR20120093954A (en)
WO (8) WO2011046984A2 (en)

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