WO2011047368A3 - Vlsi layouts of fully connected generalized and pyramid networks with locality exploitation - Google Patents

Vlsi layouts of fully connected generalized and pyramid networks with locality exploitation Download PDF

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Publication number
WO2011047368A3
WO2011047368A3 PCT/US2010/052984 US2010052984W WO2011047368A3 WO 2011047368 A3 WO2011047368 A3 WO 2011047368A3 US 2010052984 W US2010052984 W US 2010052984W WO 2011047368 A3 WO2011047368 A3 WO 2011047368A3
Authority
WO
WIPO (PCT)
Prior art keywords
links
integrated circuit
sub
circuit blocks
vlsi layouts
Prior art date
Application number
PCT/US2010/052984
Other languages
French (fr)
Other versions
WO2011047368A2 (en
Inventor
Venkat Konda
Original Assignee
Venkat Konda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=43876924&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2011047368(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Venkat Konda filed Critical Venkat Konda
Priority to US13/502,207 priority Critical patent/US8898611B2/en
Publication of WO2011047368A2 publication Critical patent/WO2011047368A2/en
Publication of WO2011047368A3 publication Critical patent/WO2011047368A3/en
Priority to US15/351,453 priority patent/US10050904B2/en
Priority to US16/029,645 priority patent/US10554583B2/en
Priority to US16/671,177 priority patent/US10977413B1/en
Priority to US17/167,082 priority patent/US11451490B1/en
Priority to US17/938,928 priority patent/US11811683B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing

Abstract

VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther subintegrated circuit blocks. The sub-integrated circuit blocks can be arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.
PCT/US2010/052984 2009-10-16 2010-10-16 Vlsi layouts of fully connected generalized and pyramid networks with locality exploitation WO2011047368A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US13/502,207 US8898611B2 (en) 2009-10-16 2010-10-16 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US15/351,453 US10050904B2 (en) 2009-10-16 2016-11-15 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US16/029,645 US10554583B2 (en) 2009-10-16 2018-07-08 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US16/671,177 US10977413B1 (en) 2009-10-16 2019-11-01 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US17/167,082 US11451490B1 (en) 2009-10-16 2021-02-04 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US17/938,928 US11811683B1 (en) 2009-10-16 2022-09-06 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US25260909P 2009-10-16 2009-10-16
US25260309P 2009-10-16 2009-10-16
US61/252,609 2009-10-16
US61/252,603 2009-10-16

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/502,207 A-371-Of-International US8898611B2 (en) 2009-10-16 2010-10-16 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US14/522,599 Continuation US9529958B2 (en) 2009-10-16 2014-10-24 VLSI layouts of fully connected generalized and pyramid networks with locality exploitation

Publications (2)

Publication Number Publication Date
WO2011047368A2 WO2011047368A2 (en) 2011-04-21
WO2011047368A3 true WO2011047368A3 (en) 2011-06-16

Family

ID=43876924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/052984 WO2011047368A2 (en) 2009-10-16 2010-10-16 Vlsi layouts of fully connected generalized and pyramid networks with locality exploitation

Country Status (2)

Country Link
US (1) US8898611B2 (en)
WO (1) WO2011047368A2 (en)

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US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US11451490B1 (en) 2009-10-16 2022-09-20 Konda Technologies Inc. VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US9529958B2 (en) * 2014-10-24 2016-12-27 Konda Technologies Inc. VLSI layouts of fully connected generalized and pyramid networks with locality exploitation
US11405331B1 (en) 2011-09-07 2022-08-02 Konda Technologies Inc. Optimization of multi-stage hierarchical networks for practical routing applications
US10536399B2 (en) 2013-07-15 2020-01-14 Konda Technologies Inc. Automatic multi-stage fabric generation for FPGAs
US9509634B2 (en) * 2013-07-15 2016-11-29 Konda Technologies Inc. Fast scheduling and optmization of multi-stage hierarchical networks
US11509605B1 (en) 2011-09-07 2022-11-22 Konda Technologies Inc. Automatic multi-stage fabric generation for FPGAs
US11405332B1 (en) 2011-09-07 2022-08-02 Konda Technologies Inc. Fast scheduling and optimization of multi-stage hierarchical networks
US9374322B2 (en) * 2014-03-06 2016-06-21 Konda Technologies Inc. Optimization of multi-stage hierarchical networks for practical routing applications
WO2013036544A1 (en) * 2011-09-07 2013-03-14 Venkat Konda Optimization of multi-stage hierarchical networks for practical routing applications
US9069912B2 (en) 2012-03-31 2015-06-30 Qualcomm Technologies, Inc. System and method of distributed initiator-local reorder buffers
US9817933B2 (en) 2013-03-15 2017-11-14 The Regents Of The University Of California Systems and methods for switching using hierarchical networks
US9503092B2 (en) 2015-02-22 2016-11-22 Flex Logix Technologies, Inc. Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same
US10333508B2 (en) 2017-03-29 2019-06-25 International Business Machines Corporation Cross bar switch structure for highly congested environments
US10169511B2 (en) * 2017-03-29 2019-01-01 International Business Machines Corporation Method to synthesize a cross bar switch in a highly congested environment
CN109445752B (en) * 2018-10-10 2019-10-15 西安交通大学 A kind of system of parallel computation
CN109995652B (en) * 2019-04-15 2021-03-19 中北大学 Network-on-chip perception early-warning routing method based on redundant channel construction
CN110866599A (en) * 2019-11-08 2020-03-06 芯盟科技有限公司 Chip and method for establishing data path in chip

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US5541914A (en) * 1994-01-19 1996-07-30 Krishnamoorthy; Ashok V. Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fanin buffering to efficiently realize arbitrarily low packet loss
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US6335930B1 (en) * 1997-05-23 2002-01-01 Samsung Electronics Co., Ltd. Multi-stage interconnection network for high speed packet switching
US20040073699A1 (en) * 2002-09-09 2004-04-15 Hong Kang Woon Dynamic routing method for multistage bus networks in distributed shared memory environment
US20070171105A1 (en) * 2003-12-24 2007-07-26 Madurawe Raminda U Look-up table structure with embedded carry logic

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US8269523B2 (en) 2007-05-25 2012-09-18 Konda Technologies Inc. VLSI layouts of fully connected generalized networks
WO2008147927A1 (en) 2007-05-25 2008-12-04 Venkat Konda Fully connected generalized multi-link multi-stage networks
US8170040B2 (en) 2007-05-25 2012-05-01 Konda Technologies Inc. Fully connected generalized butterfly fat tree networks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654695A (en) * 1991-02-22 1997-08-05 International Business Machines Corporation Multi-function network
US5541914A (en) * 1994-01-19 1996-07-30 Krishnamoorthy; Ashok V. Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fanin buffering to efficiently realize arbitrarily low packet loss
US6335930B1 (en) * 1997-05-23 2002-01-01 Samsung Electronics Co., Ltd. Multi-stage interconnection network for high speed packet switching
US20040073699A1 (en) * 2002-09-09 2004-04-15 Hong Kang Woon Dynamic routing method for multistage bus networks in distributed shared memory environment
US20070171105A1 (en) * 2003-12-24 2007-07-26 Madurawe Raminda U Look-up table structure with embedded carry logic

Also Published As

Publication number Publication date
US20120269190A1 (en) 2012-10-25
US8898611B2 (en) 2014-11-25
WO2011047368A2 (en) 2011-04-21

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