WO2011057062A4 - Dual conducting floating spacer metal oxide semiconductor field effect transistor (dcfs mosfet) and method to fabricate the same - Google Patents
Dual conducting floating spacer metal oxide semiconductor field effect transistor (dcfs mosfet) and method to fabricate the same Download PDFInfo
- Publication number
- WO2011057062A4 WO2011057062A4 PCT/US2010/055605 US2010055605W WO2011057062A4 WO 2011057062 A4 WO2011057062 A4 WO 2011057062A4 US 2010055605 W US2010055605 W US 2010055605W WO 2011057062 A4 WO2011057062 A4 WO 2011057062A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive
- dielectric layer
- spacer
- control gate
- dcfs
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract 11
- 230000009977 dual effect Effects 0.000 title claims abstract 10
- 239000004065 semiconductor Substances 0.000 title claims abstract 10
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- -1 spacer metal oxide Chemical class 0.000 title abstract 2
- 125000006850 spacer group Chemical group 0.000 claims abstract 24
- 239000000758 substrate Substances 0.000 claims abstract 9
- 238000000151 deposition Methods 0.000 claims 6
- 238000000059 patterning Methods 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction. By storing charge in the two independent conducting floating spacers, DCFS MOSFET can have two independent sets of threshold voltages associated with the source junctions.
Claims
1. A dual conductive floating spacer memory cell, comprising: a semiconductor substrate having trench isolation in the substrate and having impurities of a first conductivity type, the semiconductor substrate having a first surface at which is formed a first source/drain region, a second source drain region and a channel region between the first source/drain region and the second source/drain region, each of the first and second source/drain region having impurities of a second conductivity type; a control gate formed above the channel region, electrically isolated therefrom by a gate dielectric layer, a first conductive floating spacer and a second conductive floating spacer each formed adjacent the control gate and electrically isolated from the control gate, the first and second conductive floating spacers being formed above the channel region and overlapping the first and second source drain regions, respectively, separated therefrom by a tunnel oxide region; and a dielectric spacer formed over and the control gate and enclosing the first and second conductive floating spacers.
2. A dual conductive floating spacer memory cell as in Claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
3. A dual conductive floating spacer memory cell as in Claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
4. A dual conductive floating spacer memory cell, wherein the dual conductive floating spacer memory cell is formed in a N AND-type non- volatile memory array.
5. A dual conductive floating spacer memory cell, wherein the dual conductive floating spacer memory cell is formed in a NOR-type non-volatile memory array.
6. A method for forming a dual conductive spacer memory cell, comprising:
depositing and patterning a first dielectric layer on a semiconductor substrate; forming a layer of tunnel oxide on the exposed semiconductor substrate not covered by the patterned first dielectric layer;
depositing a first conductive layer over the patterned first dielectric layer, etching the first conductive layer to form a first conductive spacer and a second conductive spacer above the tunnel oxide area;
removing the patterned first dielectric layer;
forming a channel oxide on the semiconductor substrate in selected area exposed by the removing of the first patterned dielectric layer, depositing a second dielectric layer on the semiconductor layer and enclosing the first and second conductive spacers;
depositing and patterning a second conductive layer over the second dielectric layer to form a control gate over and between the first and second conductive spacers; and
depositing a third dielectric layer over the control gate and etching the third dielectric layer to form dielectric spacers to enclose the control gate and the first and second conductive spacers.
7. A method as in Claim 6, wherein the first conductive layer comprises a doped poly-silicon.
8. A method as in Claim 6, wherein the first dielectric layer comprises an oxide layer approximately 12θΑ thick.
9. A method as in Claim 6, wherein the first dielectric layer comprises a nitride layer approximately 150θΑ thick.
10. A method as in Claim 6, wherein the second dielectric layer comprises an oxide- nitride-oxide stack.
11. A method as in Claim 6, further comprising forming a source drain region by ion implantation after patterning forming the control gate.
15
12. A method as in Qaim 6, further comprising a source drain region by ion implantation after forming the first conductive spacer and the second conductive spacer, and before depositing the second dielectric layer.
13. A method as in Qaim 6, further comprising forming trench isolation in the semiconductor substrate.
16
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/614,265 | 2009-11-06 | ||
| US12/614,265 US8415735B2 (en) | 2009-11-06 | 2009-11-06 | Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2011057062A2 WO2011057062A2 (en) | 2011-05-12 |
| WO2011057062A3 WO2011057062A3 (en) | 2011-07-28 |
| WO2011057062A4 true WO2011057062A4 (en) | 2011-09-15 |
Family
ID=43970778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2010/055605 WO2011057062A2 (en) | 2009-11-06 | 2010-11-05 | Dual conducting floating spacer metal oxide semiconductor field effect transistor (dcfs mosfet) and method to fabricate the same |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US8415735B2 (en) |
| WO (1) | WO2011057062A2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9219167B2 (en) | 2013-12-19 | 2015-12-22 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell |
| US10878161B2 (en) * | 2018-09-28 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Method and structure to reduce cell width in integrated circuits |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6093945A (en) | 1998-07-09 | 2000-07-25 | Windbond Electronics Corp. | Split gate flash memory with minimum over-erase problem |
| US6103573A (en) * | 1999-06-30 | 2000-08-15 | Sandisk Corporation | Processing techniques for making a dual floating gate EEPROM cell array |
| US6417049B1 (en) | 2000-02-01 | 2002-07-09 | Taiwan Semiconductor Manufacturing Company | Split gate flash cell for multiple storage |
| JP2002050703A (en) | 2000-08-01 | 2002-02-15 | Hitachi Ltd | Multi-level non-volatile semiconductor memory device |
| EP1179454A3 (en) * | 2000-08-10 | 2003-03-12 | Nihon Plast Co., Ltd. | Superimposed airbag portions bonded with silicones |
| US6746920B1 (en) * | 2003-01-07 | 2004-06-08 | Megawin Technology Co., Ltd. | Fabrication method of flash memory device with L-shaped floating gate |
| KR100609237B1 (en) | 2003-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Non-volatile memory device |
| KR100601915B1 (en) | 2003-12-31 | 2006-07-14 | 동부일렉트로닉스 주식회사 | Non-volatile memory device |
| US7547599B2 (en) * | 2005-05-26 | 2009-06-16 | Micron Technology, Inc. | Multi-state memory cell |
| KR20090055836A (en) | 2007-11-29 | 2009-06-03 | 주식회사 동부하이텍 | Method of manufacturing flash memory device |
-
2009
- 2009-11-06 US US12/614,265 patent/US8415735B2/en active Active
-
2010
- 2010-11-05 WO PCT/US2010/055605 patent/WO2011057062A2/en active Application Filing
-
2013
- 2013-03-18 US US13/846,571 patent/US8809147B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011057062A3 (en) | 2011-07-28 |
| US8809147B2 (en) | 2014-08-19 |
| US20110108904A1 (en) | 2011-05-12 |
| US8415735B2 (en) | 2013-04-09 |
| US20130224917A1 (en) | 2013-08-29 |
| WO2011057062A2 (en) | 2011-05-12 |
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