WO2011068459A1

WO2011068459A1 - Integrated chip comprising a ditch

Info

Publication number: WO2011068459A1
Application number: PCT/SE2010/051326
Authority: WO
Inventors: Christofer Silfvenius; Marcin Swillo
Original assignee: Ekklippan Ab
Priority date: 2009-12-04
Filing date: 2010-12-01
Publication date: 2011-06-09
Also published as: SE0950937A1; SE534346C2

Abstract

Integrated chip (1) for data or telecommunication or optical analysis for one, two or more wavelengths, wherein the chip (1) has a basic structure which is identical, from a carrier and upwards over the entire surface of the chip, wherein waveguides are formed at the upper surface of the chip (1) by way of the basic structure being etched down so that protruding waveguides (2; 4; 5) are formed, and wherein the chip (1) comprises monolithically integrated components. The invention is characterized in that a ditch (7) is etched down along at least one of the sides of one of the waveguides and down to an etch depth that is at least so large so as to achieve a ditch that is optically isolating.

Description

Integrated chip comprising a ditch

The present invention relates to an integrated chip for data or telecommunication or analytic applications wherein the chip can be used both for emitting light from narrow-band light sources such as lasers or broadband light sources such as for example light emitting diodes, and to be able to detect laser light or light from other light sources, for example from light emitting diodes or luminescent light from biological samples or the like.

The invention refers especially to an integrated chip comprising several optical components. Such integrated chips can in general comprise one or more components, such as for example lasers, photo diodes, diplex- ers, or matrices of such components. Each component can in turn be composed of partial components, such as for example where a diplexer comprises a number of waveguides.

As for data and telecommunication, lasers are often used to emit laser light which is modulated with the information to be emitted, and light detectors, such as photo diodes, to detect received laser light.

In applications where light is both emitted and received, possibly over several different wavelengths, there are combined chips with several different components. Swedish patent no. 0501217-4 describes such a chip which is monolithically integrated. In contrast to the conventional integrating method which is based on the so called butt-joint coupling, the patent mentioned above describes a monolithic integration without splices, wherein the chip has a basic structure, which is the same from a carrier and up over the entire surface of the chip, without any splices in the waveguide. The chip comprises a number of waveguides and compo- nents, all of which are formed through etching of the basic structure. Such a chip offers low manufacturing cost combined with a high yield.

A problem during transmitting and receiving optical signals is the risk of optical and electrical overhearing between various components. This is particularly true for the case where laser components and light detector components are arranged on the same integrated chip. Problems with undesired reflections in joints or interfaces can arise, as the connec- tion port to the optical fiber, or from other disturbing stray light. Moreover, undesired such light can exist from externally arranged components of such as lasers, light diodes and similar, as well as scattered light from imperfections in waveguides and gratings and also spontaneous emis- sion from optically active material in the chip itself.

The physical distances between components are often small, particularly in integration applications, and the risk of both electrical and optical overhearing are therefore big.

Consequently, the invention refers to an integrated chip for data or telecommunication or optical analysis for one, two or more wavelengths, wherein the chip has a basic structure which is identical, from a carrier and upwards over the en- tire surface of the chip, wherein waveguides are formed at the upper surface of the chip by way of the basic structure being etched down so that protruding waveguides are formed, and wherein the chip comprises monolithically integrated components, and is characterized in that a ditch is etched down along at least one of the sides of one of the waveguides and down to an etch depth, which is at least so large so as to achieve a ditch which is optically isolating.

The invention will now be described in more detail, with reference to the exemplifying embodiments of the invention and the accompanying drawings, wherein: Figure 1 is a perspective view of a monolithically integrated chip for optical signals according to a first preferred embodiment of the present invention;

Figure 2 is a top view of the integrated chip according to claim 1;

Figure 3 is a perspective view of a monolithically integrated chip for optical signals according to a second preferred embodiment of the present invention;

Figure 4 is a top view of the integrated chip as shown in figure 3; and

Figures 5a-5c are cross sectional views through A-A in figure 2, illustrating the detailed embodiment of a ditch wall in accordance with the present invention.

Figure 1 illustrates schematically a monolithically inte- grated chip 1, prior to metallization, with a coupling waveguide 2, an optical coupler 6 and two output waveguides 4, 5. A chip with such features is known from the Swedish patent No. 0501217-4. One or both of the waveguides 4, 5 can also serve as input waveguides to the coupler 6.

According to the invention, the chip 1 is intended for data- or telecommunication or optical analysis of one, two or more wavelengths . The chip 1 comprises a waveguide 2 with a first port 3, which port 3 is arranged to convey light into or out from the waveguide 2. The waveguide 2 is expanded, in an expanded part in form of an optical coupler 6, from the first port 3 in a direction towards a second waveguide 4 and a third waveguide 5. The various components of the chip 1 are monolithically integrated. In other words, the chip has a basic structure which is identical from a carrier and upwards over the entire surface of the chip, and the waveguides 2, 4, 5 are formed at the upper surface of the chip by way of the basic structure being etched down so that protruding waveguides are formed.

Figure 2 shows an integrated chip similar to the one in fig- ure 1. Corresponding parts have the same reference numbers in all figures.

The monolithically integrated components included in the chip 1 share a common ground plane, namely the substrate in the chip 1, constituting the n-side of the structure. Over there is a material layer constituting a p-side of the chip 1, whereby a pn- unction arises.

Along at least one of the sides of one of the waveguides, there is a ditch 7. The ditch 7 is produced by etching the monolithically integrated material structure in the chip 1 from the upper side of the chip and down to an etching depth that is at least as large so as to achieve a ditch which is optically and preferably also electrically isolating. Accord- ing to a preferred embodiment, the etching is continued at least down to an n-layer in the chip 1. According to another preferred embodiment, the etching is continued at least down to a depth where all p-layers in the structure above the pn- junction have been etched through, or at least until a depth reaching down to the pn-junction or down to the pn-junction except only a few, preferably at most 3, material layers, alternatively at least down to the first occurring n-layer except only a few, preferably at most 3, material layers in the etching direction down through the material, alternatively to a depth that at least goes past the pn-junction.

It is particularly preferred that the ditch 7 reaches down to a depth of between 50 and 5000 nm, preferably between 200 and 2000 nm. Such etching depths lead to good isolating characteristics optically as wells as electrically (see below).

The ditch 7 illustrated in the figures runs on both sides of all waveguides 2, 4, 5 of the chip 1. However, the ditch 7 may either run along only parts of one or more waveguides, enclose one or more waveguides, alternatively enclose one or more components on the chip 1. This is clear from the following .

By means of the ditch 7 an effective optical isolation of the mentioned waveguide is achieved with regard to stray light incident to the waveguide from directions that are shielded by means of the ditch 7. Such stray light can originate from nearby components or part components such as from an integrated laser, but can also consist of for instance spontaneously emitted light from the coupler 6 itself or light incident to the chip 1 from the outside. Figure 5a illustrates a cross section of a preferred embodiment of a ditch 7 according to the present invention. A waveguide, in this case the third waveguide 5, is provided with a ditch 7. The figure is for clarifying purpose not according to scale. According to a preferred embodiment, at least one wall 55 of the ditch 7, which is arranged closest to the waveguide 5, is vertical. In this case, the chip 1 is advantageously designed in absorbing material 8 on the side of the ditch 7 where the waveguide 5 is not present. Since incident, unwanted stray light L is reflected back, due to the vertical wall 55, into the absorbing material 8, such stray light L can be prevented from spreading further. It is preferred that the amount of absorbing material 8 between the mutually from each other isolated components or part components on the chip 1 is sufficient to black out essentially all such stray light L that is reflected back. According to a preferred embodiment the smallest distance between two nearby, parallel ditches, each arranged to isolate a respective waveguide, is thus at least 25 μπι. It is also preferred that earthed, alternatively biased, contact surfaces are used with the chip 1 to improve the absorption of unwanted light L in the absorbing material 8.

Figure 5b illustrates, similarly with figure 5a, a second preferred embodiment of the wall 55. At least one wall of the ditch 7, which is arranged closest to the waveguide 5, is thus inclined so that light L incident to the waveguide 5 is reflected against the ditch wall 55 out from the chip 1.

Figure 5c illustrates in a corresponding way a third preferred embodiment of the wall 55, wherein at least one wall of the ditch 7, which wall is arranged closest to the waveguide 5, is inclined so that light L incident to the waveguide 5 is reflected against the ditch wall 55 down into the substrate of the chip 1, which generally is not absorbing. This can in many cases lead to that the unwanted stray light is distributed over a larger material volume, which is desirable. On the other side, there is a risk that light is reflected back to sensitive areas in the chip. Moreover, there is a risk that disturbing interference fringe pattern occur between the walls of the chip 1. It is therefore preferred in some applications to use either the first or the second preferred embodiment of the wall 55, as described above.

As is clear from the Swedish patent no. 0501217-4, the material system in a monolithically integrated chip according to the present invention can be designed in various materials. The material structure generally consists of a number of layers of various semiconductive materials, mainly consisting of As, P, Ga, In and/or Al . There is more than one appropriate way of manufacturing a monolithically integrated grating to be used as laser cavity or filter in accordance with the present invention. The active material can further consist of a bulk layer, a multiple quantum well structure (MQW) or a combination of quantum dots (QD) .

To achieve a good isolation of a certain waveguide, it is preferred that a respective ditch runs along both sides of at least one waveguide. In other words, the considered waveguide is isolated optically by means of a ditch in accordance with the invention along both sides, why influences from incident stray light in the waveguide and on components arranged along the waveguide decrease considerably.

According to an especially preferred embodiment, also illustrated in figures 1-4, the ditch 7 is arranged to run along with and around all waveguides 2, 4, 5 arranged in a compo- nent, so that all these waveguides 2, 4, 5 are enclosed by the ditch 7.

In reality the ditch 7 does not describe, as it is illu- strated in figures 1 and 2, a closed curve. The reason for this is that light is lead into and out from the first waveguide 2, through the port 3, why an opening in the ditch 7 must be arranged in front of the port 3. The expression that the ditch 7 "encloses" all waveguides 2, 4, 5, as it is used herein, is also meant to include designs wherein the ditch 7 has openings where connections to one or more waveguides exist. The waveguides 4, 5 may also include ports for conveying light in and out, as has been mentioned above, in which case the ditch 7 is arranged with openings in front of such ports.

In cases where several components are arranged next to each other with transport waveguides arranged to convey light between components, it is preferred that at ditch is arranged to enclose all these components including transport waveguides, however with openings for possible external ports. In the case where a chip is to be cleaved, it is preferred that no ditch is arranged along a waveguide at the place of cleaving, since such a ditch can cause cleaving errors.

The undesired currents causing electrical overhearing between various components in the chip 1 mostly occur in the p- material, alternatively via pn-transitions . In the case where the ditch 7, when enclosing the group of waveguides 2, 4, 5, cuts off the p-side and the pn-transition in the chip 1 around the whole group, the group will essentially be electrically isolated from disturbing electrical overhearing from other parts of the chip 1. Such an arrangement thus leads to that a very good optical, as well as electrical, isolation can be achieved for a group of waveguides 2, 4, 5 on the chip 1. According to an especially preferred embodiment, an array of components is arranged on the same chip 1. Such a chip can for example comprise a number of components of the type illustrated in figures 1 and 2, wherein each component comprises a first waveguide 2, a second waveguide 4 and a third wave- guide 5. The second waveguide 4 comprises a laser for emitting light. The third waveguide comprises a light detector for detecting light. The part components can in this case advantageously be monolithically integrated. Light from the laser is conveyed through an expanded part in the form of an optical coupler 6 to the first waveguide 4 and further out through the port 3, and light is also conveyed from the port 3, via the first waveguide 2 and on to the light detector in the third waveguide. Various components are arranged with the respective lasers and light detectors to emit and receive light with different respective wavelengths.

Each component is in this case preferably isolated from the other components by means of a respective enclosing ditch in accordance with what has been described above, resulting in that a plurality of such components can be manufactured on one chip 1 and be operated there without substantial overhearing between components. Such manufacturing of several components and waveguides on one chip results in low manufacturing costs, for example for applications in which light with a number of various wavelengths is to be handled in parallel . The skilled person realizes that a number of components can be arranged on one monolithically integrated chip 1 in a number of different ways. For example, a number of lasers and/or light detectors for various wavelengths can be ar- ranged in separate waveguides, isolated from each other on one chip 1. Some components on the chip 1 can also be cascaded one after the other, by means of optical couplers, wherein each respective component is optically and electrically isolated from the other components as described above, with openings in the ditch for transport waveguides and so on. In this way it is for example possible to build up trip- lexers, with two lasers and a photo detector that are active on either separate wavelength. The individual components on the chip can then each be encapsulated individually without dividing the material itself. A chip with arrays of component can then be packed (aligned optically) against a fiber ribbon, or a band cable of parallel optical fibers, which results in that all components in the array can be attached to a common multi-channel control electronics circuit, which is cost saving and moreover saves physical space. This will in turn result in smaller premises needed and therefore energy-saving. In many applications, optical filters are used as components in monolithically integrated chips 1 of the present type. According to a preferred embodiment, at least one such optical filter is achieved in the chip 1 by modification of a ditch running along the waveguides in which the filter is to be arranged. This is illustrated in figures 3 and 4, in which an optical filter 52 is arranged along with the third waveguide 5. Consequently, the part of the ditch 7 running along the part of the third waveguide 5, at which the filter 52 is arranged, is located at such distance from the waveguide 5 so that the optical mode in the waveguide 5 is affected by the ditch 7 closest to the inner wall 53 of the waveguide 5, and also possibly the bottom of the ditch 53. The ditch wall 53 and/or the ditch bottom is corrugated 54, so that a filter function of the first order is achieved. The corrugation 54 of the ditch wall 53 or the ditch bottom is preferably achieved, similarly to the ditch 7 itself, by way of etching, in a way which is known as such.

The distance from the ditch 7 to the waveguide 5, and the physical geometry of the corrugated wall 53, determine the functionality of the filter regarding filter strength, pass/exclusion band, etc., in a way which is conventional as such .

Furthermore, the present inventors have surprisingly found that the size, in the plane of the chip 1 (the plane illustrated in figures 2 and 4), in the area of the ditch 7 that is etched away and also in the total etched off material volume, will affect the quality of the corrugated side wall 53 or the bottom of the ditch. An area that is too small will make it hard for the process gases to reach the etching front, resulting in a deteriorated physical structure of the corrugated wall. This is of course not desirable, since it affects the characteristics of the filter 52. A too large total etched off material volume will, on the other hand, lead to heavy regrowth during etching, which also deteriorates the structure of the corrugated side wall 53 or the bottom of the ditch. It has been realised that good etching results can be

achieved relating to the corrugation of the ditch wall 53 if the ditch 7 is at least 0.1 μπι, preferably at least 0.5 μπι wide and at most 1000 μπι, preferably at most 250 μιτι wide. The width of the ditch 7 is the dimension of the ditch 7 as can be seen in figure 4 perpendicularly to the longitudinal direction of the third waveguide 5.

It has also been realised that good etching results can be achieved in the case where the cross-sectional area of the ditch 7, perpendicularly to its main area of direction, is between 0.005 and 5000 μιτι², preferably between 0.1 and 500 μιη². To achieve a good filtering ability, it is preferred that such a monolithically integrated filter 52 comprises at least about 100 grating periods, wherein each grating period is about between 50 and 300 nm. The distance between the ditch 7 and the waveguide 5 is preferably between 0 and 10 μιη at the location of the filter 52, and at other locations preferably between 0 and 500 μπι.

In accordance with a preferred embodiment, the ditch can be exposed to air, giving a high refractive index difference. It can also be covered by a dielectric such as SiO_x, SiN_x, BCB or the corresponding, giving a lower refractive index difference, but on the other hand a better physical protection of the filter and/or the ditch. This choice depends for example on the enclosure used for the chip 1.

It is also possible to achieve other grating based optical part components by adjusting a wall of the ditch 7 closest a certain waveguide. Examples include lasers and diftractive couplers, wherein the latter can be used to couple light from the waveguide to a neighboring waveguide.

By achieving the grating based optical part components in the wall in the existing ditch 7 rather than as freestanding, separately produced, either monolithically integrated or not, components, it is easier and therefore cheaper to produce the chip 1. Specifically, the ditch 7 and the filter 52 can in many cases be manufactured in one and the same step.

Preferred embodiments have been described above. However, it is obvious for a person skilled in the art that many modifications can be made to the described embodiments. The invention shall thus not be limited to the described embodiments, but may be varied within the scope of the enclosed claims.

Claims

1. Integrated chip (1) for data or telecommunication or optical analysis for one, two or more wavelengths, wherein the chip (1) has a basic structure which is identical, from a carrier and upwards over the entire surface of the chip, wherein waveguides are formed at the upper surface of the chip (1) by way of the basic structure being etched down so that protruding waveguides (2; 4; 5) are formed, and wherein the chip (1) comprises monolithically integrated components, c h a r a c t e r i s e d in that a ditch (7) is etched down along at least one of the sides of one of the waveguides and down to an etch depth that is at least so large so as to achieve a ditch that is optically isolating.

2. Integrated chip (1) according to claim 1, c h a r a c - t e r i s e d in that the etching depth is at least so large so as to achieve a ditch that is also electrically isolating.

3. Integrated chip (1) according to claim 1 or 2 , c h a r a c t e r i s e d in that the chip (1) is arranged for data or telecommunication or optical analysis of one, two or more wavelengths and can be used to emit light and to detect light, and in that the chip (1) comprises a first waveguide (2) with a first port (3), wherein the first waveguide (2) is expanded from the first port (3) in a direction towards at least a second waveguide (4) and a third waveguide (5) .

4. Integrated chip (1) according to claim 1, 2 or 3, c h a - r a c t e r i s e d in that at least one wall (55) of the ditch (7), arranged closest to a waveguide, is vertical.

5. Integrated chip (1) according to claim 1 or 2, c h a r a c t e r i s e d in that at least one wall (55) of the ditch (7), arranged closest to a waveguide, is inclined so that light incident to the waveguide is reflected against the ditch wall (55) and in towards the substrate of the chip (1).

6. Integrated chip (1) according to claim 1, 2 or 3, c h a r a c t e r i s e d in that at least one wall (55) of the ditch (7), arranged closest to a waveguide, is inclined so that light incident to the waveguide is reflected against the ditch wall (55) and out from the chip (1) .

7. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that the width of the ditch (7) is between 0.1 and 1000 μπι.

8. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that the width of the ditch (7) is between 0.5 and 250 μητι.

9. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that the etch depth of the ditch is between 50 and 5000 nm.

10. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that the ditch (7) is arranged to run along both sides of at least one waveguide.

11. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that the ditch (7) is arranged to run along all of the waveguides (2; 4; 5) in a component in the chip (1), on all sides of all these waveguides (2;4;5), so that the waveguides (2;4;5) are surrounded by the ditch (7), except for openings for ports in the component .

12. Integrated chip (1) according to any one of the preceding claims, c h a r a c t e r i s e d in that at least one wall (53) of the ditch (7), arranged closest to a waveguide, is corrugated, and in that the corrugated wall (53) constitutes a grating based optical component.

13. Integrated chip (1) according to claim (12), c h a r a c t e r i s e d in that the grating based optical component is an optical filter.