WO2011097228A2

WO2011097228A2 - Method for driving electro-optic displays

Info

Publication number: WO2011097228A2
Application number: PCT/US2011/023340
Authority: WO
Inventors: Seth J. Bishop
Original assignee: E Ink Corporation
Priority date: 2010-02-02
Filing date: 2011-02-01
Publication date: 2011-08-11
Also published as: WO2011097228A3; US20170243547A1; US20110187689A1; US9620066B2; US9881565B2

Abstract

A large area display comprises multiple sub-units (R1C1, R1C2 etc.) arranged in rows and columns. Each sub-unit has associated row (1) and column (2) drivers, with the column driver (2) driving the column electrodes of all the sub-units in a column. A chip select means provides a separate chip select signal (CS0, CS1, CS2) to each row of sub-units, so that only one row of sub-units are scanned at a time, and all the sub-units in the selected row are scanned simultaneously. Column data are supplied to the column drivers (2) as a linear series of column data values; and delayed Gate Start Pulse signals (GSP + delay) are fed to the column drivers (2) in each column of sub-units after the first so that these column drivers (2) receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

Description

METHOD FOR DRIVING ELECTRO-OPTIC DISPLAYS

[Para 1] This application is related to U. S. Patent No. 6,252,564 and U.S. Patent Publication No. 2005/0253777.

[Para 2] This invention relates to a method for driving electro-optic displays. More specifically, this invention relates to a method for driving large displays, especially displays which are "tiled" in the sense that the large display consists of an assembly of smaller displays (of sub-units) interconnected to function as a single large display. The term "tiled display" does not imply that all the sub-units of the large display are identical, although obviously it is often convenient to use such identical sub-units.

[Para 1 ] The background nomenclature and state of the art regarding electro-optic displays is discussed at length in U.S. Patent No. 7,012,600 to which the reader is referred for further information. Accordingly, this nomenclature and state of the art will be briefly summarized below.

[Para 3] The term "electro-optic", as applied to a material or a display, is used herein in its conventional meaning in the imaging art to refer to a material having first and second display states differing in at least one optical property, the material being changed from its first to its second display state by application of an electric field to the material. Although the optical property is typically color perceptible to the human eye, it may be another optical property such as optical transmission, reflectance, luminescence or, in the case of displays intended for machine reading, pseudo-color in the sense of a change in reflectance of electromagnetic wavelengths outside the visible range.

[Para 4] The terms "bistable" and "bistability" are used herein in their conventional meaning in the art to refer to displays comprising display elements having first and second display states differing in at least one optical property, and such that after any given element has been driven, by means of an addressing pulse of finite duration, to assume either its first or second display state, after the addressing pulse has terminated, that state will persist for at least several times, for example at least four times, the minimum duration of the addressing pulse required to change the state of the display element. It is shown in U.S. Patent No. 7, 170,670 that some particle-based electrophoretic displays capable of gray scale are stable not only in their extreme black and white states but also in their intermediate gray states, and the same is true of some other types of electro-optic displays. This type of display is properly called "multi-stable" rather than bistable, although for convenience the term "bistable" may be used herein to cover both bistable and multi-stable displays.

[Para 2] Several types of electro-optic displays are known, for example:

(a) rotating bichromal member displays (see, for example, U.S. Patents Nos. 5,808,783; 5,777,782; 5,760,761; 6,054,071 6,055,091; 6,097,531 ; 6, 128,124; 6,137,467; and 6, 147,791);

(b) electrochromic displays (see, for example, O'Regan, B., et al, Nature 1991, 353, 737; Wood, D., Information Display 18(3), 24 (March 2002); Bach, U., et al, Adv. Mater., 2002, 14(11), 845; and U.S. Patents Nos. 6,301,038; 6,870.657; and 6,950,220);

(c) electro-wetting displays (see Hayes, R.A., et al, "Video-Speed Electronic Paper Based on Electrowetting", Nature, 425, 383-385 (25 September 2003) and U.S. Patent Publication No. 2005/0151709);

(d) particle-based electrophoretic displays, in which a plurality of charged particles move through a fluid under the influence of an electric field (see U.S. Patents Nos. 5,930,026; 5,961,804; 6,017,584; 6,067, 185; 6, 118,426; 6, 120,588; 6,120,839; 6, 124,851 ; 6, 130,773; and 6, 130,774; U.S. Patent Applications Publication Nos. 2002/0060321 ; 2002/0090980; 2003/0011560; 2003/0102858; 2003/0151702; 2003/0222315; 2004/0014265; 2004/0075634; 2004/0094422; 2004/0105036; 2005/0062714; and 2005/0270261; and International Applications Publication Nos. WO 00/38000; WO 00/36560; WO 00/67110; and WO 01/07961 ; and European Patents Nos. 1,099,207 Bl ; and 1,145,072 B l; and the other MIT and E Ink patents and applications discussed in the aforementioned U.S. Patent No. 7,012,600).

[Para 3] There are several different variants of electrophoretic media. Electrophoretic media can use liquid or gaseous fluids; for gaseous fluids see, for example, Kitamura, T., et al, "Electrical toner movement for electronic paper-like display", IDW Japan, 2001, Paper HCSl-1, and Yamaguchi, Y., et al., "Toner display using insulative particles charged triboelectrically", IDW Japan, 2001, Paper AMD4-4); U.S. Patent Publication No. 2005/0001810; European Patent Applications 1,462,847; 1,482,354; 1,484,635; 1,500,971; 1,501, 194; 1,536,271 ; 1,542,067; 1,577,702; 1,577,703; and 1,598,694; and International Applications WO 2004/090626; WO 2004/079442; and WO 2004/001498. The media may be encapsulated, comprising numerous small capsules, each of which itself comprises an internal phase containing electrophoretically-mobile particles suspended in a liquid suspending medium, and a capsule wall surrounding the internal phase. Typically, the capsules are themselves held within a polymeric binder to form a coherent layer positioned between two electrodes; see the aforementioned MIT and E Ink patents and applications. Alternatively, the walls surrounding the discrete microcapsules in an encapsulated electrophoretic medium may be replaced by a continuous phase, thus producing a so- called polymer-dispersed electrophoretic display, in which the electrophoretic medium comprises a plurality of discrete droplets of an electrophoretic fluid and a continuous phase of a polymeric material; see for example, U.S. Patent No. 6,866,760. For purposes of the present application, such polymer-dispersed electrophoretic media are regarded as sub-species of encapsulated electrophoretic media. Another variant is a so-called "microcell electrophoretic display" in which the charged particles and the fluid are retained within a plurality of cavities formed within a carrier medium, typically a polymeric film; see, for example, U.S. Patents Nos. 6,672,921 and 6,788,449.

[Para 5] An encapsulated electrophoretic display typically does not suffer from the clustering and settling failure mode of traditional electrophoretic devices and provides further advantages, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates. (Use of the word "printing" is intended to include all forms of printing and coating, including, but without limitation: pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; silk screen printing processes; electrostatic printing processes; thermal printing processes; inkjet printing processes; electrophoretic deposition (See U.S. Patent No. 7,339,715); and other similar techniques.) Thus, the resulting display can be flexible. Further, because the display medium can be printed (using a variety of methods), the display itself can be made inexpensively.

[Para 4] Although electrophoretic media are often opaque (since, for example, in many electrophoretic media, the particles substantially block transmission of visible light through the display) and operate in a reflective mode, many electrophoretic displays can be made to operate in a so-called "shutter mode" in which one display state is substantially opaque and one is light-transmissive. See, for example, the aforementioned U.S. Patents Nos. 6, 130,774 and 6, 172,798, and U.S. Patents Nos. 5,872,552; 6, 144,361; 6,271,823; 6,225,971; and 6, 184,856. Dielectrophoretic displays, which are similar to electrophoretic displays but rely upon variations in electric field strength, can operate in a similar mode; see U.S. Patent No. 4,418,346.

[Para 6] Other types of electro-optic media may also be used in the displays of the present invention.

[Para 7] Encapsulated electrophoretic and certain other types of electro-optic displays can be made light in weight, easy to read under a variety of lighting conditions, and have low power consumption per unit area, especially having regard to their bistability, since a bistable display only draws power when the image thereon is being rewritten (or refreshed, if an single image has to be displayed for so long a period that the quality of the displayed image begins to decline). These advantages render such displays very suitable for large area displays, for example billboard type displays or large data displays for use in sports stadia or airports or railroad stations. It is convenient to form such large area displays by tiling together a number of sub-units; see, for example, the aforementioned U.S. Patent No. 6,252,564. Two key advantages accrue from such a modular design. First, many different display configurations can be formed by assembling tiles or modules in different arrangements. Second, if a single module fails, it can be replaced in the field, at a much lower cost than replacing the entire display.

[Para 8] Such large area displays typically have a complex hierarchy of physical elements, signals and controllers. The sub-units or individual tiles may contain a certain number of pixels, or one or more characters in the case of a segmented, starburst or mosaic display. These tiles are then connected together, physically and electronically, to create a single display. The display will typically be addressed by a single controller, which may or may not distribute signals to "line controllers", which address individual lines or portions of the display. In turn, the signals may then be applied directly to the display elements, or may be used as control signals for display drivers, or may be further interpreted and processed by separate controllers for each module or tile.

[Para 9] Obviously, in order to keep costs as low as possible, it is desirable to construct such large area displays using off-the-shelf rather than purpose-built components, especially since the number of such large area displays sold is likely to be much lower than that of other types of electro-optic displays (for example, portable electronic book readers). In particular, it is desirable that the single controller of the large area display comprise one or more controllers designed to drive a single panel of the type used in the large area display.

[Para 10] It might at first glance appear that, since the large area display is bistable and since rapid updates are not likely to be a major concern in large area displays used as, for example departure boards in railroad stations and airports, the logical way to update a large area display comprised of a number of identical sub-units would be a use a controller designed to drive a single sub-unit, and simply arrange to switch the output of the controller to each sub-unit in succession. Although such a driving method is sound in principle, it is often impossible in practice because of the physical limitations of conventional display controllers and the interfaces used to connect such display controllers to sub-units in large area displays. In many cases, there are simply not enough select lines available either on the display controller or on the interfaces connecting the display controller to the sub-units of the large area display, and, as previously noted, the numbers of large area displays sold are not sufficient to justify modifications of the controllers and interfaces in such large area displays.

[Para 11] The present invention relates to a method of driving a large area display which reduces or eliminates the aforementioned problems due to the limited number of select lines on display controllers and/or interfaces.

[Para 12] Accordingly, this invention provides a method of driving a large area display comprising a plurality of sub-units arranged in a plurality of rows and columns, each sub- unit having an associated row driver and an associated column driver, the sub-units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column. The method comprises providing a separate chip select signal to each row of sub-units, so that only one row of sub-units is scanned at any one time, and all of the sub-units in the selected row are scanned simultaneously. The method further comprises supplying column data to the column drivers as a linear series of column data values under the control of a Gate Start Pulse signal and a Gate Clock signal, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and wherein delayed Gate Start Pulse signals are fed to the column drivers in each column of sub-units after the first so that the column drivers in each column of sub- units after the first receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

[Para 13] In one form of this method, the Gate Start Pulse and Gate Clock signals are provided to a programmable logic device which generates a delayed Gate Start Pulse signal at a time appropriate for the column drivers associated with a column of sub-units after the first to begin receiving data. For this purpose, the column data may be supplied to the column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the delayed Gate Start Pulse signal may cause bytes 1 to N of the linear series of data (where N is a integer equal to the number of columns in the sub-units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bytes (N+l) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

[Para 14] In another form of the method of the present invention, a display controller generates a number n of chip select signals (where k is an integer smaller than the number of rows of sub-units in the large area display) and the chip select signals from the display controller are supplied to a row selection means which generates Xk secondary chip select signals (where X is an integer such that Xk is at least equal to the number of rows of sub- units in the large area display), and the secondary chip select signals are used to supplied to the row drivers of the large area display and control which row of sub-units are rewritten at any given time.

[Para 15] This invention also provides a large area display comprising:

a plurality of sub-units arranged in a plurality of rows and columns, each sub-unit having an associated row driver and an associated column driver, the sub- units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column;

chip select means for providing a separate chip select signal to each row of sub-units, so that only one row of sub-units is scanned at any one time, and all of the sub-units in the selected row are scanned simultaneously;

column data supply means for supplying column data to the column drivers as a linear series of column data values; and means for feeding delayed Gate Start Pulse signals to the column drivers in each column of sub-units after the first so that the column drivers in each column of sub-units after the first receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

[Para 16] In one form of such a large area display, the means for feeding delayed Gate Start Pulse signals may comprise means for generating Gate Start Pulse and Gate Clock signals, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and a programmable logic device which receives the Gate Start Pulse and Gate Clock signals and generates the delayed Gate Start Pulse signals. The column data supply means may be arranged to supply the column data to the column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the means for feeding delayed Gate Start Pulse signals may be arranged to cause bytes 1 to N of the linear series of data (where N is a integer equal to the number of columns in the sub-units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bytes (N+l) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

[Para 17] The large area display of the present invention may further comprise a display controller arranged to generate a number n of chip select signals (where k is an integer smaller than the number of rows of sub-units in the large area display) and a row selection means arraged to receive the chip select signals from the display controller and to generate Xk secondary chip select signals (where X is an integer such that Xk is at least equal to the number of rows of sub-units in the large area display), and to supply the secondary chip select signals to the row drivers of the large area display. Also, in the present large area display, at least one of the sub-units may be provided, along an edge where it abuts another sub-unit, with optical means arranged to reduce the apparent width of a gap between the sub-units. Such an optical means may comprise a lens molded into the viewing surface of the sub-unit. Alternatively, at least one of the sub-units may be provided with a electro-optic medium which continues over an edge of the sub-unit where it abuts another sub-unit.

[Para 18] The large area display of the present invention may make use of any of the types of electro-optic media described above. Thus, for example, the display may comprise a rotating bichromal member or electrochromic electro-optic medium. Alternatively, the display may comprise an electrophoretic medium which itself comprises a plurality of electrically charged particles disposed in a fluid and capable of moving through the fluid under the influence of an electric field. The electrically charged particles and the fluid may be confined within a plurality of capsules or microcells, or may be present as a plurality of discrete droplets surrounded by a continuous phase comprising a polymeric material. The fluid may be liquid or gaseous.

[Para 19] The sole Figure of the accompanying drawing is a schematic top plan view of a large area display of the present invention.

[Para 20] As already noted, the accompanying drawing is a schematic top plan view of a large area display of the present invention. This large area display is formed from six sub- units arranged in three rows and two columns, the individual sub-units being denoted R[ow] lC[olumn] l etc. (The terms "rows" and "columns" are used herein not in the layman's sense of referring to horizontal and vertical lines but in the conventional manner by those skilled in the technology of active matrix electro-optic displays, i.e., "row" refers to a line of pixels or sub-units which are selected simultaneously and "column" refers to a group of pixels or sub-units interconnected by a column electrode. Thus, in the Figure, the rows of both pixels and sub-units are vertical as illustrated, while the columns are horizontal.) For purposes of illustration, it will be assumed that the individual sub-units have a resolution of 800 rows by 600 columns, so that the entire large area display shown in the Figure is an electro-optic display having a resolution of 2400 rows by 1200 columns. Although the Figure, for ease of illustration, shows substantial gaps between adjacent sub-units, it will be appreciated that in practice every attempt should be made to reduce these gaps to the minimum possible size so that overall display does appear to the observer as a single continuous display with no visible breaks within the active area of the display. Methods for reducing the visual effect of breaks between the sub-units are described below.

[Para 21] Each sub-unit has an associated row driver 1 and column driver 2. (This is convenient and conventional but not strictly necessary. A single row or column driver of sufficient capacity could operate multiple adjacent physical displays, or multiple low capacity low or column drivers could be used in a single sub-unit. In such cases, it may be necessary to distinguish "drivable" sub-units from physical sub-units; this invention is basically concerned with the former.) Each row driver 1 receives a chip select signal (designated CS) from the display controller (not shown). However, each row of sub-units receives a different chip select signal, three signals designated CSO, CS1 and CS2 being supplied to the sub-units in rows 1, 2 and 3 respectively. The three signals CSO, CS1 and CS2 are timed such that the 800 rows in row 1 are scanned, followed by the 800 rows in row 2 and finally the 800 rows in row 3. (Note that although both sub-units in row 1, i.e., R1C1 and R1C2 are scanned simultaneously, it is not essential that the same row in each sub-unit be scanned at the same time; for example, the rows in R1C1 could be scanned from left to right as illustrated in the Figure, while the rows in R1C2 could be scanned from right to left at the same time. However, in general it is preferred that the same row in each sub-unit be scanned at the same time since, if the scanning is slow enough to be perceived by the eye, this will produce a "horizontal wipe" effect typically well tolerated by observers.) In effect, the three chip select signals CSO, CS1 and CS2 enable the 2400 lines of the large area display to be scanned exactly as if it were a single conventional display.

[Para 22] The handling of the input signals to the column drivers 2 is somewhat more complicated. As already mentioned, in a conventional electro-optic display, the column data (defining what voltages to be asserted on the various column electrodes) are supplied to the column drivers as a linear series of digital column data values under the control of a Gate Start Pulse (GSP) signal and a Gate Clock (GCLK) signal, the GSP signal indicating the start of a new row of data and the GCLK signal indicating that a new column data value is supplied. Upon an appropriate transition in the GSP signal, the column drivers place data into a shift register at a rate of one byte per Gate Clock (GCLK) pulse. From the shift register, the data is latched and fed to digital/analogue converters which supply the appropriate voltages to each column electrode in a manner which is entirely conventional and need not be described in detail herein. In principle, one could load the column drivers for both columns of sub-units of the large area display shown in the Figure by taking the output from the shift registers of the column drivers of the first column of sub-units and sending them to the shift registers of the second column of sub-units. However, in practice, most commercial column drivers and/or connector interfaces do not provide an appropriate output from the column driver shift register. Accordingly, it is necessary for the large area display shown in the Figure to be provided with different circuitry for ensuring that the column drivers for the second column of sub-units (hereinafter the "second column drivers") to be provided with appropriate inputs to their shift registers.

[Para 23] For this purpose, the large area display is provided with a programmable logic device (CPLD), which receives the GSP and GCLK signals from the display controller and generates a delayed GSP ("dGSP") signal at a time appropriate from the second column drivers to begin receiving data into their shift registers, this dGSP signal (denoted "GSP + delay" in the Figure) being fed to the inputs of the second column drivers which would normally receive the GSP signal. As already noted, the column drivers are designed so that, upon receipt of an appropriate transition in the GSP signal, the column drivers place data into a shift register at a rate of one byte per Gate Clock (GCLK) pulse. In the case of the large area display shown in the Figure, upon receipt of the appropriate transition in the GSP signal, the column drivers for the first column of sub-units ("the first column drivers") proceed to place 600 successive bytes of data from the display controller into their shift registers at the rate of one bite per GCLK signal. The CPLD, upon receipt of the appropriate transition in the GSP signal, starts to count GCLK pulses, but does not generate any change in the level of the dGSP signal as yet. Note that since the second column drivers have not as yet experienced any transition in the dGSP signal, none of the first 600 bytes of data have been placed in the shift registers of these second column drivers.

[Para 24] After the receipt of the 600th byte of column data, the shift registers of the first column drivers are full, and subsequent bytes are ignored by the first column drivers. However, when the 600th GCLK pulse is received, the CPLD generates an appropriate transition in the dGSP signal, so that the second column drivers begin to place incoming bytes of data from the display controller into their shift registers. The second column drivers proceed to accumulate 600 bytes of data in this manner. Thus, at the end of the entire process, the shift registers of the first column drivers contain bytes 1-600 from the display controller, while the shift registers of the second column drivers contain bytes 601- 1200. In effect, the entire large area display "appears" to the display controller as a single 1200 pixel wide display.

[Para 25] From the foregoing, it will be seen that the present invention simplifies the hardware design of a large area display and greatly simplifies the software required to operate the display since the driving electronics can treat the system of six sub-units as one display with three source drivers and two column drivers.

[Para 26] It will be apparent to those skilled in the art that numerous changes and modifications can be made in the specific embodiments of the invention described above without departing from the scope of the invention. For example, the large area display shown in the Figure could readily be adapted to accommodate additional columns of sub- units by arranging the CPLD to generate a plurality of dGSP signals at appropriate intervals, with the first dGSP signal being fed to the second column drivers, the second dGSP signal to the third column drivers, the third dGSP signal to the fourth column drivers etc., the various dGSP signals being timed so that (again assuming each display is 600 columns wide), at the end of each complete line, the shift registers of the first column drivers contain bytes 1-600 from the display controller, the shift registers of the second column drivers contain bytes 601-1200, the shift registers of the third column drivers contain bytes 1201-1800, the shift registers of the fourth column drivers contain bytes 1801-2400, etc.

[Para 27] The specific embodiment of the invention shown in the Figure is limited to a number of rows of sub-units equal to the number of chip select (CS) signals (three in the specific embodiment discussed above) available from the display controller. However, this limitation can be overcome by interposing between the display controller and the CS inputs of the various row controllers a row selection circuit which receives the RESET, CS0, CS1 and CS2 signals from the display controller (the RESET signal being a signal which indicates that the row controllers should reset to an initial state ready to begin a complete new scan), and, as the display controller repeatedly cycles through the CS0, CS1 and CS2 signals, generates appropriate CS signals for more than three rows of sub-units. For example, in a display with nine rows of sub-units, the row selection circuit might operate as follows (where the successive rows of the table below are assumed to follow each other at regular intervals, and "CSR«" indicates a signal applied to the CS input of row controllers in row n of the sub-units): Signal from display controller Output from row selection circuit cso CSR1

CS1 CSR2

CS2 CSR3

CSO CSR4

CS1 CSR5

CS2 CSR6

CSO CSR7

CS1 CSR8

CS2 CSR9

(Cycle repeats)

In effect, and again assuming two columns of 800 x 600 pixel sub-units, what "appears" to the display controller to be the writing of three successive 1600 x 1800 images is in reality the writing of a single 1600 x 5400 image.

[Para 28] As noted above, one of the inherent problems with a large area display composed of a plurality of sub-units is concealing from a viewer, as far as possible, the junctions between sub-units, since customer acceptance of such displays is very adversely affected if viewers can see a pattern of non-switching areas between the sub-units. In many cases, it is not possible to extend the electro-optic material to the extreme edges of the sub-units since many types of sub-unit require some type of edge seal either to hold an electro-optic material in position or to prevent the entry of moisture and other environmental contaminants which may adversely affect the performance of the sub-unit.

[Para 29] Methods for concealing the junctions between sub-units may be divided into optical methods and physical methods. The term "optical methods" refers to methods in which the join is physically present but the optical properties of the display are arranged to wholly or partially hide the junction area from a viewer. For example, a peripheral portion of one or both sub-units along the junction may be modified so the viewer sees an image of the peripheral portion which is wider than the peripheral portion itself, so that the image covers at least part of the junction area, thus hiding the non-switching junction area. Appropriate forms of lens for effecting such widening of the image are well known, and are used for example in lenticular displays to enable an image of a series of narrow spaced strips to form a continuous image for a viewer. To provide the necessary lens without major expense, it is generally advantageous to modify the form of the polymeric protective layer which will typically be present on the viewing surface of a display; such polymeric protective layers are often formed of thermoplastics (for example, polyethylene terephthalate), and can readily be embossed or thermally formed to provide the necessary lens. Since the effect of the lens is to create an image of certain pixels wider than the pixels themselves, some distortion of the image may be visible at the junction, and to avoid such distortion it may be desirable to make pixel in the peripheral area smaller in one dimensions than other pixels in the display, such that the reduced size pixels appear full sized in the image produced by the lens.

[Para 30] The term "physical methods" refers to methods in which the structure of the sub-units is arranged so as to produce a reduced junction area between adjacent pixels. In one important physical method, a flexible electro-optic medium is used, and this flexible medium is carried over the edge of the sub-unit in the junction area; in many cases, it will be necessary or desirable to provide a curved edge on the sub-unit to avoid damage to the electro-optic medium. Any necessary edge seal for the electro-optic medium can then be provided on a side surface of the sub-unit at a location spaced from the viewing surface of the large area display where the edge seal is hidden by the overlying electro-optic medium. If the electro-optic medium is carried over the edges of both sub-units in the junction area in this manner, the non-switching area can be reduced to a negligible width and hence made virtually invisible to a view of the large area display.

Claims

1. A method of driving a large area display comprising a plurality of sub- units arranged in a plurality of rows and columns, each sub-unit having an associated row driver and an associated column driver, the method being characterized in that the sub-units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column, the method comprising providing a separate chip select signal to each row of sub-units, so that only one row of sub-units is scanned at any one time, and all of the sub-units in the selected row are scanned simultaneously, and supplying column data to the column drivers as a linear series of column data values under the control of a Gate Start Pulse signal and a Gate Clock signal, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and wherein delayed Gate Start Pulse signals are fed to the column drivers in each column of sub-units after the first so that the column drivers in each column of sub-units after the first receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

2. A method according to claim 1 wherein the Gate Start Pulse and Gate Clock signals are provided to a programmable logic device which generates a delayed Gate Start Pulse signal at a time appropriate for the column drivers associated with a column of sub-units after the first to begin receiving data.

3. A method according to claim 2 wherein the column data are supplied to the column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the delayed Gate Start Pulse signal causes bytes 1 to N of the linear series of data (where N is a integer equal to the number of columns in the sub- units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bytes (N+l) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

4. A method according to claim 1 wherein a display controller generates a number n of chip select signals (where k is an integer smaller than the number of rows of sub- units in the large area display) and the chip select signals from the display controller are supplied to a row selection means which generates Xk secondary chip select signals (where X is an integer such that Xk is at least equal to the number of rows of sub-units in the large area display), and the secondary chip select signals are used to supplied to the row drivers of the large area display and control which row of sub-units are rewritten at any given time.

5. A large area display comprising:

a plurality of sub-units arranged in a plurality of rows and columns, each sub- unit having an associated row driver and an associated column driver, the sub-units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column;

the display being characterized by:

chip select means for providing a separate chip select signal to each row of sub-units, so that only one row of sub-units is scanned at any one time, and all of the sub- units in the selected row are scanned simultaneously;

column data supply means for supplying column data to the column drivers as a linear series of column data values; and

means for feeding delayed Gate Start Pulse signals to the column drivers in each column of sub-units after the first so that the column drivers in each column of sub-units after the first receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

6. A large area display according to claim 5 wherein the means for feeding delayed Gate Start Pulse signals comprises means for generating Gate Start Pulse and Gate Clock signals, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and a programmable logic device which receives the Gate Start Pulse and Gate Clock signals and generates the delayed Gate Start Pulse signals.

7. A large area display according to claim 6 wherein the column data supply means is arranged to supply the column data to the column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the means for feeding delayed Gate Start Pulse signals are arranged to cause bytes 1 to N of the linear series of data (where N is a integer equal to the number of columns in the sub-units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bytes (N+l) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

8. A large area display according to claim 5 further comprising a display controller arranged to generate a number n of chip select signals (where k is an integer smaller than the number of rows of sub-units in the large area display) and a row selection means arraged to receive the chip select signals from the display controller and to generate Xk secondary chip select signals (where X is an integer such that Xk is at least equal to the number of rows of sub-units in the large area display), and to supply the secondary chip select signals to the row drivers of the large area display.

9. A large area display according to claim 5 wherein at least one of the sub-units is provided, along an edge where it abuts another sub-unit, with optical means arranged to reduce the apparent width of a gap between the sub-units.

10. A large area display according to claim 9 wherein the optical means comprises a lens molded into the viewing surface of the sub-unit.

11. A large area display according to claim 5 wherein at least one of the sub-units is provided with a electro-optic medium which continues over an edge of the sub- unit where it abuts another sub-unit.

12. A large area display according to claim 5 comprising a rotating bichromal member or electrochromic electro-optic medium.

13. A large area display according to claim 5 comprising an electrophoretic medium which itself comprises a plurality of electrically charged particles disposed in a fluid and capable of moving through the fluid under the influence of an electric field.

14. A large area display according to claim 13 wherein the electrically charged particles and the fluid are confined within a plurality of capsules or microcells.

15. A large area display according to claim 13 wherein the electrically charged particles and the fluid are present as a plurality of discrete droplets surrounded by a continuous phase comprising a polymeric material.

16. An electro-optic display according to claim 34 wherein the fluid is gaseous.