WO2011147443A1

WO2011147443A1 - Extended bitmaps for a programmable logic device

Info

Publication number: WO2011147443A1
Application number: PCT/EP2010/057192
Authority: WO
Inventors: Anthony Stansfield; Stuart Parry
Original assignee: Panasonic Corporation
Priority date: 2010-05-25
Filing date: 2010-05-25
Publication date: 2011-12-01

Abstract

A configuration interface, and associated method, for a programmable logic device, comprises configuration data means arranged to receive and store configuration data and address data means arranged to receive and store address data indicative of at least one location in the programmable logic device where the configuration data is to be written. The configuration interface also comprises address modification means arranged to receive address modification instructions, replacement address means arranged to receive replacement address data from a memory unit and modifying means arranged to modify the stored address data based on the information contained in the address modification instructions and the replacement address data received from the memory unit.

Description

EXTENDED BITMAPS FOR A PROGRAMMABLE LOGIC DEVICE

The present invention relates to the field of programmable logic devices. More specifically, the present invention relates to a system and method for using extended bitmaps for a programmable logic device.

Programmable logic devices (PLDs), such as Field Programmable Gate Arrays (FPGAs) or D-Fabrix Architecture (DFA), are often used to target applications which contain parameters, i.e. variables that can take a range of values but do not change during the execution of the application. Examples of such values are modes of operation of the PLD device, and descriptions of other devices which the PLD has to interface with. The benefit of using such modes of operation is that the same PLD can be used in multiple devices, each one of which comprising different operating parameters. For example, the same PLD could provide a reconfigurable digital filter to various devices, each configuration having different filter coefficients.

In order to configure such PLDs using prior art systems, it is necessary to have a memory unit comprising a plurality of configurations, each one containing parameters which are unique to a particular mode of operation. In such prior art system, each different configuration is stored in memory, even if much of the configuration program is common for each configuration. This need to store multiple configurations adds to the application footprint and so requires access to a larger amount of memory.

One method of trying to solve this problem is by using software to select the appropriate configurations. Such methods for selecting a configuration typically include software which comprises code that decides which of the configurations should be used, and then copies the selected configuration to the reconfigurable component.

This approach however means that the software has to be modified every time the number of PLD configurations, or the reason for selecting one rather than another, changes.

In many design projects, PLD programming is viewed as a hardware task, which should ordinarily be separate from software development. Therefore, the introduction of multiple different operating modes for a PLD can result in an undesirable coupling between hardware and software development.

Accordingly, there is a clear need for, on one hand, a system for rapidly and efficiently configuring a PLD having multiple operating modes and, on the other hand, reducing the amount of memory resources allocated to such a system, without the need to use dedicated software to select the appropriate configuration parameters.

In order to solve the problems associated with the prior art, the present invention provides a configuration interface for a programmable logic device, the configuration interface comprises:

configuration data means arranged to receive and store configuration data;

address data means arranged to receive and store address data indicative of at least one location in the programmable logic device where the configuration data is to be written;

address modification means arranged to receive address modification instructions;

replacement address means arranged to receive replacement address data from a memory unit; and

modifying means arranged to modify the stored address data based on the information contained in the address modification instructions and the replacement address data received from the memory unit.

The memory unit may be a control register.

Alternatively, the memory unit is part of a mode selection Random

Access Memory (ROM).

Preferably, the configuration data, the address data, the address data modification instructions are data words of a predetermined number of bits.

Preferably, the predetermined number of bits is 32.

The present invention also provides a system for configuring a programmable logic device, the system comprises: a control processor;

a mode selection unit;

a configurable component;

a configuration memory for storing configurations of the configurable component;

a memory unit;

a configuration interface in accordance with any of claims 1 to 5.

The memory unit may form part of the mode selection unit.

Alternatively, the memory unit is a control register.

Preferably, the control register is arranged to interface with the control processor and the configuration interface.

The present invention also provides a method of configuring a programmable logic device including the steps of:

receiving and storing configuration data;

receiving and storing address data indicative of at least one location in the programmable logic device where the configuration data is to be written; receiving address modification instructions;

receiving replacement address data from a memory unit; and

modifying the stored address data based on the information contained in the address modification instructions and the replacement address data received from the memory unit.

Preferably, the predetermined number of bits is 32.

As will be appreciated, the present invention provides several advantages over the prior art. For example, by using the system in accordance with the present invention, it is possible to reuse large segments of a configuration. The present invention also allows separation of hardware and software development activities. The present invention also allows the reduction of configuration size when multiple operating modes are used. Specific embodiment of the present invention will now be described, with reference to enclosed drawings, in which:

Figure 1 represents a system in accordance with the prior art;

Figure 2 represent a system in accordance with one embodiment of the present invention;

Figure 3 represents a system in accordance with a second embodiment of the present invention;

Figure 4 represents a system in accordance with a third embodiment of the present invention;

Figure 5 represents a diagram showing possible bitstream words used in a system in accordance with one embodiment of the present invention; and

Figure 6 represents a comparative diagram of the memory resources needed to store two configurations in a system in accordance with the prior art, and a system in accordance with the present invention.

Figure 1 shows a functional block diagram of a system in accordance with the prior art. A mode selection circuit is interfaced with a control processor, which is connected to a memory bus. A memory is also connected to the memory bus. A reconfigurable component is connected to the memory bus, via a configuration interface.

While the system is starting, the control processor reads data from the mode selection circuit. This circuit may be an external ROM, a set of switches, or some other circuit that can store data to indicate the operating mode of the system. Then, the control processor executes a program that analyses the information read from the mode selection circuit. Based on the results of this program, the control processor selects one of the sets of configuration data stored in its memory (i.e. one of configuration 1 , configuration 2, etc.) to copy to the configuration interface. Finally, the configuration interface receives the data from the selected configuration and loads it specific locations of the reconfigurable component, which locations are determined by addresses contained in the various configurations. Figure 2 shows a functional block diagram of a system in accordance with one embodiment of the present invention. A mode selection circuit is interfaced with a control processor, which is connected to a memory bus. A memory is also connected to the memory bus. A reconfigurable component is connected to the memory bus, via a configuration interface. A control register interfaces with both the control processor and the configuration interface.

The configuration interface of this embodiment comprises a data register (not shown), that stores data that is to be loaded into the reconfigurable array, and an address register (not shown), that determines where in the array the data is to be loaded. In the present embodiment, the data register is 29 bits wide, and the address register is 16 bits wide.

The data register can be updated by the bitstream either directly of indirectly. In a direct update, the register changes in a way that depends only on the contents of a word in the bitstream. In an indirect update, the bitstream word encodes a read from the control register, and the read data is used to modify the configuration interface register.

Figure 3 shows a functional block diagram of a system in accordance with a second embodiment of the present invention. A mode selection circuit is interfaced with a control processor, which is connected to a memory bus. A memory is also connected to the memory bus. A reconfigurable component is connected to the memory bus, via a configuration interface. A control register is interfaced with both the mode selection circuit and the configuration interface.

This embodiment is particularly advantageous in situations where the reconfigurable component is the only part of the system that needs access to the mode selection circuit. In this case, it is possible to have the control register connected directly to the mode selection circuit, instead of having to go through the processor. In this situation, the processor does not need any connection to the mode selection circuit.

As with the previous embodiment, the configuration interface of this embodiment comprises a data register (not shown), that stores data that is to be loaded into the reconfigurable array, and an address register (not shown), that determines where in the array the data is to be loaded. In the present embodiment, the data register is 29 bits wide, and the address register is 16 bits wide.

Figure 4 shows a functional block diagram of a system in accordance with a third embodiment of the present invention. A mode selection ROM is interfaced with a control processor, which is connected to a memory bus. A memory is also connected to the memory bus. A reconfigurable component is connected to the memory bus, via a configuration interface. The mode selection ROM is also interfaced with the configuration interface.

As with the previous embodiments, the configuration interface of this embodiment comprises a data register (not shown), that stores data that is to be loaded into the reconfigurable array, and an address register (not shown), that determines where in the array the data is to be loaded. In the present embodiment, the data register is 29 bits wide, and the address register is 16 bits wide.

This embodiment is also advantageous in situations where the reconfigurable component is the only part of the system that needs access to the mode selection circuit. Moreover, this embodiment provides a further advantage, in that it allows a simplification of the interface between the configuration interface and the mode selection ROM. In this situation, the processor does not need any connection to the mode selection ROM.

The data register can be updated by the bitstream either directly of indirectly. In a direct update, the register changes in a way that depends only on the contents of a word in the bitstream. In an indirect update, the bitstream word encodes a read from the mode selection ROM, and the read data is used to modify the configuration interface register.

The bitstream in one embodiment comprises a sequence of 32-bit words. The format of these words is shown in Figure 5. Figure 5A represents a data set word, Figure 5B represents an address set word and Figure 5C represents a address modifier word.

A data set word, which in the embodiment of Figure 5A has bits 31 and 30 being set to 1 and 0, respectively, directly loads the 29-bit data register with the value in the bottom 29 bits of the bitstream word. Bit 29 (i.e. bit "C") is a control bit that determines whether the contents of the data register are to be written to the reconfigurable array. If this bit is 1 , then the data register is written into the array, and if it is 0, no write is performed. The address register is automatically incremented after the contents of the data register have been written into the reconfigurable component. This address register is not however incremented if no write operation takes place.

An address set word, which in the embodiment of Figure 5B has bits 31 and 30 being set to 0 and 0, respectively, directly modifies the 16-bit address register. The form of the change depends on the values of the Mode, namely bits 24 and 25. If Mode = 00, the address register is XORed with the bottom 16 bits of the bitstream word to generate the new value of the address register. If Mode = 01 , the address register is ANDed with the bottom 16 bits of the bitstream word to generate the new value of the address register. If Mode = 10, the address register is ORed with the bottom 16 bits of the bitstream word to generate the new value of the address register. Finally, Mode = 1 1 , the address register is replaced with the bottom 16 bits of the bitstream word. There is no write to the array, nor any incrementing of the address register at the end of the operation.

An address modifier word, which in the embodiment of Figure 5C has bits 31 and 30 being set to 0 and 1 , respectively, is an extended form of an address set word that conditionally updates the address register.

Bits 23 to 16 of the bitstream word specify an 8-bit address that selects one of (up to) 256 bits in the control register. The selected bit from the control register is then compared to bit 26 in the bitstream word. If the two bits are the same, then the address register is modified in the same way as described above. If the two bits are different, then there is no change to the address register Accordingly, the present invention is capable of sending specific data to various locations in the reconfigurable component, which locations are not predetermined by addresses contained in the configurations found in the system memory, but rather addresses determined by the control register. Moreover, the present invention is also capable of sending data to an address that will subsequently be overwritten, or to an invalid (i.e. out of range) address, such that the data is effectively ignored and does not contribute to the final configuration of the reconfigurable component.

As will be appreciated, whilst the embodiment described above comprise 32 bit words, any number of different sizes can be possible within scope of the invention. Moreover, any other control schemes and bit configurations can be possible within the scope of the present invention.

The above described sequence of operations has the effect of allowing the actions of the control processor (i.e. copying the mode selection data to the control register, and the configuration blocks to the configuration interface) to be independent from the ultimate operating mode of the system. The setting of the configuration state of the reconfigurable component is achieved by interaction of the configuration interface and the control register, without further reference to the control processor.

Therefore, using the present invention, it is possible to achieve the objective of separating the development of the software for the control processor from the development of the configuration data for the reconfigurable component.

Moreover, because the data passed from the memory to the configuration interface is independent of the state of the control register, it can be fetched without reference to the control register. In the above-described embodiment, it is assumed that the control processor manages this transfer. It is however also possible to use a separate DMA (direct memory access) controller to do so. In both situations, the configuration interface need only act as a slave on the memory bus. It therefore does not need to be a master, as it does not need to modify the sequence of addresses to the memory. It is possible to reduce the overall size of the configuration data by sharing data where appropriate. An example of this is shown in Figure 6. In Figure 6, two operating modes (i.e. A and B) exist for a system, each with its own configuration for the reconfigurable component, and the configurations share some common logic. Each configuration can then be divided into two sections; one for the common logic and one for the configuration-specific logic. The configuration memory for the common logic can then be shared between the two operating modes. In this example, Figure 6A represents the memory needed to store two distinct configuration using a system in accordance with the prior art, and Figure 6B represents the memory needed to store two configurations using a system in accordance with the present invention.

As will be appreciated from the above, the control registers of the first two embodiments could be substituted with any other form of memory unit.

Claims

1. A configuration interface for a programmable logic device, the configuration interface comprising:

configuration data means arranged to receive and store configuration data;

2. The configuration interface of claim 1 , wherein the memory unit is a control register.

3. The configuration interface of claim 1 , wherein the memory unit is part of a mode selection Random Access Memory (ROM).

4. The configuration interface of any of the preceding claims, wherein the configuration data, the address data, the address data modification instructions are data words of a predetermined number of bits.

5. The configuration interface of claim 4, wherein the predetermined number of bits is 32.

6. A system for configuring a programmable logic device, the system comprising:

a control processor;

a mode selection unit;

a configurable component;

a memory unit;

a configuration interface in accordance with any of claims 1 to 5.

7. The system of claim 6, wherein the memory unit forms part of the mode selection unit.

8. The system of claim 6, wherein the memory unit is a control register.

9. The system of claim 8, wherein the control register is arranged to interface with the control processor and the configuration interface.

10. A method of configuring a programmable logic device including the steps of:

receiving and storing configuration data;

receiving replacement address data from a memory unit; and

1 1 . The method of claim 10, wherein the configuration data, the address data, the address data modification instructions are data words of a predetermined number of bits.

12. The method of claim 1 1 , wherein the predetermined number of bits is 32.