WO2011149118A1 - Forming method and crystallization method for an oxide semiconductor thin film using a liquid-phase process, and a method for forming semiconductor elements by using the same - Google Patents

Forming method and crystallization method for an oxide semiconductor thin film using a liquid-phase process, and a method for forming semiconductor elements by using the same Download PDF

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WO2011149118A1
WO2011149118A1 PCT/KR2010/003263 KR2010003263W WO2011149118A1 WO 2011149118 A1 WO2011149118 A1 WO 2011149118A1 KR 2010003263 W KR2010003263 W KR 2010003263W WO 2011149118 A1 WO2011149118 A1 WO 2011149118A1
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thin film
oxide semiconductor
semiconductor thin
substrate
heat treatment
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PCT/KR2010/003263
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French (fr)
Korean (ko)
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김현재
이근우
허건의
정태훈
신현수
김건희
안병두
김경호
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연세대학교 산학협력단
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Publication of WO2011149118A1 publication Critical patent/WO2011149118A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO

Definitions

  • Embodiments of the present invention relate to a method of forming a semiconductor thin film using a liquid phase process, a crystallization method, and a method of forming a semiconductor device using the same.
  • embodiments of the present invention relate to a method of forming an oxide semiconductor thin film using a liquid phase process and a crystallization method thereof, a flash memory device using the liquid phase process and a method of forming the same, and an oxide semiconductor transistor using a liquid phase process and a method of forming the same.
  • the flash memory device using a liquid phase process and a method of forming the same according to an embodiment of the present invention are derived from a study performed as a part of a national laboratory project of the Ministry of Education, Science and Technology and the Korea Science Foundation. -0878, Title: Development of SOLUTION BASED SI (SBS) thin film and ALL SOLUTION BASED (ASB) TFT technology for next generation display].
  • SBS SOLUTION BASED SI
  • ASB ALL SOLUTION BASED
  • oxide thin films are useful for displays and semiconductor devices.
  • ZnO zinc oxide
  • ZnO is a group II-VI direct transition semiconductor, having a high band gap of 3.37 eV, transparent in the visible region, and having an exciton binding energy of 60 meV, which is widely used as an optical device ⁇ D.
  • ZnO zinc oxide
  • Zinc oxide exhibits n-type characteristics by native defects such as chipped zinc and oxygen vacancies, and can change electrical properties from 10-2 to 1010 ⁇ cm depending on process conditions.
  • the electron concentration can be further increased to be used as a transparent electrode, and doped with Group III or doped.
  • dopants include group III gallium (Ga), aluminum (Al) or indium (In), and the doped material is zinc gallium oxide (GZO) ⁇ Quan-Bao et al. "Structural, electrical, and optical properties of transparent conductive ZnO: Ga films prepared by DC reactive magnetron sputtering" Journal of Crystal Growth, 304, 64 (2007) ⁇ , aluminum zinc oxide (AZO) ⁇ Byeong-Yun Oh et al. "Properties of transparent conductive
  • ZnO Al films prepared by co-sputtering "Journal of Crystal Growth, Volume 274, 453, (2005) ⁇ , Indium Zinc Oxide (IZO) ⁇ EJ Luna-Arredondo et al.” Indium-doped ZnO thin films deposited by the solgel technique ”Thin Solid Films, 490, 132 (2005). These transparent electrodes are in the spotlight as a substitute for indium tin oxide (ITO), which is widely used in electronic devices.
  • ITO indium tin oxide
  • the transparency of the zinc oxide enables transparent transistors and is used as the transistor active layer of display devices due to the high mobility. If the zinc oxide is bulk, it has a good mobility of about 200 cm2 / Vs ⁇ D. C. Look et al. "Electrical properties of bulk ZnO" Solid State Commun. 105, 399 (1998) ⁇ . In addition, zinc compounds have ionic bonds, which make them single crystals compared to silicon (Si).
  • Indium-gallium-zinc oxide Indium-gallium-zinc oxide (IGZO; In-Ga-ZnO), indium zinc oxide (IZO; In-ZnO), tin-zinc oxide (SZO; Sn-ZnO), tin-gallium-zinc oxide (SGZO; Sn -Ga-ZnO), indium-tin-zinc oxide (ISZO; In-Sn-ZnO), thallium-zinc oxide (TZO; Tl-ZnO), thallium-gallium-zinc oxide (TGZO; Tl-Ga-ZnO)
  • a substance having an orbital of 5s or more having a larger ion radius than zinc is added to form an alloy with the
  • At least one or two or more oxidized compounds selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds are transparent by a sol-gel method and a heat treatment process using a liquid phase process.
  • Another embodiment of the present invention is a method of manufacturing a flash memory device capable of forming a channel region at a low temperature using a liquid phase process, easy implementation of a 3D stacked cell, and sufficient application of a glass or plastic substrate, and a flash memory device thereby. To provide.
  • Another embodiment of the present invention to provide a method for manufacturing an oxide semiconductor thin film and the oxide thin film transistor using a liquid phase process.
  • Oxide semiconductor thin film crystallization method comprises the steps of (a) forming an insulating film on the substrate; (b) depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film; (c) drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d) drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And (e) drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
  • the insulating film may be formed of a silicon oxide film or a nitride film.
  • the method may further include performing plasma or solution treatment to improve stable bonding between the substrate and the oxide compound sol.
  • the oxide compound sol in the step (b), may be deposited using spin coating or inkjet printing.
  • the step (b) may further comprise the step of performing the sol-gel process of step (c) at least once.
  • the step (e) using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer may further comprise the step of performing again.
  • the crystallization of the transparent crystalline oxide semiconductor thin film may be controlled by controlling the molar ratio of at least one oxide selected from zinc, indium, gallium, tin and tantalum compounds.
  • the first heat treatment process is to evaporate the solvents and stabilizers contained in the oxidized compound sol and to assist in chemical decomposition of each compound. It is carried out to change, it can be carried out for 1 hour in the 250 °C to 450 °C temperature range.
  • the second heat treatment process is performed so that the organic components included in the compound are all evaporated to form an oxide semiconductor, and the second heat treatment process is performed such that the temperature is changed according to the treatment time. It may be performed for 24 hours in the temperature range of °C to 800 °C.
  • the third heat treatment is performed to change the temperature according to the treatment time, wherein the film of the amorphous phase is made of a transparent nanocrystalline film through the third heat treatment process, and the 900 °C to 1100 It can be performed for 24 hours in the temperature range °C.
  • Oxide semiconductor thin film crystallization method (a ') forming an insulating film on a substrate; (b ') depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film; (c ') drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d ') repeating the sol-gel process of steps (b') and (c ') at least once on the oxidized compound gel; (e ') drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And (f ') drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
  • oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds
  • Oxide semiconductor thin film crystallization method (a ") forming an insulating film on a substrate; (b") on the insulating film zinc compound, indium compound, gallium compound, tin compound and tantalum compound Depositing at least one oxide compound sol selected from the group consisting of; (c ”) drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d”) drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film.
  • step (e ) drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film; and (f") the steps (b ”) to on the transparent crystalline oxide semiconductor thin film.
  • step (e ′′) may be performed using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer.
  • hydrophilicity and hydrophobicity may be achieved by plasma or solution treatment to improve stable bonding between the first transparent crystalline oxide semiconductor thin film and the oxide compound sol in step (b ′′). It may further comprise the step of forming.
  • a method of forming a flash memory device includes forming a channel layer, a floating gate, and a control gate on a substrate, wherein the channel layer is formed by coating a solution-based semiconductor oxide material. do.
  • the channel layer may be formed by coating a solution-based indium gallium zinc oxide (IGZO) material.
  • IGZO indium gallium zinc oxide
  • the channel layer may be formed by coating a material selected from solution based ZnO, IZO and ZTO.
  • the floating gate may be formed by coating a solution-based carbon nanotube material.
  • the carbon nanotube material may include at least one of SWNT, MWNT, graphene, and fullerene.
  • the floating gate may be formed by coating a material selected from solution-based IGZO, ZnO, IZO and ZTO.
  • the channel layer may be formed using a process selected from spin coating, nano imprinting, and inkjet printing.
  • a flash memory device manufactured by the manufacturing method is a bottom control gate type device, and after forming the control gate and the floating gate on the substrate, the channel layer is formed. can do.
  • the flash memory device manufactured by the manufacturing method is a top control gate type device, and after forming the channel layer on the substrate, the floating gate and the control gate may be formed. have.
  • the substrate may be a glass substrate or a plastic substrate such as PET. As another embodiment, it may be a silicon substrate.
  • a flash memory device includes a substrate and a channel layer, a floating gate, and a control gate formed on the substrate, the channel layer being formed of a poly crystalline layer formed by coating a solution-based IGZO material. It is characterized by consisting of IGZO.
  • the floating gate may have a layer structure made of carbon nanotubes.
  • the floating gate may be a layer structure made of a material selected from IGZO, ZnO, IZO, and ZTO.
  • a bottom control gate type flash memory device may include a control gate disposed on the substrate, the floating gate disposed on the control gate, and the channel layer disposed on the floating gate.
  • the flash memory device may be a top control gate type flash memory device in which a channel layer is disposed on the substrate, the floating gate is disposed on the channel layer, and the control gate is disposed on the floating gate.
  • a flash memory device forming method includes forming a first floating gate layer and a first control gate layer on a substrate; And forming an upper channel layer, a second floating gate layer, and a second control gate layer on the first gate layer, wherein the upper channel layer is formed by coating a solution-based semiconductor oxide material. .
  • the upper channel layer may be formed by coating a material selected from a solution-based IGZO, ZnO, IZO and ZTO.
  • the substrate may be made of a silicon semiconductor.
  • the first floating gate may be formed of a polysilicon material.
  • the method may further include forming a lower channel layer by coating a material selected from solution-based IGZO, ZnO, IZO, and ZTO on the substrate before forming the first floating gate.
  • the second floating gate may be formed by coating a solution-based carbon nanotube material.
  • the second floating gate may be formed by coating a material selected from solution-based IGZO, ZnO, IZO, and ZTO.
  • the upper channel layer may be formed using a process selected from spin coating, nano imprinting, and inkjet printing.
  • a flash memory device may include: a first memory cell unit including a first floating gate and a first control gate formed on a substrate; And a second memory cell portion including an upper channel layer, a second floating gate layer, and a second control gate layer formed on the first memory cell portion, wherein the upper channel layer is formed of a polycrystalline crystal formed by coating a solution-based IGZO material. It is made of IGZO.
  • the substrate may be made of a silicon semiconductor.
  • the first floating gate may be made of a polysilicon material.
  • the first memory cell part may further include a lower channel layer formed on the substrate and made of a material selected from IGZO, ZnO, IZO, and ZTO.
  • the second floating gate may have a layer structure made of carbon nanotubes.
  • the second floating gate may be a layer structure made of a material selected from IGZO, ZnO, IZO, and ZTO.
  • Oxide semiconductor thin film formation method comprises the steps of forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on a substrate; And forming an oxide semiconductor thin film by heat treatment by irradiating a laser beam on the aqueous oxide semiconductor solution, and when irradiating the laser beam, different characteristics are formed on the oxide semiconductor thin film by using a half-tone mask. At least two areas having a feature to collectively form.
  • the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
  • the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
  • a method of forming an aqueous solution of an oxide semiconductor on the substrate may be any one of screen printing, spin coating, or ink-jet. Can be.
  • An oxide thin film transistor forming method comprises the steps of forming a gate electrode on a substrate; Forming a gate insulating layer on the gate electrode; And forming an oxide semiconductor thin film by heat treatment after forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on the gate insulating layer, wherein a half-tone mask is applied when the laser beam is irradiated. At least two regions having different characteristics may be collectively formed on the oxide semiconductor thin film.
  • At least one of the at least two regions may be a region for use as a source and a drain electrode.
  • At least one of the at least two regions may be a channel region.
  • the laser beam may be irradiated with the largest energy density in the region for use as the source and drain electrodes of the at least two regions.
  • the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
  • the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
  • any one method selected from among screen printing, spin coating, and ink-jet methods may be used.
  • a method of forming an oxide thin film transistor including: forming an oxide semiconductor thin film by heat treatment after forming an aqueous oxide semiconductor solution by a liquid phase manufacturing process on a substrate; Forming a gate insulating layer on the oxide semiconductor thin film; And forming a gate electrode on the gate insulating layer, wherein when the laser beam is irradiated, at least two regions having different characteristics are collectively formed on the oxide semiconductor thin film by using a half-tone mask. Characterized in that.
  • At least one of the at least two regions may be a region for use as a source and a drain electrode.
  • At least one of the at least two regions may be a channel region.
  • the energy density of the laser beam irradiated to the area for use as the source and drain electrodes of the at least two areas may be the largest.
  • the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
  • the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
  • any one method selected from among screen printing, spin coating, and ink-jet method may be used as a method of forming the oxide semiconductor aqueous solution.
  • the crystallization method of the oxide semiconductor thin film using the liquid manufacturing base at least one selected from the group consisting of a liquid semiconductor based oxide semiconductor, for example, zinc compound, indium compound, gallium compound, tin compound and tantalum compound
  • a liquid semiconductor based oxide semiconductor for example, zinc compound, indium compound, gallium compound, tin compound and tantalum compound
  • the liquid-based oxide semiconductor thin film manufactured by the present invention provides a transparent oxide film required for a transistor liquid crystal display, an organic electroluminescent display, a solar cell, an image sensor, etc., in place of an oxide semiconductor thin film using a sputtering deposition method currently used.
  • a transparent oxide film required for a transistor liquid crystal display, an organic electroluminescent display, a solar cell, an image sensor, etc. in place of an oxide semiconductor thin film using a sputtering deposition method currently used.
  • the channel region of a flash memory cell by applying a solution-based semiconductor oxide material by spin coating, etc., the channel region is easily formed in a relatively simple process at low temperature.
  • the 3D stacked cell can be easily implemented, and the flash memory cell can be stably implemented on a glass or flexible substrate.
  • a floating gate by coating a solution-based semiconductor oxide or a solution-based carbon nanotube material, it is possible not only to keep the manufacturing process temperature of the flash memory cell lower but also to solve the inter-cell interference problem. .
  • the laser since the heat treatment using a laser (Laser) during the formation of the oxide semiconductor thin film can directly block the heat transfer to the substrate, the laser (Laser The strong energy of) has the advantage that it is easy to secure the temperature required to form a thin film.
  • FIGS. 1A to 1D are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a first embodiment of the present invention.
  • FIG. 2 is a graph showing a change in transmittance according to a wavelength of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
  • FIG. 3 is a graph and a planar scanning electron micrograph showing the results of X-ray diffraction of the amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • FIG. 4 is a graph showing X-ray diffraction results of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention and nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature.
  • FIG. 5 is a graph showing a change in transmittance according to wavelength of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
  • FIG. 6 is a photograph of an amorphous oxide semiconductor thin film and a nanocrystalline oxide semiconductor thin film applied to a first embodiment of the present invention.
  • FIG. 7 is a planar scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention.
  • FIG. 8 is a cross-sectional scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • FIG. 9 is an atomic beam micrograph of a subsequently heat-treated nanocrystalline oxide semiconductor thin film of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • 10A to 10F are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention.
  • FIG. 11 is a graph illustrating a change in thickness of an oxide semiconductor thin film according to the number of repetitions of sol-gel deposition and sol-gel process of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention.
  • FIG. 12 is a planar scanning microscope photograph according to the change in thickness of the nanocrystalline oxide semiconductor thin film applied in the second embodiment of the present invention.
  • FIG. 13 is a cross-sectional SEM image according to a change in thickness of the nanocrystalline oxide semiconductor thin film applied to the second embodiment of the present invention.
  • FIG. 14 is a graph showing X-ray diffraction results of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment according to the thickness of the amorphous oxide semiconductor thin film applied to the second embodiment of the present invention.
  • FIG. 15 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • 16 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • 17 is a cross-sectional scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxidized compound sol applied in the embodiment of the present invention.
  • FIG. 18 is a graph showing X-ray diffraction results of nanocrystalline oxide semiconductor thin films after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • FIG. 19 is a graph for explaining a comparison of relative peak intensities of (008) main growth directions of a nanocrystalline oxide semiconductor thin film by subsequent heat treatment of an amorphous oxide semiconductor thin film according to the molar ratio of an oxide compound sol applied to an embodiment of the present invention. .
  • 20A to 20E are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a third embodiment of the present invention.
  • 21 is a cross-sectional view of a flash memory device according to an embodiment of the present invention.
  • FIG. 22 is a cross-sectional view of a flash memory device according to another embodiment of the present invention.
  • FIG. 23 is a cross-sectional view illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.
  • FIG. 24 is a cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment of the present invention.
  • 25 is a cross-sectional view of a flash memory device having a 3D stacked cell structure according to an embodiment of the present invention.
  • 26 is a cross-sectional view of a flash memory device having a 3D stacked cell structure according to another embodiment of the present invention.
  • 27A and 27B are cross-sectional views illustrating a method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention.
  • 28A to 28E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a bottom gate method.
  • 29A to 29E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a top gate method.
  • FIGS. 30 and 31 are plan views and cross-sectional views illustrating a backplane structure of a liquid crystal display device to which a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention is applied.
  • TFT thin-film transistor
  • a-Si amorphous silicon
  • LTPS low temperature polycrystalline silicon
  • organic thin film transistor easy access to the transparent display using the transparent properties of the thin film is possible.
  • the carrier mobility of the zinc oxide is about 200 cm 2 / V ⁇ s ⁇ reference; DC Look et al. , “Electrical properties of bulk ZnO,” Solid State Commun., 105, 399 (1998) ⁇ Using an oxidizing compound composed of amorphous indium-gallium-zinc compound higher than 100 cm 2 / V ⁇ s of low-temperature polycrystalline silicon as an active layer
  • the mobility of the thin film transistor TFT is about 1 to 120 cm 2 / V ⁇ s ⁇ reference; HN. Lee et al., J. Soc. Inf. Display, 16, 265 (2008) ⁇ , superior to the characteristics of amorphous silicon thin film transistors, and comparable to polycrystalline silicon thin film transistors.
  • Amorphous Indium-Gallium-Zinc Oxide (a-IGZO), which is composed of amorphous indium-gallium-zinc compounds, has been flexible in LG Electronic and SAIT since it was first proposed by Hideo Hosono Research Group of Tokyo University of Technology. We are trying to develop organic light emitting diode panel.
  • the transparent oxide film is optimally used as a driving element of a flexible organic light emitting diode display.
  • a vacuum deposition method such as sputtering and pulsed laser deposition (PDL) is widely used.
  • PDL pulsed laser deposition
  • high temperature crystallization is required in the existing sputtering process, and the application of the oxide semiconductor thin film made of indium-gallium-zinc compound using the sputter deposition method which is currently commercially available is limited to its amorphous phase. This is because the crystallization requires heat treatment at a high temperature of about 1000 degrees or more.
  • an embodiment of the present invention provides a crystallization method of an oxide semiconductor thin film based on a liquid phase process.
  • FIGS. 1A to 1D are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a first embodiment of the present invention.
  • an insulating film 110 made of, for example, a silicon oxide film or a nitride film is formed on a substrate 100 for example, a zinc compound, an indium compound, a gallium compound, a tin compound, and the like are formed on the insulating film 110.
  • At least one oxide compound sol (eg, indium-gallium-zinc sol, etc.) 120 selected from the group consisting of tantalum compounds is deposited.
  • the oxide sol 120 may be deposited using, for example, spin coating or inkjet printing.
  • the insulating film 110 on the substrate 100 in order to improve the stable bonding of the substrate 100 and the oxide compound sol 120, for example, by performing a plasma (Plasma) or solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
  • a plasma Pasma
  • solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
  • an oxide compound sol 120 is dried and heated through a first heat treatment process to form an oxide compound gel 130.
  • the first heat treatment process serves to evaporate the solvents and stabilizers included in the oxide compound sol 120 and to help chemically decompose each compound.
  • the first heat treatment process is preferably performed so that the temperature is changed according to the treatment time, and the solvent and stabilizers are in the range of about 250 ° C. to 450 ° C. (preferably, about 350 ° C.). Preferably for about 1 hour or less.
  • the oxidized compound gel 130 is dried and heated through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film 140.
  • the second heat treatment process serves to make the organic components included in the compound evaporate to the oxide semiconductor.
  • the second heat treatment process is preferably carried out to change the temperature according to the treatment time, about 600 °C to 800 °C range (preferably, about 700 °C) or less temperature that the organic components are all evaporated It is preferable to carry out for 24 hours or less.
  • the opaque amorphous semiconductor thin film 140 is dried and heated through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film 150.
  • the third heat treatment process serves to make the amorphous phase film made of a transparent nanocrystalline film.
  • the third heat treatment process is preferably performed to change the temperature according to the treatment time, it is preferable to perform for about 24 hours or less in the range of about 900 °C to 1100 °C (preferably, about 1000 °C).
  • the first to third heat treatment processes include, for example, a heat treatment process in a hot plate, a heat treatment process in a crucible for a long time, and a heat treatment in a rapid thermal annealing (RTA) to rapidly change the temperature. It is preferable to use any one of the heat treatment process selected from the process, or the process of heat treatment in the pulsed rapid heat treatment (Pulsed RTA).
  • RTA rapid thermal annealing
  • FIG. 2 is a graph showing a change in transmittance according to a wavelength of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
  • an insulating film 110 (see FIG. 1A) deposited on a glass substrate 100 (see FIG. 1A), that is, a silicon oxide film (a) and an oxide compound gel (eg, indium-gallium-zinc gel) (B) (130, FIG. 1b) shows the transmittance according to the wavelength of the thin film (b), that is, the amorphous oxide semiconductor thin film (140, see FIG. 1c) heat-treated at about 275 °C, the heat-treated thin film (b) You can see that is translucent.
  • oxide compound gel eg, indium-gallium-zinc gel
  • FIG. 3 is a graph and a planar scanning electron micrograph showing the results of X-ray diffraction of the amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • the oxidized compound gel eg, indium-gallium-zinc gel
  • FIG. 1C after drying the oxidized compound gel (eg, indium-gallium-zinc gel) 120 (see FIG. 1B) and heat-treated at about 275 ° C., that is, an amorphous oxide semiconductor thin film 140 (see FIG. 1C) X-ray diffraction results of the amorphous phase of the thin film without a crystal peak, it can be confirmed that no grains can be found in the scanning electron micrograph inserted therein.
  • the oxidized compound gel eg, indium-gallium-zinc gel
  • FIG. 4 is a graph showing X-ray diffraction results of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention and nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature.
  • the temperature was (b) 300 ° C., (c) 350 ° C., (d) 400 ° C., and (e) 450 ° C. and heat-treated at atmospheric pressure for about 1 hour.
  • the indium-gallium-zinc oxide compound semiconductor thin film (N-MA) at a heat treatment temperature of about 300 ° C. or more except for the (a) amorphous oxide semiconductor thin film heat-treated at about 275 ° C. a peak due to crystal grains is shown.
  • FIG. 5 is a graph showing a change in transmittance according to wavelength of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
  • an insulating film 110 (see FIG. 1A) deposited on a glass substrate 100 (see FIG. 1A), that is, a silicon oxide film (a) and an amorphous indium-gallium-zinc oxide compound semiconductor thin film (b) That is, the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film (C-bar) according to the subsequent heat treatment temperature of the amorphous oxide semiconductor thin film 140 (see FIG.
  • the heat treatment temperature is (C) 300 °C, (D) 350 °C, (E) 400 °C, (bar) 450 °C, heat treatment at atmospheric pressure for about 1 hour.
  • the transmittance is greatly improved at a heat treatment of about 300 ° C. or higher, and the transmittance is also improved as the heat treatment temperature is increased. .
  • FIG. 6 is a photograph of an amorphous oxide semiconductor thin film and a nanocrystalline oxide semiconductor thin film applied to a first embodiment of the present invention.
  • an amorphous indium-gallium-zinc oxide thin film i
  • a nanocrystalline indium-gallium-zinc oxide semiconductor thin film heat treated at about 450 ° C. with an amorphous oxide semiconductor thin film 140 (see FIG. 1C).
  • B In other words, as a photograph of the transparent crystalline oxide semiconductor thin film 150 (refer to FIG. 1D), a difference in transmittance with or without crystallization can be seen.
  • FIG. 7 is a planar scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention.
  • an amorphous indium-gallium-zinc oxide semiconductor thin film that is, a nanocrystalline indium-gallium-zinc oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film 140 (see FIG. 1C) That is, the planar scanning electron micrograph of the transparent crystalline oxide semiconductor thin film 150 (refer FIG. 1D),
  • the heat-treatment temperature is (a) 300 degreeC, (b) 350 degreeC, (c) 400 degreeC, (d) It was 450 ° C and heat-treated at atmospheric pressure for about 1 hour.
  • the size of the nano-crystals increases by several tens of nm, and the shape of the crystals is also clear.
  • FIG. 8 is a cross-sectional scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • an amorphous indium-gallium-zinc oxide semiconductor thin film that is, a nanocrystalline indium-gallium-zinc oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film 140 (see FIG. 1C) That is, the cross-sectional scanning electron micrograph of the transparent crystalline oxide semiconductor thin film 150 (refer FIG. 1D),
  • the heat processing temperature is (A) 300 degreeC, (B) 350 degreeC, (C) 400 degreeC, (D) It was 450 ° C and heat-treated at atmospheric pressure for about 1 hour.
  • FIG. 9 is an atomic beam micrograph of a subsequently heat-treated nanocrystalline oxide semiconductor thin film of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
  • an amorphous indium-gallium-zinc oxide semiconductor thin film that is, an amorphous crystalline indium-gallium-zinc oxide semiconductor thin film that is subsequently heat treated to about 450 ° C. That is, as an atomic beam micrograph of the transparent crystalline oxide semiconductor thin film 150 (see FIG. 1D), the surface roughness of the amorphous indium-gallium-zinc oxide compound semiconductor thin film conventionally pulsed laser deposited with a roughness of about 1.2 nm. Compared with the improved characteristics.
  • FIGS. 10A to 10F are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention, and a liquid phase based oxide (eg, indium-gallium-zinc, etc.) semiconductor thin film An embodiment for increasing the thickness of.
  • a liquid phase based oxide eg, indium-gallium-zinc, etc.
  • the insulating film 110 formed of, for example, a silicon oxide film or a nitride film is formed on the substrate 100, for example, a zinc compound, an indium compound, a gallium compound, a tin compound, and the like are formed on the insulating film 110.
  • At least one oxide compound sol (eg, indium-gallium-zinc sol, etc.) 120 selected from the group consisting of tantalum compounds is deposited.
  • the oxide compound sol 120 is preferably deposited using, for example, spin coating or inkjet printing.
  • the insulating film 110 on the substrate 100 in order to improve the stable bonding of the substrate 100 and the oxide compound sol 120, for example, by performing a plasma (Plasma) or a solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
  • a plasma Pasma
  • a solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
  • the oxide sol 120 is dried and heated through a first heat treatment process to form an oxide compound gel 130.
  • the first heat treatment process serves to evaporate the solvents and stabilizers included in the oxide compound sol 120 and to help chemically decompose each compound.
  • the first heat treatment process is preferably performed so that the temperature is changed according to the treatment time, and the solvent and stabilizers are in the range of about 250 ° C. to 450 ° C. (preferably, about 350 ° C.). Preferably for about 1 hour or less.
  • the sol (eg, indium-gallium-zinc sol, etc.) 120 ′ is deposited again using, for example, spin coating or inkjet printing.
  • the oxide sol 120 ′ formed on the oxide gel 130 is again subjected to the aforementioned first heat treatment process to dry and heat the oxide sol 120 ′. 130 ').
  • the oxide gels 130 and 130 ′ are dried and heated through the above second heat treatment process to be about twice as thick as the opaque amorphous oxide semiconductor thin film 140 of the first embodiment.
  • An opaque amorphous oxide semiconductor thin film 140 ' is formed.
  • the opaque amorphous semiconductor thin film 140 ′ is dried and heated through the third heat treatment process to form a thick transparent crystalline oxide semiconductor thin film 150 ′.
  • FIG. 11 is a graph illustrating a change in thickness of an oxide semiconductor thin film according to the number of repetitions of sol-gel deposition and sol-gel process of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention.
  • an oxide compound eg, indium-gallium-zinc, etc.
  • the thickness of the thin film is proportional to the number of repetitions of the sol-gel process after the thickness of about 100 nm is deposited in one deposition. You can see the increase.
  • the nanocrystalline oxide semiconductor thin film 150 after subsequent heat treatment at about 450 ° C. according to the number of repetitions of the oxidizing compound (eg, indium-gallium-zinc, etc.) sol-gel process and the thickness thereof applied in the second embodiment of the present invention (150) 10F), the thickness of which is (a) 100 nm, (b) 140 nm, (c) 170 nm, and (d) 300 nm.
  • the thickness increases, the size of the nanocrystals tends to increase little by little.
  • FIG. 13 is a cross-sectional SEM image according to a change in thickness of the nanocrystalline oxide semiconductor thin film applied to the second embodiment of the present invention.
  • the nanocrystalline oxide semiconductor thin film 150 after subsequent heat treatment at about 450 ° C. according to the number of repetitions of the oxidizing compound (eg, indium-gallium-zinc, etc.) sol-gel process and the thickness thereof applied in the second embodiment of the present invention (150) 10F), the thickness of which is (a) 100 nm, (b) 170 nm, and (c) 300 nm. That is, the thickness of the nanocrystalline oxide semiconductor thin film 150 ′ may be effectively increased by repeating the sol-gel process, and it may be confirmed that no interface exists between the stacked film and the film due to continuous deposition. In addition, in accordance with the results of the planar scanning electron microscope, as the thickness of the nanocrystalline oxide semiconductor thin film 150 ′ increased, the grain size slightly increased.
  • the oxidizing compound eg, indium-gallium-zinc, etc.
  • FIG. 14 is a graph showing X-ray diffraction results of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment according to the thickness of the amorphous oxide semiconductor thin film applied to the second embodiment of the present invention.
  • an amorphous indium-gallium-zinc oxide compound semiconductor thin film i.e., a nanocrystalline oxide semiconductor after subsequent heat treatment at about 450 ° C. depending on the thickness of the amorphous oxide semiconductor thin film 140 '(see FIG. 10E)).
  • It is the X-ray diffraction result of thin film (b ⁇ ma) (150 ', see FIG. 10F).
  • the thickness of the film is (a) 100 nm, (b) 100 nm, (c) 140 nm, (d) 170 nm, and (e) 300 nm.
  • the grain peak tends to increase as the thickness of the film increases, which tends to match the result of the scanning electron microscope.
  • FIG. 15 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol 120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B) applied to an embodiment of the present invention is shown.
  • Nanocrystalline indium-gallium-zinc oxide compound thin film that is, amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E and 20D) after subsequent heat treatment at about 450 ° C.
  • the grain size of the film after the heat treatment of about 450 ° C. is about the same, but it can be seen that the void indicated by the arrow appears when the indium molar ratio is 2 or more.
  • FIG. 16 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol 120,120 ', 120 ", FIG. 1A, FIG. 10A, 10C, and 20B
  • the amorphous indium-gallium-zinc oxide compound thin film that is, the amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS.
  • FIG. 17 is a cross-sectional scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxidized compound sol applied in the embodiment of the present invention.
  • the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol 120,120 ', 120 ", FIG. 1A, FIG. 10A, 10C, and 20B) applied to an embodiment of the present invention is shown.
  • Nanocrystalline indium-gallium-zinc oxide after subsequent heat treatment of the amorphous indium-gallium-zinc oxide compound semiconductor thin film that is, the amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E and 20D).
  • FIG. 18 is a graph showing X-ray diffraction results of nanocrystalline oxide semiconductor thin films after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
  • the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol 120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B
  • Nanocrystalline indium-gallium-zinc oxide compound thin film that is, amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS.
  • the intensity of X-ray peaks of the nanocrystalline oxide semiconductor thin films 150, 150 ', and 150 "crystallized through about 450 ° C first and subsequent heat treatments of about 700 ° C is shown as the indium molar ratio increases. The intensity decreases, which means a decrease in crystallinity.
  • the main growth direction is changed from (008) to (100), and the indium-gallium-zinc oxide compound has different hexagonal structure gallium-zinc compound and cubic structure indium
  • the compound has a raised structure.
  • the grain growth of the hexagonal gallium-zinc compound interferes with the columnar growth structure, and the grain grows horizontally and inclined with the film. This is consistent with the photograph of the cross-sectional scanning electron microscope.
  • FIG. 19 is a graph for explaining a comparison of relative peak intensities of (008) main growth directions of a nanocrystalline oxide semiconductor thin film by subsequent heat treatment of an amorphous oxide semiconductor thin film according to the molar ratio of an oxide compound sol applied to an embodiment of the present invention.
  • the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol 120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B) applied to an embodiment of the present invention is shown.
  • Nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film according to the subsequent heat treatment of the amorphous indium-gallium-zinc oxide compound semiconductor thin film that is, the amorphous oxide semiconductor thin film 140, 140 ', 140 ", see FIGS. 1C, 10E and 20D
  • the heat treatment conditions at this time (a) is about 450 °C
  • the crystallinity of the nanocrystalline oxide semiconductor thin film 150, 150 ′, 150 ′′ is improved by the second subsequent heat treatment, and the crystallinity decreases as the indium molar ratio increases.
  • the experimental result of adjusting the molar ratio of indium in the indium-gallium-zinc oxide compound is shown, but not limited to this, the same result can be obtained for other oxide compounds.
  • 20A to 20E are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a third embodiment of the present invention, and a liquid phase based oxide (eg, indium-gallium-zinc, etc.) semiconductor thin film An embodiment for improving the characteristics and adjusting the thickness.
  • a liquid phase based oxide eg, indium-gallium-zinc, etc.
  • the transparent nanocrystals crystallized through the sol-gel process of the first embodiment described above on the insulating film 110.
  • the crystalline oxide semiconductor thin film 150 is formed.
  • hydrophilicity and hydrophobicity may be formed between the nanocrystalline oxide semiconductor thin film 150 and the oxidized compound sol 120 ′′, for example, by plasma or solution treatment, thereby improving stable bonding with the oxidized compound sol 120 ′′.
  • plasma or solution treatment thereby improving stable bonding with the oxidized compound sol 120 ′′.
  • an oxide compound sol 120 ′′ is dried and heated to form an oxide compound gel 130 ′ through the first heat treatment process applied to the first embodiment of the present invention.
  • the oxidized compound gel 130 ′′ is dried and heated through the second heat treatment process applied to the first embodiment of the present invention to form an opaque amorphous oxide semiconductor thin film 140 ′′.
  • the opaque amorphous semiconductor thin film 140 ′′ is dried and heated through a third heat treatment process applied to the first embodiment of the present invention, and the transparent nanocrystalline semiconductor thin film 150 is converted into a crystallized nucleus layer.
  • the thickened second transparent crystalline oxide semiconductor thin film 150 ′′ is formed.
  • the nanocrystalline semiconductor thin film 150 serves as a nucleus for crystal growth to improve the directivity and crystallinity of the upper opaque amorphous semiconductor thin film 140 ′′.
  • the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film may also function as a crystal growth nucleus for improving the orientation of the film and facilitating grain formation in the zinc compound oxide film series.
  • Amorphous or nano, fine, polycrystalline compound semiconductor thin film produced by the present invention which provides a crystallization technique, is, for example, a display device such as an organic light emitting diode (OLED) and a liquid crystal display (LCD), or a solar cell. Can be applied.
  • OLED organic light emitting diode
  • LCD liquid crystal display
  • the present invention high temperature crystallization is required in the existing sputtering process, while the liquid crystal manufacturing method enables crystallization at low temperature.
  • the application of the indium-gallium-zinc oxide compound semiconductor thin film using the sputter deposition method currently available is limited to the amorphous phase. This is because the crystallization requires heat treatment at a high temperature of about 1000 ° C. or higher.
  • the liquid crystal-based oxide compound semiconductor thin film is capable of crystallization at a relatively low temperature and provides crystallization of the crystalline oxide film having structural and optical properties improved compared to an amorphous phase.
  • the present invention is crystallized at a low temperature through the sol deposition of the oxide compound using spin coating, inkjet printing, etc., after the gel drying process and the formation of the amorphous thin film, the heat treatment of the amorphous semiconductor thin film To provide nano, fine, polycrystalline semiconductor thin film to provide improved transmittance and structural characteristics compared to the amorphous semiconductor thin film.
  • the flash memory device includes a charge storage unit called a floating gate between dielectric layers of a conventional MOS structure, and has a characteristic of storing data even when a power supply is cut off.
  • a charge storage unit called a floating gate between dielectric layers of a conventional MOS structure
  • polysilicon is mainly used as a floating gate for storing charge, but due to the difficulty of improving the integration density due to interference between devices, a charge trap type memory device is recently used to replace polysilicon.
  • flash memory devices use silicon semiconductors as channel regions through which current flows. When the channel region of the silicon semiconductor is applied, ion implantation and heat treatment processes for channel doping, source-drain doping, and well doping are performed.
  • the performance of a flash memory device is determined by the data storage capability and the stability and speed of write and read operations of the data.
  • the need for high integration is increasing. To this end, efforts have been made to reduce the size of memory devices, but there is a need for a method for preventing deterioration of device characteristics such as short channel effects due to device shrinkage.
  • a possibility of implementing a 3D (3-dimensional) stacked cell in which a plurality of flash memory cells are vertically stacked is proposed.
  • the floating gate formation process is also preferably performed at lower temperatures than conventional polysilicon formation temperatures.
  • an embodiment of the present invention provides a flash memory forming method capable of low-temperature processing by applying a liquid phase process.
  • FIG. 21 is a cross-sectional view of a flash memory device according to an embodiment of the present invention.
  • FIG. 21 shows a 'bottom control gate type' flash memory cell in particular in which a gate structure (including a control gate and a floating gate) is disposed between the substrate and the channel region.
  • a gate structure including a control gate and a floating gate
  • a flash memory device 1000 may include a control gate 1030, an interdielectric layer 1040, a floating gate 1070, a tunneling insulating layer 1070, and a channel layer 108 formed on a substrate 1010. ).
  • a SiO 2 buffer layer 103 is formed between the substrate 1010 and the control gate 1030 to prevent the incorporation of impurities into the layer structure on the buffer layer 1030 and to improve the film quality of the layer structure on the buffer layer 103.
  • Source-drain electrodes 1100 and 1200 spaced apart from each other are disposed at both ends of the channel layer 108.
  • the channel layer 1080 is formed by coating a solution-based semiconductor oxide material, as described below. In particular, by coating a solution-based Indium Gallium Zinc Oxide (IGZO) on the tunneling insulating film 1070 using a simple low-temperature process such as spin coating, nano imprinting or inkjet printing. The channel layer 1080 can be easily obtained.
  • IGZO Indium Gallium Zinc Oxide
  • the channel layer 1080 is made of polycrystalline IGZO.
  • the polycrystalline IGZO has a high mobility semiconductor property, so that the channel is applied to the source-drain electrodes 1100 and 1200 and the control gate 1030 according to the application of the voltage. Operating current flows through layer 1080.
  • the channel layer 1080 of the polycrystalline IGZO acts as a channel of the transistor without any doping and does not require a separate impurity region (diffusion region or ion implantation region) for junction with the source-drain electrode.
  • a conventional silicon substrate may be used, but a flexible substrate such as a glass substrate or a flexible substrate such as polyethyleneterephthalate (PET) may be easily applied.
  • PET polyethyleneterephthalate
  • the channel layer 1080 may be formed at a low temperature by a coating process of a solution-based semiconductor oxide material, unlike a conventional silicon semiconductor, even if a substrate having a material, such as plastic or glass, which is weak to heat, the substrate is not damaged. Because it does not.
  • the flash memory cell structure according to the present embodiment may be embedded in a display such as an LCD or an OLED to implement a system on chip (SOC), which is advantageous for implementing a flexible memory device.
  • SOC system on chip
  • the control gate 1030 may be formed of a metal or an alloy such as MoW, W, Mo, AlNd, Ag, Cu, MoTa, Cr, or the like.
  • the interlayer insulating film 1040 is an insulating film disposed between the control gate 1030 and the floating gate 1050, and serves to transfer a voltage applied to the control gate 1030 to the floating gate 1050 through a coupling. . Therefore, it is preferable that the capacitance value of the interlayer insulating film 1040 is large. In addition, it is desirable to have an appropriate thickness in order to improve the retention characteristic, which is one of the main characteristics affecting the reliability of the memory cell.
  • the interlayer insulating film 1040 may use a double film structure of a nitride film and an oxide film.
  • the interlayer insulating film 1040 may have a double film structure of a SiNx film 1040a of about 15 nm and a SiO 2 film 1040b of about 10 nm.
  • the interlayer insulating film 1040 may use an ONO structure, a structure using only an oxide film, and a material or film structure such as Al 2 O 3 , HfO 2 , Zr / oxide / Zr, which are high-k materials. have.
  • a high dielectric constant oxide such as Al 2 O 3 may be used.
  • a high dielectric constant material such as SiO 2 , SiNx, Al 2 O 3 , HfO 2, or the like may be used.
  • the floating gate 1050 may be formed of a carbon nanotube layer.
  • the floating gate 1050 of the carbon nanotube layer structure is easily obtained by coating a solution-based CNT material in which carbon nanotubes (CNTs) are dispersed by a low temperature process such as spin coating, nano stamping, or inkjet printing. Can be.
  • CNTs carbon nanotubes
  • the CNT for the floating gate 1050 for example, single wall carbon nanotube (SWNT) or multiwall carbon nanotube (MWNT) can be used.
  • SWNT single wall carbon nanotube
  • MWNT multiwall carbon nanotube
  • the floating gate 1050 having the carbon nanotube layer structure can be manufactured relatively easily through a low temperature process as described below, the 3D stacked cell can be more easily implemented together with the channel layer 1070 of the polycrystalline IGZO described above. To be able.
  • the floating gate 1050 may be formed from a solution-based semiconductor oxide material. As described below, it is also possible to form a floating gate using a solution-based IGZO, or a solution-based ZnO, a solution-based IZO, a solution-based ZTO material, or the like. In this case, it is also possible to manufacture a floating gate by a low temperature process, which is advantageous for implementing a 3D stacked cell.
  • the source-drain electrodes 1100 and 1200 may be formed using, for example, IZO, Cu, Al, W, MoW, Ti, Ta, Cr, or Ag.
  • FIG. 22 is a cross-sectional view of a flash memory device 2000 according to another embodiment of the present invention.
  • a 'top control gate type' flash memory cell in which a gate structure is disposed over a substrate and a channel region is shown.
  • a SiO 2 buffer layer 2010 and a channel layer 2080 are formed on a substrate 2010, and a tunneling insulating film 2070, a floating gate 2050, an interlayer insulating film 2040, and control are formed thereon.
  • the gates 2030 are sequentially stacked.
  • Source-drain electrodes 2100 and 2200 are spaced apart from each other at both ends of the channel layer 2080.
  • the material and basic structure of each of the component parts 2030 to 2200, such as the channel layer and the floating gate, including the substrate 2010, are the same as in the above-described embodiment (Fig. 21).
  • the channel layer 2080 may be obtained by coating a solution-based IGZO material on the buffer layer 2020 using a simple low-temperature process such as spin coating, nano stamping or inkjet printing, and has a polycrystalline IGZO semiconductor layer structure.
  • the floating gate 2050 may be a layer structure of carbon nanotubes or a layer structure of IGZO, ZnO, IZO or ZTO, which may be formed by low temperature coating of a solution-based material. Therefore, like the above-described embodiment (FIG. 21), it is advantageous to manufacture the cell by a low temperature process and to the 3D stacked cell implementation.
  • 23A to 23F are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment of the present invention, and are related to fabrication of a flash memory device having a bottom control gate type structure.
  • the SiO 2 buffer layer 102 is formed on a plastic substrate 1010 such as silicon, glass, or PET.
  • the buffer layer 1020 serves to prevent impurities from being incorporated into the later stacked layers and to maintain the quality of subsequent layers in a good state.
  • the control gate 1030 is formed on the buffer layer 1020.
  • the control gate 103 may be formed by depositing a material such as MoW, W, Al, AlNd, Ag, Cu, MoTa, or Cr by sputtering.
  • an interlayer insulating film 1040 is formed on the control gate 1030.
  • the interlayer insulating film 1040 may be formed in a double layer structure of NO by sequentially forming the nitride film 1040a and the oxide film 1040b.
  • the interlayer insulating film 1040 is disposed between the control gate 1030 and the subsequent floating gate, and is preferably formed of a material having a large capacitance value for voltage coupling.
  • the interlayer insulating film 1040 is preferably formed to an appropriate thickness in order to improve the retention characteristics of the memory cell.
  • the interlayer insulating film 1040 may be formed of a nitride film 1040a of about 15 nm and an oxide film 1040b of about 10 nm.
  • the interlayer insulating film 1040 may be formed of only an oxide film, or the interlayer insulating film 1040 may be formed of an oxide film such as Al 2 O 3 or HfO, which is a high dielectric constant material.
  • the interlayer insulating film 1040 may be formed in a stacked film structure of Zr / oxide film / Zr.
  • a floating gate 1050 is formed on the interlayer insulating film 1040.
  • the floating gate 1050 may be formed by coating a solution-based carbon nanotube such as SWNT or MWNT that is well purified and dispersed on the interlayer insulating film 1040.
  • the solution-based carbon nanotube material may include graphene or fullerene.
  • Carbon nanotubes (CNTs) and dispersants may be added to deionized water to form solution-based carbon nanotube materials with uniform dispersion of CNTs.
  • the CNT content in the solution (dispersion) in which the CNTs are dispersed is not particularly limited, but CNTs may be included in the dispersion at, for example, 10-100 mg / L.
  • benzene konium chloride sodium dodecyl sulfate, polyethylenimine, dimethylformamide, ethanol or magnesium chloride may be used.
  • the dispersant content may be added in weight percent generally known to those skilled in the art to achieve sufficient dispersion.
  • Solution-based carbon nanotube materials can be coated using simple, low temperature (less than 450 ° C.) processes such as spin coating, nano stamping or inkjet printing.
  • the coating is heated to an appropriate temperature (eg, less than 250 ° C.) during or after the coating process to blow off solvents such as moisture and additives such as dispersants to form a carbon nanotube layer.
  • an appropriate temperature eg, less than 250 ° C.
  • the carbon nanotube particles in the floating gate 1050 may act as trapping sites for trapping the tunneled carrier through the tunneling insulating film.
  • the floating gate 1050 may be formed by low temperature coating (spin coating, nano stamping, inkjet printing, etc.) of a solution-based conductive semiconductor oxide instead of the above-described solution-based carbon nanotube material.
  • the floating gate 105 may be formed by coating a solution-based IGZO material or by coating a solution-based ZnO, indium zinc oxide (IZO), or zinc tin oxide (ZTO) material. It may be.
  • a tunneling insulating layer 107 is formed on the floating gate 1050.
  • the tunneling insulating film 1070 an oxide film or a nitride film such as Al 2 O 3 having a high dielectric constant, SiO 2 , SiNx, HfO 2 , or the like can be used.
  • the channel layer 1080 is formed by coating a solution-based semiconductor oxide material on the tunneling insulating layer 1070, and source-drain electrodes on both sides of the channel layer 1080 are formed. 1100, 1200.
  • the channel layer 1080 is coated on the tunneling insulating layer 107 by, for example, spin-coating a solution-based indium gallium zinc oxide (IGZO) material, or by nano stamping or inkjet printing, to blow off additives or solvents in the solution.
  • IGZO solution-based indium gallium zinc oxide
  • a channel layer 108 of IGZO can be formed.
  • the formed IGZO channel layer is a polycrystalline n-type semiconductor material and can function as a conductive region for carrier transfer with high mobility.
  • Channel layer formation by a solution-based semiconductor oxide coating process can be easily performed at a low temperature of less than 450 °C.
  • the semiconductor oxide used to form the channel layer 1080 in addition to the above-described IGZO, ZnO, IZO, ZTO, or the like may be used.
  • Solution based ZnO, IZO or ZTO materials can be easily formed by spin coating, nano stamping or inkjet printing at temperatures below 450 ° C.
  • the channel layer formation through the coating of the solution-based semiconductor oxide material spin coating, nano stamping or inkjet method
  • Solution-based IGZO materials can be prepared, for example, as follows. 1.0 M zinc acetate dihydrate ((Zn (CH 3 COO) 2 2 H 2 O), 0.5 M gallium nitrate hydrate (Ga (NO 3 ) 3 3 H 2 O) and indium nitrate hydrate (In (NO 3 ) Prepare a precursor of IGZO by dissolving 3 xH 2 O) in 20 mL of 2-methoxyethanol solvent, where monoethanolamine is added as a solution stabilizer. And drop the acetic acid (CH 3 COOH) and stir to make a homogeneous solution, after strong sterling for 1 h at 60 ° C., allow the IGZO solution to age for 72 h .
  • a material such as IZO, Cu, Al, W, MoW, Ti, Ta, Cr, or Ag may be used.
  • a bottom control gate type flash memory cell can be made on a glass substrate or a flexible substrate.
  • the advantage of such a cell is that a glass substrate can be used to implement a SOC (System on chip) by embedding flash memory in a display such as an LCD or an OLED.
  • SOC System on chip
  • FIGS. 24 are cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment, and correspond to a process of manufacturing a top control gate type flash memory device.
  • the solution-based IGZO material, or the solution-based ZnO, IZO, or ZTO material as shown in FIG. 24 (b). Is coated (spin coated, nano stamped, ink jet coated) to form a channel layer 2080, and a nuling insulating film 2070 is formed thereon.
  • the floating gate layer 2050 is formed by coating a solution-based carbon nanotube material or a solution-based IGZO, ZnO, IZO or ZTO material.
  • an interlayer insulating film 2040 and a control gate layer 203 are formed.
  • the floating gate layer, the interlayer insulating film and the control gate layer are patterned, and as shown in Fig. 24 (f), the source-drain electrodes 2100 and 2200 and the sidewall insulating film are shown. 2060 and the like.
  • FIG. 25 is a cross-sectional view illustrating an example of a flash memory device having a 3D stacked cell structure manufactured by applying the above-described flash memory cell structure / manufacturing method to a conventional silicon semiconductor based flash memory cell.
  • a silicon semiconductor substrate 3010 having conventional doped source-drain regions 3100 and 3200, a tunneling insulating film 3070, a first floating gate 3070, an interlayer insulating film 3040, and a first
  • the control gate 3030 forms a lower memory cell (first memory cell unit).
  • an upper memory cell (second memory cell portion) using a channel layer such as IGZO described above is stacked.
  • the semiconductor oxide is coated on the interconnection metal layer 350 and the intermetallic insulating film 3600 by coating (spin coating, nanopressure, inkjet printing, etc.) based on the above-described solution-based IGZO, ZnO, IZO or ZTO.
  • Channel layer 3680 is formed.
  • the tunneling insulating layer 3670, the second floating gate 3650, the interlayer insulating layer 3640, and the second control gate 3630 are sequentially stacked on the channel layer 3680.
  • the second floating gate 3650 may be formed by coating a solution-based nanotube material or a solution-based IGZO, ZnO, IZO or ZTO, similar to the floating gates 1050 and 2050 of the above-described embodiment.
  • the second floating gate 3650 and the channel layer 3680 are formed by coating a solution-based semiconductor oxide or carbon nanotube material, a low temperature process of 450 ° C. or less is possible. Therefore, it is possible to form a channel layer using a solution-based semiconductor oxide by stacking on a silicon-based flash memory cell currently used, and the floating gate (second floating gate) is also easily formed as a carbon nanotube or a semiconductor oxide in a low temperature process. You can make it.
  • the low temperature process of the upper memory cell hardly affects the source, drain doped regions 3100 and 3200 and the channel doped region and the interconnection metal layer 3500 at the bottom, it is possible to implement a flash memory cell having a 3D stacked structure. Can be. Therefore, high density can be realized at low cost, which is advantageous for application to SSDs.
  • FIG. 26 is a cross-sectional view illustrating a flash memory device having a 3D stacked cell structure according to another embodiment.
  • the embodiment of FIG. 26 applies channel layer formation by the above-described solution-based semiconductor oxide coating not only on the upper memory cell but also on the lower memory cell.
  • the first floating gate 4050 and the first control gate 4030 form a lower first memory cell unit.
  • An interconnect metal layer 4500 and an intermetallic insulating film 4600 are formed thereon.
  • the second channel layer 4680, the tunneling insulating film 4670, and the second floating gate (not formed by coating a solution-based IGZO, ZnO, IZO, or ZTO material on the first memory cell portion with the metal layer 4500 interposed therebetween).
  • a second memory cell unit including a 4650 and a second control gate 4630 is stacked.
  • the first and second floating gates 4050 and 4650 may be formed by coating a solution-based nanotube material or a solution-based IGZO, ZnO, IZO or ZTO, similar to the floating gates 1050 and 2050 of the above-described embodiment. Can be.
  • Source-drain electrodes 4100 and 4200 are disposed at both sides of the first channel layer 4080.
  • Oxide semiconductors are expected to replace conventional semiconductor processes using silicon (Si).
  • Si silicon
  • active driving devices such as organic light emitting diodes (OLEDs) using oxide semiconductors. This is concentrated.
  • OLEDs organic light emitting diodes
  • TFT-LCD liquid crystal display
  • UHD Ultra High Definition
  • oxide semiconductors have been proposed.
  • the conventional sputtering method and the vacuum deposition method such as ALD (Atomic Layer Deposition) have been proposed, but the manufacturing cost is high, so spin coating or inkjet method is used to reduce the manufacturing cost according to the vacuum equipment. Proposed.
  • ALD Atomic Layer Deposition
  • spin coating or inkjet method is used to reduce the manufacturing cost according to the vacuum equipment. Proposed.
  • the sol-gel method requires a solvent, etc. as an additive in order to make the sol-gel, and these additives are blown through the post-heat treatment and leave only the pure oxide that we want to obtain.
  • heat is transferred using Furnace. This heat treatment is usually carried out at several hundred degrees Celsius, since oxides are not formed at temperatures below that and thus exhibit no semiconductor properties.
  • this heat treatment is expensive to manufacture and is an obstacle to applying to a flexible substrate.
  • an embodiment of the present invention provides an oxide semiconductor thin film and an oxide thin film transistor forming method capable of blocking direct heat transfer to a substrate.
  • 27A and 27B are cross-sectional views illustrating a method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention.
  • an oxide semiconductor aqueous solution 210 is formed on a substrate 200 by a liquid phase manufacturing process.
  • a liquid phase manufacturing process for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2
  • An oxide semiconductor comprising any one or two or more components of O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3 , for example It is manufactured in a liquid state such as a sol-gel method and coated on the substrate 200.
  • the substrate 200 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
  • a method of coating the oxide semiconductor aqueous solution 210 on the substrate 200 for example, a screen printing method, a spin coating method, or an ink-jet method may be used. It is not limited thereto.
  • the screen printing method is, for example, by forming a predetermined oxide semiconductor in a liquid phase, for example, forming a sol-gel, and then, for example, a method such as silk screen or stainless mesh. It is a method of coating the liquid oxide prepared oxide semiconductor on a substrate as if pressed through the coating.
  • the screen printing method is a method of printing a desired pattern on a substrate by, for example, placing a screen on which a predetermined pattern is formed on the substrate 200 and, for example, compressing and transferring a predetermined paste. Because of its simplicity and low cost of equipment, there is a possibility of lowering the manufacturing cost when mass-producing products.
  • the process mechanism of the screen printing method is, for example, the paste is rotated in the front direction than the squeegee at the site where the squeegee, the screen, the substrate and the like contact, the screen The opening of is moved downwards in contact with the substrate and filled in the pattern portion.
  • the paste remains on the substrate.
  • the squeegee serves to make the adhesion between the screen and the substrate uniform and stable, and to stabilize the rotation of the paste.
  • the four variables that greatly affect the printing conditions of the screen printing method are, for example, the clearance for the separation of the screen, the angle of the squeegee for the rotation of the paste, and the uniform adhesion with the substrate. Pressure applied and the speed of the squeegee for proper flow of the paste.
  • the spin coating method is one of the most used in the sol-gel method
  • the inkjet method is a thin film formation method that can be most noticed in a flexible display in the future, for example, to a semiconductor layer after coating
  • the process cost can be reduced because there is no need for patterning.
  • an oxide semiconductor thin film 210 ′ is formed on the substrate 200 by heat treating the oxide semiconductor aqueous solution (210 of FIG. 27A).
  • the heat treatment is a process for evaporating and removing additives such as solvents or stabilizers necessary for the preparation of the oxide semiconductor aqueous solution (210 of FIG. 27A), and in the method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
  • the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
  • the heat treatment using the laser is, for example, unlike the conventional heat treatment by Furnace, etc., a high temperature of, for example, about 300 ° C. or higher accompanying the heat treatment of the oxide semiconductor aqueous solution (210 in FIG. 27A) is performed on the substrate 200. Since it is possible to prevent the direct addition to the substrate, for example, it is possible to use a relatively inexpensive substrate that can be used at a low temperature, thereby reducing the manufacturing cost, and making it possible to use, for example, a flexible substrate.
  • the oxide semiconductor thin film 210 ' according to the embodiment of the present invention, at least two regions P1 and P2 having different characteristics on the oxide semiconductor thin film 110' formed after the heat treatment. It is possible to form a batch.
  • the oxide semiconductor thin film 210 it is possible to simultaneously form at least two regions P1 and P2 on the oxide semiconductor thin film 210 'through one heat treatment process (that is, heat treatment by irradiation of a laser beam), for example, an oxide semiconductor. It is possible to simultaneously form a semiconductor region (Semi-conductor), a conductor region (Conductor) and the like on the thin film.
  • the semiconductor region refers to, for example, about 1 ⁇ 10 13 cm ⁇ 3 to 9 ⁇ 10 16 cm ⁇ 3
  • the conductor region includes, for example, about 9 ⁇ 10 17 cm ⁇ 3 or more of the carrier.
  • these two regions may have an amorphous phase, a polycrystalline phase, or the like.
  • At least two regions P1 and P2 formed on the oxide semiconductor thin film 210 ' may be formed by using, for example, a half-tone mask M, but is not limited thereto. It is also possible to use any other means having the same function as the half-tone mask M.
  • the lasers with different energy densities are irradiated simultaneously by irradiating the laser through this half-tone mask (M). It is possible to do
  • At least two regions P1 and P2 may be simultaneously formed in one heat treatment process, thereby reducing the number of mask processes, for example. As a result, the process time and the process cost can be reduced.
  • 28A to 28E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a bottom gate method.
  • the gate electrode 310 is formed on the substrate 300 on which the buffer layer B is formed.
  • the gate electrode 310 is a conductive metal having transparency on the substrate 300, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and gallium zinc oxide (GZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • GZO gallium zinc oxide
  • any one of the translucent metals may be formed by depositing, for example, sputtering or the like, and then patterning the metal into a predetermined shape, but is not limited thereto.
  • the substrate 300 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
  • the buffer layer B serves to prevent contamination by the lower substrate 300 in the process of forming a channel region (P2 of FIG. 2D), which will be described later.
  • the buffer layer B may be omitted. It is also possible.
  • a gate insulating layer 320 is formed on the substrate 300 including the gate electrode 310.
  • the gate insulating layer 320 may be formed by, for example, depositing an oxide film, a nitride film, or a transparent insulating material by, for example, a plasma enhanced chemical vapor deposition (PECVD) method, but is not limited thereto.
  • PECVD plasma enhanced chemical vapor deposition
  • the oxide semiconductor aqueous solution 330 is formed on the gate insulating layer 320.
  • the oxide semiconductor aqueous solution 230 is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 At least one of TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3
  • the oxide semiconductor may be manufactured in a liquid state, such as a sol-gel method, and applied to the gate insulating layer 320.
  • a screen printing method and a spin coating method may be used. It is possible to use the method or the ink-jet (Ink-jet)
  • the oxide semiconductor aqueous solution 330 is heat-treated to form an oxide semiconductor thin film 330 ′ on the substrate 300.
  • the heat treatment is a process for evaporating and removing additives such as solvents or stabilizers, which are necessary for manufacturing an oxide semiconductor solution (330 of FIG. 28C), and in the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
  • the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
  • Such a heat treatment using the laser is, for example, unlike the conventional heat treatment by Furnace (Furnace, etc.), a high temperature, for example, about 300 °C or more involved in the heat treatment of the oxide semiconductor aqueous solution (330 in FIG. 28C) on the substrate 300 Since direct application can be prevented, the manufacturing cost can be reduced, for example, by using a relatively inexpensive substrate 300 that can be used at a low temperature. For example, it is possible to use a flexible substrate 300 or the like. Let's do it.
  • At least two regions P1 and P2 having different characteristics may be collectively formed on the oxide semiconductor thin film 330 ′ formed after the heat treatment.
  • This can be formed, for example, by using a half-tone mask (M), but is not limited to any other having the same function as the half-tone mask (M). It is also possible to use means.
  • M half-tone mask
  • At least two regions P1 'and P2' of different densities are provided to correspond to the respective regions (e.g., regions P1 and channel regions P2 for forming source / drain electrodes, etc.).
  • the transmittance of the laser according to the density of the half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously.
  • the laser beam having a higher energy density can be irradiated, for example, by being covered by the half-tone mask M only for a certain region corresponding to the channel region P2, thereby forming an image on the oxide semiconductor thin film 330 '. It is possible to collectively form two regions having different characteristics in the.
  • the heat treatment by the laser can improve the TFT characteristics according to the improvement of the contact resistance for the region by lowering the resistance of the source / drain electrode forming region P1 through the heat treatment at a high temperature. .
  • the formed oxide semiconductor thin film 330 ' is patterned in a predetermined pattern. For example, it can pattern in an island shape.
  • the interlayer insulating layer 340 is formed on the entire formed portion, and a predetermined region of the interlayer insulating layer is patterned to form source / drain electrodes 350 and 350 ′.
  • such a bottom gate structure also referred to as an inverted staggered structure, in other words, has a number of advantages as a structure commonly used in, for example, AMLCD, etc.
  • the mask (Mask) is easy to mass-produce There is an advantage in reducing city expenses.
  • 29A to 29E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a top gate method.
  • the oxide semiconductor aqueous solution 410 is formed on the substrate 400 on which the buffer layer B is formed.
  • the substrate 400 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
  • the buffer layer B serves to prevent, for example, contamination by the lower substrate 400 in the process of forming the channel region (P2 of FIG. 3B), and omits the buffer layer B as necessary. It is possible.
  • the substrate prevents the heat generated during the heat treatment using a laser (Laser) to prevent the transfer to the substrate 400, the anti-transmission film (not shown) that can effectively discharge the heat to the substrate It is also possible to form further on 400.
  • Laser laser
  • the anti-transmission film not shown
  • the oxide semiconductor aqueous solution 410 is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 At least one of TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3
  • the oxide semiconductor may be manufactured and applied in a liquid phase through a sol-gel method, for example, a screen printing method, a spin coating method, or an ink-jet method. Law, etc., but is not limited to such.
  • the oxide semiconductor aqueous solution 410 is heat-treated to form an oxide semiconductor thin film 410 ′ on the substrate 400.
  • the heat treatment is a process for evaporating and removing additives, for example, solvents and stabilizers, which are necessary for the preparation of an aqueous oxide semiconductor solution (410 of FIG. 29A), and in the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
  • the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
  • the heat treatment using the laser can prevent direct application of a high temperature of, for example, about 300 ° C. or higher, which is involved in the heat treatment of the oxide semiconductor aqueous solution (410 of FIG. 29A), directly on the substrate 400.
  • a high temperature for example, about 300 ° C. or higher
  • the manufacturing cost can be reduced, and for example, the flexible substrate 400 can be used.
  • At least two regions P1 and P2 having different characteristics may be collectively formed on the oxide semiconductor thin film 410 ′ formed after the heat treatment.
  • This can be formed, for example, by using a half-tone mask (M), but is not limited to any other having the same function as the half-tone mask (M). It is also possible to use means.
  • M half-tone mask
  • At least two regions P1 'and P2' of different densities are provided to correspond to the respective regions (for example, regions P1 and channel regions P2 for forming source / drain electrodes, etc.).
  • the transmittance of the laser according to the density of the half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously.
  • the laser beam having a higher energy density can be irradiated, for example, by being covered by the half-tone mask M only for a certain region corresponding to the channel region P2, thereby forming an image on the oxide semiconductor thin film 310 '. It is possible to collectively form two regions having different characteristics in the.
  • the heat treatment by the laser can improve the TFT characteristics according to the improvement of the contact resistance for the region by lowering the resistance of the source / drain electrode forming region P1 through the heat treatment at a high temperature. .
  • the formed oxide semiconductor thin film 310 ' is patterned in a predetermined pattern. For example, it can pattern in an island shape.
  • a gate insulating layer 420 is formed on the oxide semiconductor thin film 410 ′.
  • the gate insulating layer 420 may be formed by, for example, depositing an oxide film, a nitride film, or a transparent insulating material by, for example, a plasma enhanced chemical vapor deposition (PECVD) method, but is not limited thereto.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate electrode 430 is formed on the gate leading layer 420.
  • any conductive metal having transparency on the substrate 400 for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), or translucent metal
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • GZO gallium zinc oxide
  • One metal may be formed by depositing, for example, sputtering or the like, and then patterning the metal into a predetermined shape, but is not limited thereto.
  • an interlayer insulating layer 440 is formed over the entire formed layer, and a region of the interlayer insulating layer 440 is patterned to form source / drain electrodes 450 and 450 ′.
  • the top gate structure in other words, the coplanar structure (Coplanar) structure, because the gate metal is formed after the formation of the channel region (P1) has the advantage that the heat transfer can occur evenly when forming the channel region (P1). have.
  • This top gate structure mainly adopts this structure in the case of a polysilicon (P-Si) TFT using laser annealing such as excimer laser (ELA) or SLS as in one embodiment of the present invention.
  • laser annealing such as excimer laser (ELA) or SLS as in one embodiment of the present invention. This is because the grain size can be made constant because the laser energy can be prevented from being locally changed by the lower gate metal.
  • FIGS. 30 and 31 are plan views and cross-sectional views illustrating a backplane structure of a liquid crystal display device to which a method of manufacturing an oxide thin film transistor according to an embodiment of the present invention is applied, but the bottom gate method is described as an example.
  • the present invention is not limited thereto, and a top gate may be applied.
  • a backplane of a liquid crystal display includes a plurality of gate lines 510 and data lines 520 crossing each other on a substrate 500, and each unit pixel defined by them.
  • L1 and L2 and the thin film transistor formed in the area where they cross.
  • the thin film transistor includes a gate electrode 510 formed by protruding a portion of the gate line 510, and an oxide semiconductor thin film 530 that is selectively patterned, and electrically connects the gate electrode 510 and the oxide semiconductor thin film 530.
  • a gate insulating layer 540 is insulated from the substrate.
  • each of the source / drain electrode formation region (P1) and the channel region (P2) on the oxide semiconductor thin film 530. ) May be formed in a batch.
  • the source / drain electrode formation region P1 of the oxide semiconductor thin film 530 may be used as a region for forming a predetermined electrode for transmitting a data signal in the pixels L1 and L2.
  • a data signal applied through the data line 520 may be transmitted through the thin film transistor, and the transferred data signal may be transferred to the pixel electrode 550 for applying a voltage to one surface of both ends of the liquid crystal.
  • Exemplary embodiments of the present invention provide a transparent oxide film required for a transistor liquid crystal display, an organic electroluminescent display, a solar cell, an image sensor, etc. in place of an oxide semiconductor thin film using a sputtering deposition method, and also replaces an existing amorphous or polycrystalline silicon thin film. It is possible.
  • Embodiments of the present invention can be applied to a low temperature flash memory process.
  • Embodiments of the present invention are effective in implementing a system on chip (SOC) by embedding a flash memory device in a display such as an LCD or an OLED due to the applicability of a flexible substrate such as a glass substrate or PET.
  • SOC system on chip
  • Embodiments of the present invention can manufacture a highly integrated nonvolatile memory device at low cost by implementing a 3D stacked cell, which is advantageous for application to a large capacity SSD.

Abstract

Provided are oxide semiconductor thin film forming and crystallization methods and a flash memory forming method using a liquid-phase process, and also an oxide semiconductor thin film transistor and a method for forming the same.

Description

[규칙 제26조에 의한 보정 02.08.2010]　액상 공정을 이용한 산화물 반도체 박막의 형성 방법, 결정화 방법, 이를 이용한 반도체 소자 형성 방법[Correction according to Rule 26.08.2010] 형성 Formation method, crystallization method, and semiconductor device formation method using oxide semiconductor thin film using liquid phase process
본 발명의 실시 예들은 액상공정을 이용한 반도체 박막의 형성 방법, 결정화 방법, 이를 이용한 반도체 소자 형성 방법에 관련된 것이다.Embodiments of the present invention relate to a method of forming a semiconductor thin film using a liquid phase process, a crystallization method, and a method of forming a semiconductor device using the same.
더욱 상세하게 본 발명의 실시 예들은 액상 공정을 이용한 산화물 반도체 박막의 형성 방법 및 그 결정화 방법, 액상 공정을 이용한 플래쉬 메모리 소자 및 그 형성 방법, 그리고 액상 공정을 이용한 산화물 반도체 트랜지스터 및 그 형성 방법에 관련된 것이다.In more detail, embodiments of the present invention relate to a method of forming an oxide semiconductor thin film using a liquid phase process and a crystallization method thereof, a flash memory device using the liquid phase process and a method of forming the same, and an oxide semiconductor transistor using a liquid phase process and a method of forming the same. will be.
특히 본 발명의 실시 예에 따른 액상 공정을 이용한 플래쉬 메모리 소자 및 그 형성 방법은 교육과학기술부 및 한국과학재단의 국가지정연구실사업의 일환으로 수행한 연구로부터 도출된 것이다[과제관리번호: 2008-8-0878, 과제명: 차세대 디스플레이를 위한 SBS(SOLUTION BASED SI) 박막 및 ASB(ALL SOLUTION BASED) TFT 기술개발].In particular, the flash memory device using a liquid phase process and a method of forming the same according to an embodiment of the present invention are derived from a study performed as a part of a national laboratory project of the Ministry of Education, Science and Technology and the Korea Science Foundation. -0878, Title: Development of SOLUTION BASED SI (SBS) thin film and ALL SOLUTION BASED (ASB) TFT technology for next generation display].
요즘, 산화물 박막은 디스플레이 및 반도체 소자에 유용하게 사용되어 지고Nowadays, oxide thin films are useful for displays and semiconductor devices.
있다. 그 중에 아연산화물(ZnO)은 Ⅱ-Ⅵ족 직접 천이형 반도체로서 3.37 eV의 높은 밴드갭을 가져 가시광선 영역에서 투명하며, 60 meV의 엑시톤 결합 에너지가 있어 광소자로서 많이 이용되고 있다{D. C. Look et al. "Recent advances in ZnO materials and devices" Materials Science and Engineering: B 80, 383, (2001)}. 아연산화물은 칩입형 아연과 산소공공과 같은 네이티브 디펙트(nativedefects)에 의해 n 타입 특성을 나타내고 있으며, 공정조건에 따라 10-2 ~ 1010 Ωcm 까지 전기적 특성을 변화시킬 수 있다. 여기서, 전자농도를 더욱 증가시켜투명전극으로 이용할 수 있는데, Ⅲ족이나 Ⅶ을 도핑한다. 대표적인 도펀트(dopant)로서 Ⅲ족인 갈륨(Ga), 알루미늄(Al) 또는 인듐(In)이 존재하며, 이를 도핑한 물질을 아연갈륨산화물(GZO){Quan-Bao et al. "Structural, electrical, and optical properties of transparent conductive ZnO:Ga films prepared by DC reactive magnetron sputtering" Journal of Crystal Growth, 304, 64 (2007)}, 알루미늄 아연산화물(AZO){Byeong-Yun Oh et al. "Properties of transparent conductivehave. Among them, zinc oxide (ZnO) is a group II-VI direct transition semiconductor, having a high band gap of 3.37 eV, transparent in the visible region, and having an exciton binding energy of 60 meV, which is widely used as an optical device {D. C. Look et al. "Recent advances in ZnO materials and devices" Materials Science and Engineering: B 80, 383, (2001)}. Zinc oxide exhibits n-type characteristics by native defects such as chipped zinc and oxygen vacancies, and can change electrical properties from 10-2 to 1010 Ωcm depending on process conditions. Here, the electron concentration can be further increased to be used as a transparent electrode, and doped with Group III or doped. Representative dopants include group III gallium (Ga), aluminum (Al) or indium (In), and the doped material is zinc gallium oxide (GZO) {Quan-Bao et al. "Structural, electrical, and optical properties of transparent conductive ZnO: Ga films prepared by DC reactive magnetron sputtering" Journal of Crystal Growth, 304, 64 (2007)}, aluminum zinc oxide (AZO) {Byeong-Yun Oh et al. "Properties of transparent conductive
ZnO:Al films prepared by co-sputtering" Journal of Crystal Growth, Volume 274, 453, (2005)}, 인듐 아연산화물(IZO){E.J. Luna-Arredondo et al. "Indium-doped ZnO thin films deposited by the solgel technique" Thin Solid Films, 490, 132 (2005)}로 명명한다. 이 투명전극들은 현재 전자소자에 많이 응용되고 있는 투명전극 인듐틴산화물(ITO;Indium tin oxide)을 대체할 물질로서 각광받고 있다. ZnO: Al films prepared by co-sputtering "Journal of Crystal Growth, Volume 274, 453, (2005)}, Indium Zinc Oxide (IZO) {EJ Luna-Arredondo et al." Indium-doped ZnO thin films deposited by the solgel technique ”Thin Solid Films, 490, 132 (2005). These transparent electrodes are in the spotlight as a substitute for indium tin oxide (ITO), which is widely used in electronic devices.
아연산화물의 투명도는 투명트랜지스터를 가능하게 하며, 높은 이동도로 인해 디스플레이 소자의 트랜지스터 활성층으로 사용된다. 아연산화물이 벌크(bulk)일 경우 약 200cm2/Vs의 우수한 이동도를 가지고 있다{D. C. Look et al. "Electrical properties of bulk ZnO" Solid State Commun. 105, 399 (1998)}. 또한, 아연화합물은 이온결합을 하고 있어 실리콘(Si)과 비교하여 단결정이 되었을The transparency of the zinc oxide enables transparent transistors and is used as the transistor active layer of display devices due to the high mobility. If the zinc oxide is bulk, it has a good mobility of about 200 cm2 / Vs {D. C. Look et al. "Electrical properties of bulk ZnO" Solid State Commun. 105, 399 (1998)}. In addition, zinc compounds have ionic bonds, which make them single crystals compared to silicon (Si).
때와 비정질이었을 때의 이동도 차이가 크질 않다. 이와 같은 성질은 높은 이동도의 활성층이 요구되는 현재 디스플레이 소자에 적용되어 질 수 있다. 여기서 더 나아가, 보다 더 높은 이동도와 안정된 활성층을 얻기 위해 아연화합물과 여러 가지 다른 원소를 합금화하여 이용하려 하였다. 인듐-갈륨-아연산화물(IGZO;In-Ga-ZnO}, 인듐-아연산화물(IZO;In-ZnO), 틴-아연산화물(SZO;Sn-ZnO), 틴-갈륨-아연산화물(SGZO;Sn-Ga-ZnO), 인듐-틴-아연산화물(ISZO;In-Sn-ZnO), 탈륨-아연산화물(TZO;Tl-ZnO), 탈륨-갈륨-아연산화물(TGZO;Tl-Ga-ZnO)과 같이 아연보다 이온반경이 큰 오비탈(orbital) 5s 이상을 갖는 물질(인듐,틴,탈륨)을 첨가하여 아연화합물과 합금을 이루게 한다. 이 물질들은 아연보다 큰 양이온 때문에 서로의 5s 오비탈의 최외각전자를 더 많이 공유하게 되어 전자의 이동도에 기여하게 된다. 여기서 활성층의 갈륨은 전기적 특성을 조절하고 안정성을 높이는데 기여한다. 현재, 특히 인듐-갈륨-아연화합물(IGZO)에 대해서 펄스레이저 증착법(PLD;pulsed laser deposition), 스퍼터링(sputtering), 화학기상증착(CVD;chemical vapor deposition) 등의 진공 장비를 이용하여 여러 디스플레이 소자에 응용하기 위해 연구되어지고 있다. 하지만, 이러한 진공 장비를 이용할 경우 대형화에 따른 장비 가격의 문제로 인해 공정 단가가 높아지는 단점이 있다.There is not much difference in mobility between when and when it is amorphous. This property can be applied to current display devices requiring high mobility active layers. Furthermore, zinc compounds and various other elements were alloyed to obtain higher mobility and stable active layer. Indium-gallium-zinc oxide (IGZO; In-Ga-ZnO), indium zinc oxide (IZO; In-ZnO), tin-zinc oxide (SZO; Sn-ZnO), tin-gallium-zinc oxide (SGZO; Sn -Ga-ZnO), indium-tin-zinc oxide (ISZO; In-Sn-ZnO), thallium-zinc oxide (TZO; Tl-ZnO), thallium-gallium-zinc oxide (TGZO; Tl-Ga-ZnO) Likewise, a substance having an orbital of 5s or more having a larger ion radius than zinc (indium, tin, and thallium) is added to form an alloy with the zinc compound, which is the outermost electron of each other 5s orbital due to a cation larger than zinc. And share more electrons, contributing to the mobility of electrons, where the gallium in the active layer contributes to controlling the electrical properties and enhancing the stability.At present, especially for indium-gallium-zinc compound (IGZO), Various display devices using vacuum equipment such as pulsed laser deposition (PLD), sputtering, chemical vapor deposition (CVD), etc. There is research to be applied. However, due to the vacuum equipment such as the problem of the price of the equipment when using large has the disadvantage that the fair price increases.
본 발명의 일 실시 예는 액상 공정을 이용하여, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 또는 2종 이상의 산화화합물을 졸겔법 및 열처리 공정에 의해 투명 결정질 산화물 반도체 박막을 형성함으로써, 박막 트랜지스터와 태양전지, 이미지 센서 등의 산화막을 이용한 반도체 소자를 간단하고 저렴하게 제작할 수 있도록 한 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 제공하는 데 있다.According to an embodiment of the present invention, at least one or two or more oxidized compounds selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds are transparent by a sol-gel method and a heat treatment process using a liquid phase process. By forming a crystalline oxide semiconductor thin film, a method of crystallizing an oxide semiconductor thin film using a liquid-based fabrication to enable a simple and inexpensive fabrication of semiconductor devices using oxide films such as thin film transistors, solar cells, image sensors and the like.
본 발명의 다른 실시 예는 액상 공정을 이용하여 저온에서 채널 영역을 형성할 수 있고 3D 적층셀 구현이 용이하며 유리 또는 플라스틱 기판의 적용이 충분히 가능한 플래쉬 메모리 소자의 제조 방법 및 이에 의한 플래쉬 메모리 소자를 제공하는 것이다.Another embodiment of the present invention is a method of manufacturing a flash memory device capable of forming a channel region at a low temperature using a liquid phase process, easy implementation of a 3D stacked cell, and sufficient application of a glass or plastic substrate, and a flash memory device thereby. To provide.
본 발명의 다른 실시 예는 액상 공정을 이용한 산화물 반도체 박막 및 산화물 박막 트랜지스터의 제조방법을 제공하는 데 있다.Another embodiment of the present invention to provide a method for manufacturing an oxide semiconductor thin film and the oxide thin film transistor using a liquid phase process.
본 발명의 일 측면에 따른 산화물 반도체 박막 결정화 방법은 (a) 기판 상에 절연막을 형성하는 단계; (b) 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계; (c) 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계; (d) 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계; 및 (e) 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계를 포함할 수 있다.Oxide semiconductor thin film crystallization method according to an aspect of the present invention comprises the steps of (a) forming an insulating film on the substrate; (b) depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film; (c) drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d) drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And (e) drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
바람직하게, 상기 단계(a)에서, 상기 절연막은 실리콘 산화막 또는 질화막으로 이루어질 수 있다.Preferably, in step (a), the insulating film may be formed of a silicon oxide film or a nitride film.
본 발명의 실시형태에 따르면, 상기 단계(a) 이후에, 상기 기판과 산화화합물 졸의 안정적인 결합 향상을 위하여 플라즈마 혹은 용액처리를 수행하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, after step (a), the method may further include performing plasma or solution treatment to improve stable bonding between the substrate and the oxide compound sol.
본 발명의 실시형태에 따르면, 상기 단계(b)에서, 상기 산화화합물 졸은 스핀 코팅 또는 잉크젯 프린팅을 이용하여 증착할 수 있다.According to an embodiment of the present invention, in the step (b), the oxide compound sol may be deposited using spin coating or inkjet printing.
본 발명의 실시형태에 따르면, 상기 단계(c) 이후에, 상기 단계(b) 및 단계(c)의 졸겔 공정을 적어도 한 번 반복 수행하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, after the step (c), the step (b) and may further comprise the step of performing the sol-gel process of step (c) at least once.
본 발명의 실시형태에 따르면, 상기 단계(e) 이후에, 상기 단계(b) 내지 단계(d)를 재 수행한 후 상기 최초 투명 결정질 반도체 박막을 결정화 핵 층으로 이용하여 상기 단계(e)를 재 수행하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, after the step (e), after performing the steps (b) to (d) again, the step (e) using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer It may further comprise the step of performing again.
본 발명의 실시형태에 따르면, 상기 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물 중 선택된 적어도 어느 하나의 산화화합물의 몰비를 조절하여 상기 투명 결정질 산화물 반도체 박막의 결정화를 조절할 수 있다.According to an embodiment of the present invention, the crystallization of the transparent crystalline oxide semiconductor thin film may be controlled by controlling the molar ratio of at least one oxide selected from zinc, indium, gallium, tin and tantalum compounds.
본 발명의 실시형태에 따르면, 상기 제1 열처리 공정은 상기 산화화합물 졸에 포함되어 있는 용매와 안정제들을 증발시키고 각 화합물의 화학적 분해를 도와주는 것으로서, 상기 제1 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 250℃ 내지 450℃ 온도 범위로 1시간 동안 수행할 수 있다.According to an embodiment of the present invention, the first heat treatment process is to evaporate the solvents and stabilizers contained in the oxidized compound sol and to assist in chemical decomposition of each compound. It is carried out to change, it can be carried out for 1 hour in the 250 ℃ to 450 ℃ temperature range.
본 발명의 실시형태에 따르면, 상기 제2 열처리 공정은 화합물에 포함된 유기적 성분들이 다 증발되어 산화막 반도체로 이루어지게 하는 것으로서, 상기 제2 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 600℃ 내지 800℃ 온도 범위로 24시간 동안 수행할 수 있다.According to an exemplary embodiment of the present invention, the second heat treatment process is performed so that the organic components included in the compound are all evaporated to form an oxide semiconductor, and the second heat treatment process is performed such that the temperature is changed according to the treatment time. It may be performed for 24 hours in the temperature range of ℃ to 800 ℃.
본 발명의 실시형태에 따르면, 상기 제3 열처리 공정을 통해 비정질 상의 막을 투명한 나노 결정질 상의 막으로 이루어지게 하는 것으로서, 상기 제3 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 900℃ 내지 1100℃ 온도 범위로 24시간 동안 수행할 수 있다.According to an embodiment of the present invention, the third heat treatment is performed to change the temperature according to the treatment time, wherein the film of the amorphous phase is made of a transparent nanocrystalline film through the third heat treatment process, and the 900 ℃ to 1100 It can be performed for 24 hours in the temperature range ℃.
본 발명의 다른 측면에 따른 산화물 반도체 박막 결정화 방법은, (a') 기판 상에 절연막을 형성하는 단계; (b') 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계; (c') 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계; (d') 상기 산화화합물 겔 상에 상기 단계(b‘) 및 단계(c’)의 졸겔 공정을 적어도 한 번 반복 수행하는 단계; (e') 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계; 및 (f') 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계를 포함할 수 있다.Oxide semiconductor thin film crystallization method according to another aspect of the present invention, (a ') forming an insulating film on a substrate; (b ') depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film; (c ') drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d ') repeating the sol-gel process of steps (b') and (c ') at least once on the oxidized compound gel; (e ') drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And (f ') drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
본 발명의 또 다른 측면에 따른 산화물 반도체 박막 결정화 방법은, (a") 기판 상에 절연막을 형성하는 단계; (b") 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계; (c") 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계; (d") 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계; (e") 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계; 및 (f") 상기 투명 결정질 산화물 반도체 박막 상에 상기 단계(b“) 내지 단계(d”)를 재 수행한 후, 상기 최초 투명 결정질 반도체 박막을 결정화 핵 층으로 이용하여 상기 단계(e“)를 재 수행하는 단계를 포함할 수 있다.Oxide semiconductor thin film crystallization method according to another aspect of the present invention, (a ") forming an insulating film on a substrate; (b") on the insulating film zinc compound, indium compound, gallium compound, tin compound and tantalum compound Depositing at least one oxide compound sol selected from the group consisting of; (c ") drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel; (d") drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film. Forming a; (e ") drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film; and (f") the steps (b ") to on the transparent crystalline oxide semiconductor thin film. After performing step (d ″) again, the step (e ″) may be performed using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer.
본 발명의 실시형태에 따르면, 상기 단계(f)에서, 상기 최초 투명 결정질 산화물 반도체 박막과 상기 단계(b")에서의 산화화합물 졸 사이에 안정적인 결합 향상을 위하여 플라즈마 혹은 용액처리로 친수성 및 소수성을 형성하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, in step (f), hydrophilicity and hydrophobicity may be achieved by plasma or solution treatment to improve stable bonding between the first transparent crystalline oxide semiconductor thin film and the oxide compound sol in step (b ″). It may further comprise the step of forming.
본 발명의 일 측면에 따른 플래쉬 메모리 소자 형성 방법은 기판 상에 채널층, 플로팅 게이트 및 제어 게이트를 형성하는 단계를 포함하며, 상기 채널층은 용액 기반의 반도체 산화물 물질을 코팅하여 형성되는 것을 특징으로 한다. A method of forming a flash memory device according to an aspect of the present invention includes forming a channel layer, a floating gate, and a control gate on a substrate, wherein the channel layer is formed by coating a solution-based semiconductor oxide material. do.
본 발명의 실시형태에 따르면, 상기 채널층은 용액 기반의 IGZO(Indium Gallium Zinc Oxide) 물질을 코팅하여 형성될 수 있다. 다른 실시형태에 따르면, 상기 채널층은 용액 기반의 ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성될 수 있다.According to an embodiment of the present invention, the channel layer may be formed by coating a solution-based indium gallium zinc oxide (IGZO) material. According to another embodiment, the channel layer may be formed by coating a material selected from solution based ZnO, IZO and ZTO.
본 발명의 실시형태에 따르면, 상기 플로팅 게이트는 용액 기반의 카본 나노튜브 물질을 코팅하여 형성될 수 있다. 상기 카본 나노튜브 물질은 SWNT, MWNT, 그라펜(graphene) 및 플러렌(fullerene) 중 적어도 1종을 포함할 수 있다. 다른 실시형태에 따르면, 상기 플로팅 게이트는 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성될 수 있다. According to an embodiment of the present invention, the floating gate may be formed by coating a solution-based carbon nanotube material. The carbon nanotube material may include at least one of SWNT, MWNT, graphene, and fullerene. According to another embodiment, the floating gate may be formed by coating a material selected from solution-based IGZO, ZnO, IZO and ZTO.
상기 채널층은 스핀 코팅(spin coating), 나노 압인(nano imprinting) 및 잉크젯 프린팅 중에서 선택된 공정을 이용하여 형성될 수 있다. The channel layer may be formed using a process selected from spin coating, nano imprinting, and inkjet printing.
본 발명의 실시형태에 따르면, 상기 제조 방법에 의해 제조되는 플래쉬 메모리 소자는 바텀 제어 게이트형(bottom control gate type) 소자로서, 상기 기판 위에 상기 제어 게이트와 플로팅 게이트를 형성한 후에 상기 채널층을 형성할 수 있다. 다른 실시형태에 따르면, 상기 제조 방법에 의해 제조되는 플래쉬 메모리 소자는 탑 제어 게이트형(top control gate type) 소자로서, 상기 기판 위에 상기 채널층을 형성한 후에 상기 플로팅 게이트 및 제어 게이트를 형성할 수 있다.According to an embodiment of the present invention, a flash memory device manufactured by the manufacturing method is a bottom control gate type device, and after forming the control gate and the floating gate on the substrate, the channel layer is formed. can do. According to another embodiment, the flash memory device manufactured by the manufacturing method is a top control gate type device, and after forming the channel layer on the substrate, the floating gate and the control gate may be formed. have.
상기 기판은 유리 기판 또는 PET 등의 플라스틱 기판일 수 있다. 다른 실시형태로서, 실리콘 기판일 수도 있다. The substrate may be a glass substrate or a plastic substrate such as PET. As another embodiment, it may be a silicon substrate.
본 발명의 다른 측면에 따른 플래쉬 메모리 소자는, 기판과 상기 기판 상에 형성된 채널층, 플로팅 게이트 및 제어 게이트를 포함하며, 상기 채널층은 용액 기반의 IGZO 물질의 코팅을 통해 형성된 다결정(poly crystalline) IGZO로 이루어진 것을 특징으로 한다.According to another aspect of the present invention, a flash memory device includes a substrate and a channel layer, a floating gate, and a control gate formed on the substrate, the channel layer being formed of a poly crystalline layer formed by coating a solution-based IGZO material. It is characterized by consisting of IGZO.
본 발명의 실시형태에 따르면, 상기 플로팅 게이트는 카본 나노튜브로 이루어진 층 구조일 수 있다. 다른 실시형태에 따르면, 상기 플로팅 게이트는 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 층 구조일 수 있다.According to an embodiment of the present invention, the floating gate may have a layer structure made of carbon nanotubes. According to another embodiment, the floating gate may be a layer structure made of a material selected from IGZO, ZnO, IZO, and ZTO.
본 발명의 실시형태에 따르면, 상기 플래쉬 메모리 소자는 상기 기판 위에 제어 게이트가 배치되고, 상기 제어 게이트 위에 상기 플로팅 게이트가 배치되고, 상기 플로팅 게이트 위에 상기 채널층이 배치되는 바텀 제어 게이트형 플래쉬 메모리 소자일 수 있다. 다른 실시형태에 따르면, 상기 플래쉬 메모리 소자는 상기 기판 위에 채널층이 배치되고, 상기 채널층 위에 상기 플로팅 게이트가 배치되고, 상기 플로팅 게이트 위에 상기 제어 게이트가 배치되는 탑 제어 게이트형 플래쉬 메모리 소자일 수 있다.In example embodiments, a bottom control gate type flash memory device may include a control gate disposed on the substrate, the floating gate disposed on the control gate, and the channel layer disposed on the floating gate. Can be. According to another embodiment, the flash memory device may be a top control gate type flash memory device in which a channel layer is disposed on the substrate, the floating gate is disposed on the channel layer, and the control gate is disposed on the floating gate. have.
본 발명의 또 다른 측면에 따른 플래쉬 메모리 소자 형성 방법은, 기판 상에 제1 플로팅 게이트층 및 제1 제어 게이트층을 형성하는 단계; 및 상기 제1 게이트층 위에 상부 채널층, 제2 플로팅 게이트층 및 제2 제어 게이트층을 형성하는 단계를 포함하고, 상기 상부 채널층은 용액 기반의 반도체 산화물 물질을 코팅하여 형성하는 것을 특징으로 한다.A flash memory device forming method according to another aspect of the present invention includes forming a first floating gate layer and a first control gate layer on a substrate; And forming an upper channel layer, a second floating gate layer, and a second control gate layer on the first gate layer, wherein the upper channel layer is formed by coating a solution-based semiconductor oxide material. .
상기 상부 채널층은 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성될 수 있다.The upper channel layer may be formed by coating a material selected from a solution-based IGZO, ZnO, IZO and ZTO.
본 발명의 실시형태에 따르면, 상기 기판은 실리콘 반도체로 이루어질 수 있다. 또한 상기 제1 플로팅 게이트는 폴리실리콘 물질로 형성될 수 있다. 다른 실시형태에 따르면, 상기 제1 플로팅 게이트 형성 전에 상기 기판 상에 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 하부 채널층을 형성하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, the substrate may be made of a silicon semiconductor. In addition, the first floating gate may be formed of a polysilicon material. According to another embodiment, the method may further include forming a lower channel layer by coating a material selected from solution-based IGZO, ZnO, IZO, and ZTO on the substrate before forming the first floating gate.
본 발명의 실시형태에 따르면, 상기 제2 플로팅 게이트는 용액 기반의 카본 나노튜브 물질을 코팅하여 형성될 수 있다. 다른 실시형태에 따르면, 상기 제2 플로팅 게이트는 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성될 수 있다. According to an embodiment of the present invention, the second floating gate may be formed by coating a solution-based carbon nanotube material. According to another embodiment, the second floating gate may be formed by coating a material selected from solution-based IGZO, ZnO, IZO, and ZTO.
상기 상부 채널층은 스핀 코팅(spin coating), 나노 압인(nano imprinting) 및 잉크젯 프린팅 중에서 선택된 공정을 이용하여 형성될 수 있다. The upper channel layer may be formed using a process selected from spin coating, nano imprinting, and inkjet printing.
본 발명의 또 다른 측면에 따는 플래쉬 메모리 소자는, 기판 상에 형성된 제1 플로팅 게이트 및 제1 제어 게이트를 구비하는 제1 메모리셀부; 상기 제1 메모리셀부 상에 형성된 상부 채널층, 제2 플로팅 게이트층 및 제2 제어 게이트층을 구비하는 제2 메모리셀부를 포함하고, 상기 상부 채널층은 용액 기반의 IGZO 물질의 코팅에 통해 형성된 다결정 IGZO로 이루어진다.According to another aspect of the present invention, a flash memory device may include: a first memory cell unit including a first floating gate and a first control gate formed on a substrate; And a second memory cell portion including an upper channel layer, a second floating gate layer, and a second control gate layer formed on the first memory cell portion, wherein the upper channel layer is formed of a polycrystalline crystal formed by coating a solution-based IGZO material. It is made of IGZO.
본 발명의 실시형태에 따르면, 상기 기판은 실리콘 반도체로 이루어질 수 있다. 또한 상기 제1 플로팅 게이트는 폴리실리콘 물질로 이루어질 수 있다. 다른 실시형태에 따르면, 상기 제1 메모리셀부는 상기 기판 상에 형성되고 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 하부 채널층을 더 구비할 수 있다. According to an embodiment of the present invention, the substrate may be made of a silicon semiconductor. In addition, the first floating gate may be made of a polysilicon material. In example embodiments, the first memory cell part may further include a lower channel layer formed on the substrate and made of a material selected from IGZO, ZnO, IZO, and ZTO.
본 발명의 실시형태에 따르면, 상기 제2 플로팅 게이트는 카본 나노튜브로 이루어진 층 구조일 수 있다. 다른 실시형태에 따르면, 상기 제2 플로팅 게이트는 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 층 구조일 수 있다.According to an embodiment of the present invention, the second floating gate may have a layer structure made of carbon nanotubes. According to another embodiment, the second floating gate may be a layer structure made of a material selected from IGZO, ZnO, IZO, and ZTO.
본 발명의 일 측면에 따른 산화물 반도체 박막 형성 방법은 기판 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성하는 단계; 및 상기 산화물 반도체 수용액 상에 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계를 포함하며, 상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 한다.Oxide semiconductor thin film formation method according to an aspect of the present invention comprises the steps of forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on a substrate; And forming an oxide semiconductor thin film by heat treatment by irradiating a laser beam on the aqueous oxide semiconductor solution, and when irradiating the laser beam, different characteristics are formed on the oxide semiconductor thin film by using a half-tone mask. At least two areas having a feature to collectively form.
본 발명의 실시형태에 따르면, 상기 산화물 반도체는 InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 선택된 어느 하나의 물질 또는 상기 물질들의 화합물이 포함되어 이루어질 수 있다.According to an embodiment of the present invention, the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
본 발명의 실시형태에 따르면, 상기 산화물 반도체 수용액은 졸-겔(Sol-GEL)법을 이용하여 형성할 수 있다.According to an embodiment of the present invention, the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
본 발명의 실시형태에 따르면, 상기 기판 상에 산화물 반도체 수용액을 형성하는 방법으로는 스크린 프린팅 (Screen Printing), 스핀 코팅(Spin Coating) 또는 잉크젯(Ink-Jet) 방법 중 선택된 어느 하나의 방법을 이용할 수 있다.According to an embodiment of the present invention, a method of forming an aqueous solution of an oxide semiconductor on the substrate may be any one of screen printing, spin coating, or ink-jet. Can be.
본 발명의 일 측면에 따른 산화물 박막 트랜지스터 형성 방법은 기판 상에 게이트 전극을 형성하는 단계; 상기 게이트 전극 상에 게이트 절연층을 형성하는 단계; 및 상기 게이트 절연층 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성한 후 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계를 포함하며, 상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 한다.An oxide thin film transistor forming method according to an aspect of the present invention comprises the steps of forming a gate electrode on a substrate; Forming a gate insulating layer on the gate electrode; And forming an oxide semiconductor thin film by heat treatment after forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on the gate insulating layer, wherein a half-tone mask is applied when the laser beam is irradiated. At least two regions having different characteristics may be collectively formed on the oxide semiconductor thin film.
본 발명의 실시 형태에 따르면, 상기 상기 적어도 2개의 영역 중 적어도 1개의 영역은 소오스 및 드레인 전극으로 사용하기 위한 영역일 수 있다.According to an embodiment of the present invention, at least one of the at least two regions may be a region for use as a source and a drain electrode.
본 발명의 실시 형태에 따르면, 상기 적어도 2개의 영역 중 적어도 1개의 영역은 채널 영역일 수 있다.According to an embodiment of the present invention, at least one of the at least two regions may be a channel region.
본 발명의 실시 형태에 따르면, 상기 레이저빔은 상기 적어도 2개의 영역 중 소오스 및 드레인 전극으로 사용하기 위한 영역에서 에너지 밀도를 가장 크게 하여 조사되도록 할 수 있다.According to an embodiment of the present invention, the laser beam may be irradiated with the largest energy density in the region for use as the source and drain electrodes of the at least two regions.
본 발명의 실시 형태에 따르면, 상기 산화물 반도체는 InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 선택된 어느 하나의 물질 또는 상기 물질들의 화합물이 포함되어 이루어질 수 있다.According to an embodiment of the present invention, the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
본 발명의 실시 형태에 따르면, 상기 산화물 반도체 수용액은 졸-겔(Sol-GEL)법을 이용하여 형성할 수 있다.According to an embodiment of the present invention, the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
본 발명의 실시 형태에 따르면, 상기 산화물 반도체 수용액을 형성하는 방법으로는 스크린 프린팅 (Screen Printing), 스핀 코팅(Spin Coating) 또는 잉크젯(Ink-Jet) 방법 중 선택된 어느 하나의 방법을 이용할 수 있다.According to an embodiment of the present invention, as the method for forming the oxide semiconductor aqueous solution, any one method selected from among screen printing, spin coating, and ink-jet methods may be used.
본 발명의 다른 측면에 따른 산화물 박막 트랜지스터 형성 방법은 기판 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성한 후 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계; 상기 산화물 반도체 박막 상에 게이트 절연층을 형성하는 단계; 및 상기 게이트 절연층 상에 게이트 전극을 형성하는 단계를 포함하며, 상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming an oxide thin film transistor, the method including: forming an oxide semiconductor thin film by heat treatment after forming an aqueous oxide semiconductor solution by a liquid phase manufacturing process on a substrate; Forming a gate insulating layer on the oxide semiconductor thin film; And forming a gate electrode on the gate insulating layer, wherein when the laser beam is irradiated, at least two regions having different characteristics are collectively formed on the oxide semiconductor thin film by using a half-tone mask. Characterized in that.
본 발명의 실시 형태에 따르면, 상기 적어도 2개의 영역 중 적어도 1개의 영역은 소오스 및 드레인 전극으로 사용하기 위한 영역일 수 있다.According to an embodiment of the present invention, at least one of the at least two regions may be a region for use as a source and a drain electrode.
본 발명의 실시 형태에 따르면, 상기 적어도 2개의 영역 중 적어도 1개의 영역은 채널 영역일 수 있다.According to an embodiment of the present invention, at least one of the at least two regions may be a channel region.
바람직하게는, 상기 적어도 2개의 영역 중 소오스 및 드레인 전극으로 사용하기 위한 영역에 조사하는 상기 레이저빔의 에너지 밀도는 가장 크도록 할 수 있다.Preferably, the energy density of the laser beam irradiated to the area for use as the source and drain electrodes of the at least two areas may be the largest.
본 발명의 실시 형태에 따르면, 상기 산화물 반도체는 InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 선택된 어느 하나의 물질 또는 상기 물질들의 화합물이 포함되어 이루어질 수 있다.According to an embodiment of the present invention, the oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or any one of TiSrO 3 , Compounds may be included.
본 발명의 실시 형태에 따르면, 상기 산화물 반도체 수용액은 졸-겔(Sol-GEL)법을 이용하여 형성할 수 있다.According to an embodiment of the present invention, the oxide semiconductor aqueous solution may be formed using a sol-gel (Sol-GEL) method.
본 발명의 실시 형태에 따르면 상기 산화물 반도체 수용액을 형성하는 방법으로는 스크린 프린팅 (Screen Printing), 스핀 코팅(Spin Coating) 또는 잉크젯(Ink-Jet) 방법 중 선택된 어느 하나의 방법을 이용할 수 있다.According to an embodiment of the present invention, any one method selected from among screen printing, spin coating, and ink-jet method may be used as a method of forming the oxide semiconductor aqueous solution.
본 발명의 실시 예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법에 따르면, 액상제조 기반의 산화물 반도체 예컨대, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 또는 2종 이상의 산화화합물을 졸겔법 및 열처리 공정에 의해 투명 결정질 산화물 반도체 박막을 형성함으로써, 박막 트랜지스터와 태양전지, 이미지 센서 등에서 사용된 기존의 진공 증착법을 대체하여 간단하고 저렴하게 산화막을 이용한 반도체 소자를 제작할 수 있는 이점이 있다.According to the crystallization method of the oxide semiconductor thin film using the liquid manufacturing base according to an embodiment of the present invention, at least one selected from the group consisting of a liquid semiconductor based oxide semiconductor, for example, zinc compound, indium compound, gallium compound, tin compound and tantalum compound By forming a transparent crystalline oxide semiconductor thin film by sol-gel method and heat treatment process of species or two or more kinds of oxide compounds, it is simple and inexpensive to replace conventional vacuum deposition method used in thin film transistor, solar cell, image sensor, etc. There is an advantage that the device can be manufactured.
또한, 본 발명에 의해 제작된 액상제조 기반의 산화물 반도체 박막은 현재 사용되고 있는 스퍼터링 증착법을 이용한 산화물 반도체 박막을 대신하여, 트랜지스터 액정 디스플레이, 유기 전계발광 디스플레이, 태양전지, 이미지 센서 등에 필요한 투명 산화막을 제공할 뿐만 아니라 기존의 비정질 혹은 다결정 실리콘 박막의 대체도 가능한 이점이 있다.In addition, the liquid-based oxide semiconductor thin film manufactured by the present invention provides a transparent oxide film required for a transistor liquid crystal display, an organic electroluminescent display, a solar cell, an image sensor, etc., in place of an oxide semiconductor thin film using a sputtering deposition method currently used. In addition, there is an advantage that can replace the existing amorphous or polycrystalline silicon thin film.
본 발명의 실시 예에 따른 플래쉬 메모리 소자 형성 방법에 따르면, 용액 기반의 반도체 산화물 물질을 스핀 코팅 등으로 도포함으로써 플래쉬 메모리 셀의 채널 영역을 형성함으로써, 저온에서 비교적 단순한 공정으로 채널 영역을 용이하게 형성할 수 있고 3D 적층셀 구현이 용이하며 유리 또는 플렉시블(flexible) 기판에서 플래쉬 메모리 셀을 안정적으로 구현할 수 있게 된다. 이에 더하여, 플로팅 게이트를 용액 기반의 반도체 산화물 또는 용액 기반의 카본 나노튜브 물질을 코팅하여 형성함으로써, 플래쉬 메모리셀의 제조 공정 온도를 더욱 낮게 유지시킬 수 있을 뿐만 아니라 셀 간의 간섭 문제를 해결하는데 기여한다.According to the method of forming a flash memory device according to an embodiment of the present invention, by forming a channel region of a flash memory cell by applying a solution-based semiconductor oxide material by spin coating, etc., the channel region is easily formed in a relatively simple process at low temperature. The 3D stacked cell can be easily implemented, and the flash memory cell can be stably implemented on a glass or flexible substrate. In addition, by forming a floating gate by coating a solution-based semiconductor oxide or a solution-based carbon nanotube material, it is possible not only to keep the manufacturing process temperature of the flash memory cell lower but also to solve the inter-cell interference problem. .
유리 기판 또는 PET 등의 플렉시블 기판의 적용 가능성으로 인해, LCD, OLED와 같은 디스플레이에 플래쉬 메모리 소자를 임베디드하여 SOC(system on chip)을 구현하는 데에 효과적일 뿐만 아니라, 3D 적층셀 구현으로 고집적도의 비휘발성 메모리 장치를 저비용으로 제작할 수 있고 이로써 대용량 SSD에의 적용에 유리하다. Due to the possibility of application of flexible substrates such as glass substrates or PET, it is not only effective to implement SOC (system on chip) by embedding flash memory devices in displays such as LCDs and OLEDs, but also highly integrated with 3D stacked cells. Can be manufactured at low cost, which is advantageous for application to large capacity SSDs.
본 발명의 실시 예에 따른 산화물 반도체 박막 및 산화물 반도체 박막 트랜지스터 형성 방법에 따르면, 산화물 반도체 박막 형성 시 후 열처리를 레이저(Laser)를 이용하기 때문에 기판으로의 직접적인 열 전달을 차단할 수 있으며, 레이저(Laser)의 강한 에너지를 통해 박막 형성에 필요한 온도를 확보하기 용이하다는 이점이 있다.According to the method of forming the oxide semiconductor thin film and the oxide semiconductor thin film transistor according to the embodiment of the present invention, since the heat treatment using a laser (Laser) during the formation of the oxide semiconductor thin film can directly block the heat transfer to the substrate, the laser (Laser The strong energy of) has the advantage that it is easy to secure the temperature required to form a thin film.
또한 본 발명의 실시 예에 따른 산화물 반도체 박막 및 산화물 반도체 박막 트랜지스터 형성 방법에 따르면, 산화물 반도체 박막의 형성 시 하프-톤 마스크(Half-tone mask)를 이용하여 채널 영역과 S/D 영역을 동시에 열처리함으로서 공정 시간 및 비용을 줄일 수 있는 이점이 있다.In addition, according to the method for forming the oxide semiconductor thin film and the oxide semiconductor thin film transistor according to an embodiment of the present invention, when forming the oxide semiconductor thin film using a half-tone mask (Half-tone mask) at the same time heat treatment of the channel region and the S / D region This has the advantage of reducing process time and costs.
도 1a 내지 도 1d는 본 발명의 제1 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a first embodiment of the present invention.
도 2는 본 발명의 제1 실시예에 적용된 기판 상에 증착된 절연막과 비정질 산화물 반도체 박막에 대해 파장에 따른 투과도의 변화를 나타낸 그래프이다.FIG. 2 is a graph showing a change in transmittance according to a wavelength of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
도 3은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프 및 평면 주사전자 현미경 사진이다.3 is a graph and a planar scanning electron micrograph showing the results of X-ray diffraction of the amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
도 4는 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막과 이에 대한 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다.FIG. 4 is a graph showing X-ray diffraction results of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention and nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature.
도 5는 본 발명의 제1 실시예에 적용된 기판 상에 증착된 절연막과 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막에 대해 파장에 따른 투과도의 변화를 나타낸 그래프이다.FIG. 5 is a graph showing a change in transmittance according to wavelength of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention.
도 6은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막과 나노 결정질 산화물 반도체 박막의 사진이다.6 is a photograph of an amorphous oxide semiconductor thin film and a nanocrystalline oxide semiconductor thin film applied to a first embodiment of the present invention.
도 7은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 평면 주사전자 현미경 사진이다.7 is a planar scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention.
도 8은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 단면 주사전자 현미경 사진이다.8 is a cross-sectional scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
도 9는 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리된 나노 결정질 산화물 반도체 박막의 원자빔 현미경 사진이다.9 is an atomic beam micrograph of a subsequently heat-treated nanocrystalline oxide semiconductor thin film of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention.
도 10a 내지 도 10f는 본 발명의 제2 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도이다.10A to 10F are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention.
도 11은 본 발명의 제2 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 산화화합물 졸 증착과 졸겔 공정의 반복 횟수에 따른 막의 두께 변화를 설명하기 위한 그래프이다.FIG. 11 is a graph illustrating a change in thickness of an oxide semiconductor thin film according to the number of repetitions of sol-gel deposition and sol-gel process of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention.
도 12는 본 발명의 제2 실시예에 적용된 나노 결정질 산화물 반도체 박막의 두께 변화에 따른 평면 주사현미경 사진이다.12 is a planar scanning microscope photograph according to the change in thickness of the nanocrystalline oxide semiconductor thin film applied in the second embodiment of the present invention.
도 13은 본 발명의 제2 실시예에 적용된 나노 결정질 산화물 반도체 박막의 두께 변화에 따른 단면 주사현미경 사진이다.FIG. 13 is a cross-sectional SEM image according to a change in thickness of the nanocrystalline oxide semiconductor thin film applied to the second embodiment of the present invention.
도 14는 본 발명의 제2 실시예에 적용된 비정질 산화물 반도체 박막의 두께에 따른 후속 열처리 후 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다.FIG. 14 is a graph showing X-ray diffraction results of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment according to the thickness of the amorphous oxide semiconductor thin film applied to the second embodiment of the present invention.
도 15는 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리 후 나노 결정질 산화물 반도체 박막의 평면 주사현미경 사진이다.15 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
도 16은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 1차 및 2차 후속 열처리 후 나노 결정질 산화물 반도체 박막의 평면 주사현미경 사진이다.16 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
도 17은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 1차 및 2차 후속 열처리 후 나노 결정질 산화물 반도체 박막의 단면 주사현미경 사진이다.17 is a cross-sectional scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxidized compound sol applied in the embodiment of the present invention.
도 18은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리 후 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다.FIG. 18 is a graph showing X-ray diffraction results of nanocrystalline oxide semiconductor thin films after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention.
도 19는 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리에 의한 나노 결정질 산화물 반도체 박막의 (008) 주 성장 방향의 상대적 피크의 세기 비교를 설명하기 위한 그래프이다.FIG. 19 is a graph for explaining a comparison of relative peak intensities of (008) main growth directions of a nanocrystalline oxide semiconductor thin film by subsequent heat treatment of an amorphous oxide semiconductor thin film according to the molar ratio of an oxide compound sol applied to an embodiment of the present invention. .
도 20a 내지 도 20e는 본 발명의 제3 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도이다.20A to 20E are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a third embodiment of the present invention.
도 21은 본 발명의 실시형태에 따른 플래쉬 메모리 소자의 단면도이다.21 is a cross-sectional view of a flash memory device according to an embodiment of the present invention.
도 22는 본 발명의 다른 실시형태에 따른 플래쉬 메모리 소자의 단면도이다.22 is a cross-sectional view of a flash memory device according to another embodiment of the present invention.
도 23은 본 발명의 실시형태에 따른 플래쉬 메모리 소자의 제조 방법을 설명하기 위한 단면도들이다.FIG. 23 is a cross-sectional view illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.
도 24는 본 발명의 다른 실시형태에 따른 플래쉬 메모리 소자의 제조 방법을 설명하기 위한 단면도들이다.24 is a cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment of the present invention.
도 25는 본 발명의 실시형태에 따른 3D 적층셀 구조의 플래쉬 메모리 소자의 단면도이다.25 is a cross-sectional view of a flash memory device having a 3D stacked cell structure according to an embodiment of the present invention.
도 26은 본 발명의 다른 실시형태에 따른 3D 적층셀 구조의 플래쉬 메모리 소자의 단면도이다. 26 is a cross-sectional view of a flash memory device having a 3D stacked cell structure according to another embodiment of the present invention.
도 27a 및 도 27b는 본 발명의 일 실시예에 따른 산화물 반도체 박막의 제조방법을 설명하기 위한 단면도이다.27A and 27B are cross-sectional views illustrating a method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention.
도 28a 내지 도 28e는 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법을 설명하기 위한 단면도로서, 바텀 게이트(Bottom Gate)방식을 적용한 구조이다.28A to 28E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a bottom gate method.
도 29a 내지 도 29e는 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법을 설명하기 위한 단면도로서, 톱 게이트(top Gate)방식을 적용한 구조이다.29A to 29E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a top gate method.
도 30 및 도 31은 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법이 적용된 액정표시장치의 백플레인구조를 설명하기 위한 평면도 및 단면도이다.30 and 31 are plan views and cross-sectional views illustrating a backplane structure of a liquid crystal display device to which a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention is applied.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세하게 설명한다. 그러나, 다음에 예시하는 본 발명의 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 본 발명의 실시예는 당업계에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되어 지는 것이다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.
액상 공정을 이용한 산화물 반도체 박막의 결정화 방법Crystallization Method of Oxide Semiconductor Thin Film Using Liquid Phase Process
투명 산화물 반도체(Transparent Oxide Semiconductor)를 박막 트랜지스터(Thin-Film Transistor, TFT)의 활성층으로 이용한 디스플레이 패널 제작 분야에서 많은 주목을 모으고 있다. 이는 기존의 비정질 실리콘(amorphous Silicon, a-Si), 저온 다결정 실리콘(Low Temperature Polycrystalline Silicon, LTPS) 혹은 유기(Organic) 박막 트랜지스터에 비해 상대적으로 우수한 성능을 보이기 때문이다. 또한, 박막의 투명한 특성을 이용한 투명 디스플레이로의 용이한 접근이 가능하다.Attention has been drawn in the field of display panel fabrication using a transparent oxide semiconductor as an active layer of a thin-film transistor (TFT). This is because it is relatively superior to conventional amorphous silicon (a-Si), low temperature polycrystalline silicon (LTPS) or organic thin film transistor. In addition, easy access to the transparent display using the transparent properties of the thin film is possible.
이러한 산화물 반도체 관련 연구는 1990년대부터 시작하여 많은 연구가 되어 왔으며 특히, 가시광 영역에서 높은 투과율 때문에 투명 박막 트랜지스터 응용 등에 연구가 활발히 진행 중이다. 이에 가장 주목받고 있는 산화물로는 아연산화물(ZnO)과 상기 산화물에 전이후 금속을 도핑한 비정질 산화물이다{참조문헌; Quan-Bao et al., “Structural, electrical, and optical properties of transparent conductive ZnO:Ga films prepared by DC reactive magnetron sputtering,” J. Cryst. Growth, 304, 64 (2007)}.These studies related to oxide semiconductors have been conducted since the 1990s, and especially, researches on transparent thin film transistor applications are being actively conducted due to high transmittance in the visible light region. The oxides that are attracting the most attention are zinc oxides (ZnO) and amorphous oxides doped with metals after transition to the oxides {reference; Quan-Bao et al. , “Structural, electrical, and optical properties of transparent conductive ZnO: Ga films prepared by DC reactive magnetron sputtering,” J. Cryst. Growth, 304, 64 (2007)}.
상기 아연산화물의 벌크(Bulk)의 이동도(Carrier Mobility)는 약 200 cm2/Vㆍs로{참조문헌; D. C. Look et al., “Electrical properties of bulk ZnO,” Solid State Commun., 105, 399 (1998)} 저온 다결정 실리콘의 100 cm2/Vㆍs 보다 높고, 비정질 인듐-갈륨-아연화합물으로 이루어진 산화화합물을 활성층으로 사용한 박막 트랜지스터(TFT)의 이동도는 약 1～120 cm2/Vㆍs로{참조문헌; H-N. Lee et al., J. Soc. Inf. Display, 16, 265 (2008)}, 비정질 실리콘 박막 트랜지스터의 특성 보다 월등하고, 다결정 실리콘 박막 트랜지스터와 대등하다.The carrier mobility of the zinc oxide is about 200 cm 2 / V · s {reference; DC Look et al. , “Electrical properties of bulk ZnO,” Solid State Commun., 105, 399 (1998)} Using an oxidizing compound composed of amorphous indium-gallium-zinc compound higher than 100 cm 2 / V · s of low-temperature polycrystalline silicon as an active layer The mobility of the thin film transistor TFT is about 1 to 120 cm 2 / V · s {reference; HN. Lee et al., J. Soc. Inf. Display, 16, 265 (2008)}, superior to the characteristics of amorphous silicon thin film transistors, and comparable to polycrystalline silicon thin film transistors.
이러한 비정질 인듐-갈륨-아연화합물로 이루어진 산화화합물(amorphous Indium-Gallium-Zinc Oxide, a-IGZO)은 일본 동경공업대학의 히데오 호소노 연구 그룹에서 최초 제안된 이래 LG Electronic, SAIT 등에서 플렉서블(Flexible) 유기발광 다이오드 패널 개발에 힘쓰고 있다. Amorphous Indium-Gallium-Zinc Oxide (a-IGZO), which is composed of amorphous indium-gallium-zinc compounds, has been flexible in LG Electronic and SAIT since it was first proposed by Hideo Hosono Research Group of Tokyo University of Technology. We are trying to develop organic light emitting diode panel.
기존의 유기 트랜지스터나 비정질 실리콘 트랜지스터에 비해 고 신뢰성 및 고 이동도 특성을 가지고 있으며, 저온 다결정 실리콘 트랜지스터 보다 균일성이 뛰어나기 때문이다. 또한, 기존의 실리콘 기반의 트랜지스터는 불투명하여 측정되는 빛의 양을 줄이기 때문에, 투명 산화막은 플렉서블 유기발광 다이오드 디스플레이의 구동 소자로 최적으로 대두 되고 있다.This is because it has higher reliability and higher mobility than conventional organic transistors or amorphous silicon transistors, and is more uniform than low temperature polycrystalline silicon transistors. In addition, since a conventional silicon-based transistor reduces the amount of light that is opaque and measured, the transparent oxide film is optimally used as a driving element of a flexible organic light emitting diode display.
한편, 상기와 같은 비정질 산화화합물을 증착하여 결정화시키는 방법으로는 대표적으로 스퍼터링(Sputtering)과 펄스드 레이저 증착(Pulsed Laser Deposition, PDL)과 같은 진공 증착법 등이 널리 사용되고 있다. 그러나, 기존의 스퍼터링 공정 과정에서는 높은 온도 결정화가 필요한 문제점이 있으며, 현재 상용되고 있는 스퍼터링 증착법을 이용한 인듐-갈륨-아연화합물로 이루어진 산화물 반도체 박막의 응용은 그 비정질 상으로 제한되어 있다. 이는 결정화 시 약 1000도 이상의 높은 온도에서의 열처리를 필요로 하고 있기 때문이다. 또한, 산화막의 결정질 막에 대한 광학적ㆍ구조적 특성에 대한 전반적인 인식이 부족한 실정이다.Meanwhile, as a method of depositing and crystallizing the amorphous oxide compound as described above, a vacuum deposition method such as sputtering and pulsed laser deposition (PDL) is widely used. However, there is a problem that high temperature crystallization is required in the existing sputtering process, and the application of the oxide semiconductor thin film made of indium-gallium-zinc compound using the sputter deposition method which is currently commercially available is limited to its amorphous phase. This is because the crystallization requires heat treatment at a high temperature of about 1000 degrees or more. In addition, there is a lack of general recognition of the optical and structural characteristics of the crystalline film of the oxide film.
이에 본 발명의 실시 예는 액상 공정에 기반을 둔 산화물 반도체 박막의 결정화 방법을 제공한다.Therefore, an embodiment of the present invention provides a crystallization method of an oxide semiconductor thin film based on a liquid phase process.
(제1 실시예)(First embodiment)
도 1a 내지 도 1d는 본 발명의 제1 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a first embodiment of the present invention.
도 1a를 참조하면, 기판(100) 상에 예컨대, 실리콘 산화막 또는 질화막 등으로 이루어진 절연막(110)을 형성한 후, 절연막(110) 상에 예컨대, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 이상의 산화화합물 졸(sol)(예컨대, 인듐-갈륨-아연 졸 등)(120)을 증착한다. 이때, 산화화합물 졸(120)은 예컨대, 스핀 코팅(Spin Coating) 또는 잉크젯 프린팅(Inkjet Printing)을 이용하여 증착함이 바람직하다. 한편, 기판(100) 상에 절연막(110)을 형성한 후, 기판(100)과 산화화합물 졸(120)의 안정적인 결합 향상을 위하여 예컨대, 플라즈마(Plasma) 혹은 용액처리를 수행하여 친수성 및 소수성 기판을 형성함이 바람직하다.Referring to FIG. 1A, after an insulating film 110 made of, for example, a silicon oxide film or a nitride film is formed on a substrate 100, for example, a zinc compound, an indium compound, a gallium compound, a tin compound, and the like are formed on the insulating film 110. At least one oxide compound sol (eg, indium-gallium-zinc sol, etc.) 120 selected from the group consisting of tantalum compounds is deposited. In this case, the oxide sol 120 may be deposited using, for example, spin coating or inkjet printing. On the other hand, after forming the insulating film 110 on the substrate 100, in order to improve the stable bonding of the substrate 100 and the oxide compound sol 120, for example, by performing a plasma (Plasma) or solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
도 1b를 참조하면, 제1 열처리 공정을 통해 산화화합물 졸(120)을 건조 및 가열하여 산화화합물 겔(gel)(130)로 형성한다. 이때, 상기 제1 열처리 공정은 산화화합물 졸(120)에 포함되어 있는 용매(solvent)와 안정제(stabilizer)들을 증발시키고 각 화합물의 화학적 분해를 도와주는 역할을 수행한다.Referring to FIG. 1B, an oxide compound sol 120 is dried and heated through a first heat treatment process to form an oxide compound gel 130. In this case, the first heat treatment process serves to evaporate the solvents and stabilizers included in the oxide compound sol 120 and to help chemically decompose each compound.
이러한 상기 제1 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행함이 바람직하며, 상기의 용매(solvent)와 안정제(stabilizer)들이 증발되는 약 250℃ 내지 450℃ 범위(바람직하게는, 약 350℃ 정도)이하로 약 1시간이하 동안 수행함이 바람직하다.The first heat treatment process is preferably performed so that the temperature is changed according to the treatment time, and the solvent and stabilizers are in the range of about 250 ° C. to 450 ° C. (preferably, about 350 ° C.). Preferably for about 1 hour or less.
도 1c를 참조하면, 제2 열처리 공정을 통해 산화화합물 겔(130)을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막(140)을 형성한다.Referring to FIG. 1C, the oxidized compound gel 130 is dried and heated through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film 140.
이때, 상기 제2 열처리 공정은 화합물에 포함된 유기적(organic) 성분들이 다 증발되어 산화막 반도체로 이루어지게 하는 역할을 수행한다. 이러한 상기 제2 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행함이 바람직하며, 유기적(organic) 성분들이 다 증발되는 온도인 약 600℃ 내지 800℃ 범위(바람직하게, 약 700℃ 정도)이하로 약 24시간이하 동안 수행함이 바람직하다.In this case, the second heat treatment process serves to make the organic components included in the compound evaporate to the oxide semiconductor. The second heat treatment process is preferably carried out to change the temperature according to the treatment time, about 600 ℃ to 800 ℃ range (preferably, about 700 ℃) or less temperature that the organic components are all evaporated It is preferable to carry out for 24 hours or less.
도 1d를 참조하면, 제3 열처리 공정을 통해 불투명 비정질 반도체 박막(140)을 건조 및 가열하여 투명 결정질 산화물 반도체 박막(150)을 형성한다. 이때, 상기 제3 열처리 공정은 비정질 상의 막을 투명한 나노 결정질 상의 막으로 이루어지게 하는 역할을 수행한다. 이러한 상기 제3 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행함이 바람직하며, 약 900℃ 내지 1100℃ 범위(바람직하게, 약 1000℃ 정도)이하로 약 24시간이하 동안 수행함이 바람직하다.Referring to FIG. 1D, the opaque amorphous semiconductor thin film 140 is dried and heated through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film 150. At this time, the third heat treatment process serves to make the amorphous phase film made of a transparent nanocrystalline film. The third heat treatment process is preferably performed to change the temperature according to the treatment time, it is preferable to perform for about 24 hours or less in the range of about 900 ℃ to 1100 ℃ (preferably, about 1000 ℃).
한편, 상기 제1 내지 제3 열처리 공정은 예컨대, 핫 플레이트(Hot Plate)에서 열처리하는 공정, 도가니(Furnace)에서 장시간 열처리하는 공정, 온도를 급격히 변화시키는 급속 열처리(Rapid Thermal Annealing, RTA)에서 열처리하는 공정, 또는 펄스드 급속 열처리(Pulsed RTA)에서 열처리하는 공정 중에서 선택된 어느 하나의 열처리 공정을 이용함이 바람직하다.Meanwhile, the first to third heat treatment processes include, for example, a heat treatment process in a hot plate, a heat treatment process in a crucible for a long time, and a heat treatment in a rapid thermal annealing (RTA) to rapidly change the temperature. It is preferable to use any one of the heat treatment process selected from the process, or the process of heat treatment in the pulsed rapid heat treatment (Pulsed RTA).
도 2는 본 발명의 제1 실시예에 적용된 기판 상에 증착된 절연막과 비정질 산화물 반도체 박막에 대해 파장에 따른 투과도의 변화를 나타낸 그래프이다. 도 2를 참조하면, 예컨대, 유리 기판(100, 도 1a 참조) 상에 증착된 절연막(110, 도 1a 참조) 즉, 실리콘 산화막(가)과 산화화합물 겔(예컨대, 인듐-갈륨-아연 겔)(130, 도 1b 참조)을 건조한 후 약 275℃ 정도에서 열처리된 박막(나) 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)의 파장에 따른 투과도를 나타낸 것으로, 상기 열처리된 박막(나)은 반투명하다는 것을 확인할 수 있다.FIG. 2 is a graph showing a change in transmittance according to a wavelength of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention. Referring to FIG. 2, for example, an insulating film 110 (see FIG. 1A) deposited on a glass substrate 100 (see FIG. 1A), that is, a silicon oxide film (a) and an oxide compound gel (eg, indium-gallium-zinc gel) (B) (130, FIG. 1b) shows the transmittance according to the wavelength of the thin film (b), that is, the amorphous oxide semiconductor thin film (140, see FIG. 1c) heat-treated at about 275 ℃, the heat-treated thin film (b) You can see that is translucent.
도 3은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프 및 평면 주사전자 현미경 사진이다. 도 3을 참조하면, 산화화합물 겔(예컨대, 인듐-갈륨-아연 겔)(120, 도 1b 참조)을 건조한 후 약 275℃ 정도에서 열처리된 박막 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)의 X-선 회절 결과로 결정 피크가 없는 비정질 상의 박막임을 확인할 수 있으며, 이에 삽입된 주사전자 현미경 사진에서도 아무런 결정립을 찾을 수 없음을 확인할 수 있다.3 is a graph and a planar scanning electron micrograph showing the results of X-ray diffraction of the amorphous oxide semiconductor thin film applied in the first embodiment of the present invention. Referring to FIG. 3, after drying the oxidized compound gel (eg, indium-gallium-zinc gel) 120 (see FIG. 1B) and heat-treated at about 275 ° C., that is, an amorphous oxide semiconductor thin film 140 (see FIG. 1C) X-ray diffraction results of the amorphous phase of the thin film without a crystal peak, it can be confirmed that no grains can be found in the scanning electron micrograph inserted therein.
도 4는 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막과 이에 대한 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다. 도 4를 참조하면, 산화화합물 겔(예컨대, 인듐-갈륨-아연 겔)(120, 도 1b 참조)을 건조한 후 약 275℃ 정도에서 열처리된 박막(가) 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)과 이에 대한 후속 열처리 온도에 따른 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(나～마) 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 X-선 회절 결과로 그 열처리 온도는 (나) 300℃, (다) 350℃, (라) 400℃, (마) 450℃이고, 약 1시간 동안 상압에서 열처리하였다. FIG. 4 is a graph showing X-ray diffraction results of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention and nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature. Referring to FIG. 4, a thin film heat-treated at about 275 ° C. after drying an oxidized compound gel (eg, indium-gallium-zinc gel) 120 (see FIG. 1B), that is, an amorphous oxide semiconductor thin film 140 (FIG. 1c) and the subsequent heat treatment as a result of X-ray diffraction of the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film (B), that is, the transparent crystalline oxide semiconductor thin film (150, see FIG. 1D). The temperature was (b) 300 ° C., (c) 350 ° C., (d) 400 ° C., and (e) 450 ° C. and heat-treated at atmospheric pressure for about 1 hour.
여기서, 약 275℃ 정도에서 열처리한 (가)의 비정질 산화물 반도체 박막을 제외한 약 300℃ 이상의 열처리 온도에서 인듐-갈륨-아연 산화화합물 반도체 박막(나～마)의 경우, 결정립에 의한 피크를 보이고 있으며, 그 피크의 위치에 따라 결정화된 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(나～마)은 InGaO3(ZnO)n(n=2)의 상이다. 그 열처리 온도가 증가함에 따라서 그 피크의 세기도 증가하며, 피크의 반측도(Full Width at Half Maximum; FWHM)도 감소함을 확인할 수 있다.In the case of the indium-gallium-zinc oxide compound semiconductor thin film (N-MA) at a heat treatment temperature of about 300 ° C. or more except for the (a) amorphous oxide semiconductor thin film heat-treated at about 275 ° C., a peak due to crystal grains is shown. And the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film (na-ma) crystallized according to the position of the peak is a phase of InGaO 3 (ZnO) n (n = 2). It can be seen that as the heat treatment temperature increases, the intensity of the peak increases and the full width at half maximum (FWHM) of the peak decreases.
도 5는 본 발명의 제1 실시예에 적용된 기판 상에 증착된 절연막과 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막에 대해 파장에 따른 투과도의 변화를 나타낸 그래프이다. 도 5를 참조하면, 예컨대, 유리 기판(100, 도 1a 참조) 상에 증착된 절연막(110, 도 1a 참조) 즉, 실리콘 산화막(가)과 비정질 인듐-갈륨-아연 산화화합물 반도체 박막(나) 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)의 후속 열처리 온도에 따른 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(다～바) 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 파장에 따른 투과도의 변화를 나타낸 것으로서, 그 열처리 온도는 (다) 300℃, (라) 350℃, (마) 400℃, (바) 450℃이고, 약 1시간 동안 상압에서 열처리하였다. 여기서, 비정질 인듐-갈륨-아연 산화화합물 반도체 박막(나)을 제외하고, 약 300℃ 이상의 열처리에서 그 투과도가 크게 향상되고 있음을 확인할 수 있으며, 열처리 온도가 증가함에 따라 투과도 또한 향상됨을 확인할 수 있다.FIG. 5 is a graph showing a change in transmittance according to wavelength of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an insulating film and an amorphous oxide semiconductor thin film deposited on a substrate applied to a first embodiment of the present invention. Referring to FIG. 5, for example, an insulating film 110 (see FIG. 1A) deposited on a glass substrate 100 (see FIG. 1A), that is, a silicon oxide film (a) and an amorphous indium-gallium-zinc oxide compound semiconductor thin film (b) That is, the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film (C-bar) according to the subsequent heat treatment temperature of the amorphous oxide semiconductor thin film 140 (see FIG. 1C), that is, the transparent crystalline oxide semiconductor thin film 150 (see FIG. 1D) As the change in transmittance according to the wavelength, the heat treatment temperature is (C) 300 ℃, (D) 350 ℃, (E) 400 ℃, (bar) 450 ℃, heat treatment at atmospheric pressure for about 1 hour. Here, except for the amorphous indium-gallium-zinc oxide compound semiconductor thin film (b), it can be seen that the transmittance is greatly improved at a heat treatment of about 300 ° C. or higher, and the transmittance is also improved as the heat treatment temperature is increased. .
도 6은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막과 나노 결정질 산화물 반도체 박막의 사진이다. 도 6을 참조하면, 예컨대, 비정질 인듐-갈륨-아연 산화화합물 박막(가) 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)과 약 450℃ 열처리된 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(나) 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 사진으로서, 그 결정화 유무에 따른 투과도의 차이를 볼 수 있다.6 is a photograph of an amorphous oxide semiconductor thin film and a nanocrystalline oxide semiconductor thin film applied to a first embodiment of the present invention. Referring to FIG. 6, for example, an amorphous indium-gallium-zinc oxide thin film (i), that is, a nanocrystalline indium-gallium-zinc oxide semiconductor thin film heat treated at about 450 ° C. with an amorphous oxide semiconductor thin film 140 (see FIG. 1C). (B) In other words, as a photograph of the transparent crystalline oxide semiconductor thin film 150 (refer to FIG. 1D), a difference in transmittance with or without crystallization can be seen.
도 7은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 평면 주사전자 현미경 사진이다. 도 7을 참조하면, 예컨대, 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)의 후속 열처리 온도에 따른 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(가～라) 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 평면 주사전자 현미경 사진으로서, 그 열처리 온도는 (가) 300℃, (나) 350℃, (다) 400℃, (라) 450℃이고, 약 1시간 동안 상압에서 열처리하였다.7 is a planar scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied to a first embodiment of the present invention. Referring to FIG. 7, for example, an amorphous indium-gallium-zinc oxide semiconductor thin film, that is, a nanocrystalline indium-gallium-zinc oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film 140 (see FIG. 1C) That is, the planar scanning electron micrograph of the transparent crystalline oxide semiconductor thin film 150 (refer FIG. 1D), The heat-treatment temperature is (a) 300 degreeC, (b) 350 degreeC, (c) 400 degreeC, (d) It was 450 ° C and heat-treated at atmospheric pressure for about 1 hour.
여기서, 전술한 X-선 회절 결과와 같이 열처리 온도가 증가함에 따라 나노 결정립의 크기가 수십 nm 정도가 증가함을 확인할 수 있으며, 그 결정립의 모양 또한 분명해지고 있다.Here, as shown in the X-ray diffraction results described above, as the heat treatment temperature increases, the size of the nano-crystals increases by several tens of nm, and the shape of the crystals is also clear.
도 8은 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리 온도에 따른 나노 결정질 산화물 반도체 박막의 단면 주사전자 현미경 사진이다. 도 8을 참조하면, 예컨대, 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)의 후속 열처리 온도에 따른 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막(가～라) 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 단면 주사전자 현미경 사진으로서, 그 열처리 온도는 (가) 300℃, (나) 350℃, (다) 400℃, (라) 450℃이고, 약 1시간 동안 상압에서 열처리하였다.8 is a cross-sectional scanning electron micrograph of a nanocrystalline oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention. Referring to FIG. 8, for example, an amorphous indium-gallium-zinc oxide semiconductor thin film, that is, a nanocrystalline indium-gallium-zinc oxide semiconductor thin film according to a subsequent heat treatment temperature of an amorphous oxide semiconductor thin film 140 (see FIG. 1C) That is, the cross-sectional scanning electron micrograph of the transparent crystalline oxide semiconductor thin film 150 (refer FIG. 1D), The heat processing temperature is (A) 300 degreeC, (B) 350 degreeC, (C) 400 degreeC, (D) It was 450 ° C and heat-treated at atmospheric pressure for about 1 hour.
여기서, 전술한 평면 주사전자 현미경 사진의 결과와 일치하게 단면의 사진에서도 열처리 온도가 증가함에 따라서 나노 결정립의 높이가 수십 nm 정도가 증가하고 있으며 그 모양 또한 분명해지고 있다.Here, in accordance with the results of the above-mentioned planar scanning electron micrograph, as the heat treatment temperature increases in the cross-sectional photograph, the height of the nano-crystal grains is increased by several tens of nm, and the shape thereof becomes clear.
또한, 전술한 X-선 회절과 평면-단면 주사전자 현미경 사진의 결과가 일치하는 경향을 보이고 있으며, 약 300℃ 정도의 낮은 열처리 온도에서 나노 결정립의 인듐-갈륨-아연 산화화합물 반도체 박막이 결정화됨을 확인할 수 있다.In addition, the above-described results of X-ray diffraction and planar cross-sectional scanning electron micrographs tend to coincide with each other. You can check it.
도 9는 본 발명의 제1 실시예에 적용된 비정질 산화물 반도체 박막의 후속 열처리된 나노 결정질 산화물 반도체 박막의 원자빔 현미경 사진이다. 도 9를 참조하면, 예컨대, 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140, 도 1c 참조)을 약 450℃ 정도로 후속 열처리된 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 투명 결정질 산화물 반도체 박막(150, 도 1d 참조)의 원자빔 현미경 사진으로서, 그 표면의 거칠기가 약 1.2nm로 기존의 펄스드 레이저 증착된 비정질 인듐-갈륨-아연 산화화합물 반도체 박막의 표면 거칠기에 비하여 향상된 특성을 보이고 있다.9 is an atomic beam micrograph of a subsequently heat-treated nanocrystalline oxide semiconductor thin film of an amorphous oxide semiconductor thin film applied in the first embodiment of the present invention. Referring to FIG. 9, for example, an amorphous indium-gallium-zinc oxide semiconductor thin film, that is, an amorphous crystalline indium-gallium-zinc oxide semiconductor thin film that is subsequently heat treated to about 450 ° C. That is, as an atomic beam micrograph of the transparent crystalline oxide semiconductor thin film 150 (see FIG. 1D), the surface roughness of the amorphous indium-gallium-zinc oxide compound semiconductor thin film conventionally pulsed laser deposited with a roughness of about 1.2 nm. Compared with the improved characteristics.
(제2 실시예)(2nd Example)
도 10a 내지 도 10f는 본 발명의 제2 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도로서, 액상제조 기반의 산화물(예컨대, 인듐-갈륨-아연 등) 반도체 박막의 두께를 증가시키기 위한 실시예이다.10A to 10F are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention, and a liquid phase based oxide (eg, indium-gallium-zinc, etc.) semiconductor thin film An embodiment for increasing the thickness of.
도 10a를 참조하면, 기판(100) 상에 예컨대, 실리콘 산화막 또는 질화막 등으로 이루어진 절연막(110)을 형성한 후, 절연막(110) 상에 예컨대, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 이상의 산화화합물 졸(sol)(예컨대, 인듐-갈륨-아연 졸 등)(120)을 증착한다. 이때, 산화화합물 졸(120)은 예컨대, 스핀 코팅(Spin Coating) 또는 잉크젯 프린팅(Inkjet Printing) 등을 이용하여 증착함이 바람직하다.Referring to FIG. 10A, after the insulating film 110 formed of, for example, a silicon oxide film or a nitride film is formed on the substrate 100, for example, a zinc compound, an indium compound, a gallium compound, a tin compound, and the like are formed on the insulating film 110. At least one oxide compound sol (eg, indium-gallium-zinc sol, etc.) 120 selected from the group consisting of tantalum compounds is deposited. In this case, the oxide compound sol 120 is preferably deposited using, for example, spin coating or inkjet printing.
한편, 기판(100) 상에 절연막(110)을 형성한 후, 기판(100)과 산화화합물 졸(120)의 안정적인 결합 향상을 위하여 예컨대, 플라즈마(Plasma) 혹은 용액처리를 수행하여 친수성 및 소수성 기판을 형성함이 바람직하다.On the other hand, after forming the insulating film 110 on the substrate 100, in order to improve the stable bonding of the substrate 100 and the oxide compound sol 120, for example, by performing a plasma (Plasma) or a solution treatment hydrophilic and hydrophobic substrate It is preferable to form.
도 10b를 참조하면, 제1 열처리 공정을 통해 산화화합물 졸(120)을 건조 및 가열하여 산화화합물 겔(gel)(130)로 형성한다. 이때, 상기 제1 열처리 공정은 산화화합물 졸(120)에 포함되어 있는 용매(solvent)와 안정제(stabilizer)들을 증발시키고 각 화합물의 화학적 분해를 도와주는 역할을 수행한다.Referring to FIG. 10B, the oxide sol 120 is dried and heated through a first heat treatment process to form an oxide compound gel 130. In this case, the first heat treatment process serves to evaporate the solvents and stabilizers included in the oxide compound sol 120 and to help chemically decompose each compound.
이러한 상기 제1 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행함이 바람직하며, 상기의 용매(solvent)와 안정제(stabilizer)들이 증발되는 약 250℃ 내지 450℃ 범위(바람직하게는, 약 350℃ 정도)이하로 약 1시간이하 동안 수행함이 바람직하다.The first heat treatment process is preferably performed so that the temperature is changed according to the treatment time, and the solvent and stabilizers are in the range of about 250 ° C. to 450 ° C. (preferably, about 350 ° C.). Preferably for about 1 hour or less.
도 10c를 참조하면, 산화화합물 겔(130) 상에 전술한 도 10a에 도시된 바와 같이 예컨대, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 이상의 산화화합물 졸(예컨대, 인듐-갈륨-아연 졸 등)(120‘)을 예컨대, 스핀 코팅(Spin Coating) 또는 잉크젯 프린팅(Inkjet Printing) 등을 이용하여 다시 증착한다.Referring to FIG. 10C, at least one oxide compound selected from the group consisting of, for example, zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds, as shown in FIG. 10A, described above on the oxidized compound gel 130. The sol (eg, indium-gallium-zinc sol, etc.) 120 ′ is deposited again using, for example, spin coating or inkjet printing.
도 10d를 참조하면, 산화화합물 겔(130) 상에 형성된 산화화합물 졸(120‘)을 전술한 상기 제1 열처리 공정을 다시 수행하여 산화화합물 졸(120‘)을 건조 및 가열하여 산화화합물 겔(130’)로 형성한다.Referring to FIG. 10D, the oxide sol 120 ′ formed on the oxide gel 130 is again subjected to the aforementioned first heat treatment process to dry and heat the oxide sol 120 ′. 130 ').
도 10e를 참조하면, 전술한 상기 제2 열처리 공정을 통해 산화화합물 겔(130)(130')을 건조 및 가열하여 전술한 제1 실시예의 불투명 비정질 산화물 반도체 박막(140)보다 약 두 배로 두꺼워진 불투명 비정질 산화물 반도체 박막(140‘)을 형성한다.Referring to FIG. 10E, the oxide gels 130 and 130 ′ are dried and heated through the above second heat treatment process to be about twice as thick as the opaque amorphous oxide semiconductor thin film 140 of the first embodiment. An opaque amorphous oxide semiconductor thin film 140 'is formed.
도 10f를 참조하면, 전술한 상기 제3 열처리 공정을 통해 불투명 비정질 반도체 박막(140‘)을 건조 및 가열하여 두꺼워진 투명 결정질 산화물 반도체 박막(150’)을 형성한다.Referring to FIG. 10F, the opaque amorphous semiconductor thin film 140 ′ is dried and heated through the third heat treatment process to form a thick transparent crystalline oxide semiconductor thin film 150 ′.
전술한 바와 같이, 산화화합물 졸의 증착 및 졸겔(sol-gel) 공정의 반복을 통하여 효과적으로 액상제조 기반의 산화물 반도체 박막의 두께를 조절할 수 있다.As described above, it is possible to effectively control the thickness of the liquid-based oxide semiconductor thin film through the deposition of the oxide compound sol and the sol-gel process.
도 11은 본 발명의 제2 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 산화화합물 졸 증착과 졸겔 공정의 반복 횟수에 따른 막의 두께 변화를 설명하기 위한 그래프이다. 도 11을 참조하면, 본 발명의 제2 실시예에 따른 액상제조 기반의 산화물 반도체 박막의 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸 증착과 졸겔 공정의 반복 횟수와 이에 따른 인듐-갈륨-아연화합물 반도체 박막 즉, 투명 결정질 산화물 반도체 박막(150‘, 도 10f 참조)의 두께 관계로, 1회 증착 시 그 두께가 약 100nm 정도로 증착된 이후 그 졸겔 공정의 반복 횟수와 비례하여 박막의 두께가 증가함을 확인할 수 있다.FIG. 11 is a graph illustrating a change in thickness of an oxide semiconductor thin film according to the number of repetitions of sol-gel deposition and sol-gel process of an oxide semiconductor thin film using a liquid phase manufacturing base according to a second embodiment of the present invention. Referring to FIG. 11, an oxide compound (eg, indium-gallium-zinc, etc.) of the liquid crystal-based oxide semiconductor thin film according to the second embodiment of the present invention may be repeatedly subjected to sol deposition and sol-gel processes, and thus indium-gallium- According to the thickness of the zinc compound semiconductor thin film, that is, the transparent crystalline oxide semiconductor thin film (150 ', see FIG. 10F), the thickness of the thin film is proportional to the number of repetitions of the sol-gel process after the thickness of about 100 nm is deposited in one deposition. You can see the increase.
도 12는 본 발명의 제2 실시예에 적용된 나노 결정질 산화물 반도체 박막의 두께 변화에 따른 평면 주사현미경 사진이다. 도 12를 참조하면, 본 발명의 제2 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸겔 공정의 반복 횟수 및 그 두께에 따른 약 450℃ 후속 열처리 후 나노 결정질 산화물 반도체 박막(150‘, 도 10f 참조)의 평면 주사현미경 사진으로 그 두께는 (가) 100nm, (나) 140nm, (다) 170nm, (라) 300nm 이다. 즉, 두께가 증가함에 따라 나노 결정질의 크기가 조금씩 증가하는 경향을 보이고 있다.12 is a planar scanning microscope photograph according to the change in thickness of the nanocrystalline oxide semiconductor thin film applied in the second embodiment of the present invention. Referring to FIG. 12, the nanocrystalline oxide semiconductor thin film 150 after subsequent heat treatment at about 450 ° C. according to the number of repetitions of the oxidizing compound (eg, indium-gallium-zinc, etc.) sol-gel process and the thickness thereof applied in the second embodiment of the present invention (150) 10F), the thickness of which is (a) 100 nm, (b) 140 nm, (c) 170 nm, and (d) 300 nm. In other words, as the thickness increases, the size of the nanocrystals tends to increase little by little.
도 13은 본 발명의 제2 실시예에 적용된 나노 결정질 산화물 반도체 박막의 두께 변화에 따른 단면 주사현미경 사진이다.FIG. 13 is a cross-sectional SEM image according to a change in thickness of the nanocrystalline oxide semiconductor thin film applied to the second embodiment of the present invention.
도 13을 참조하면, 본 발명의 제2 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸겔 공정의 반복 횟수 및 그 두께에 따른 약 450℃ 후속 열처리 후 나노 결정질 산화물 반도체 박막(150‘, 도 10f 참조)의 단면 주사현미경 사진으로 그 두께는 (가) 100nm, (나) 170nm, (다) 300nm 이다. 즉, 졸겔 공정의 반복을 통하여 나노 결정질 산화물 반도체 박막(150‘)의 두께를 효과적으로 증가시킬 수 있으며, 연속 증착에 따른 적층된 막과 막 사이에 경계면이 존재하지 않는 것을 확인할 수 있다. 또한, 평면 주사전자 현미경의 결과와 일치하게 나노 결정질 산화물 반도체 박막(150‘)의 두께가 증가함에 따라서 그 결정립의 크기가 조금 증가하였다.Referring to FIG. 13, the nanocrystalline oxide semiconductor thin film 150 after subsequent heat treatment at about 450 ° C. according to the number of repetitions of the oxidizing compound (eg, indium-gallium-zinc, etc.) sol-gel process and the thickness thereof applied in the second embodiment of the present invention (150) 10F), the thickness of which is (a) 100 nm, (b) 170 nm, and (c) 300 nm. That is, the thickness of the nanocrystalline oxide semiconductor thin film 150 ′ may be effectively increased by repeating the sol-gel process, and it may be confirmed that no interface exists between the stacked film and the film due to continuous deposition. In addition, in accordance with the results of the planar scanning electron microscope, as the thickness of the nanocrystalline oxide semiconductor thin film 150 ′ increased, the grain size slightly increased.
도 14는 본 발명의 제2 실시예에 적용된 비정질 산화물 반도체 박막의 두께에 따른 후속 열처리 후 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다. 도 14를 참조하면, 예컨대, 비정질 인듐-갈륨-아연 산화화합물 반도체 박막(가) 즉, 비정질 산화물 반도체 박막(140‘, 도 10e 참조)의 두께에 따른 약 450℃ 후속 열처리 후, 나노 결정질 산화물 반도체 박막(나～마)(150‘, 도 10f 참조)의 X-선 회절 결과이다. 막의 두께는 (가) 100nm, (나) 100nm, (다) 140nm, (라) 170nm, (마) 300nm 이다.FIG. 14 is a graph showing X-ray diffraction results of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment according to the thickness of the amorphous oxide semiconductor thin film applied to the second embodiment of the present invention. Referring to FIG. 14, for example, an amorphous indium-gallium-zinc oxide compound semiconductor thin film (i.e., a nanocrystalline oxide semiconductor after subsequent heat treatment at about 450 ° C. depending on the thickness of the amorphous oxide semiconductor thin film 140 '(see FIG. 10E)). It is the X-ray diffraction result of thin film (b ~ ma) (150 ', see FIG. 10F). The thickness of the film is (a) 100 nm, (b) 100 nm, (c) 140 nm, (d) 170 nm, and (e) 300 nm.
즉, 막의 두께의 증가에 따른 결정립 피크가 증가하는 경향이 있으며, 이는 주사전자 현미경의 결과와 일치하는 경향을 보이고 있다. 또한, 막의 두께의 증가에 따른 결정립 피크의 이동(shift)이 없는 것으로 보아서, 막의 스트레스(stress)를 받지 않고 있음을 확인할 수 있다.That is, the grain peak tends to increase as the thickness of the film increases, which tends to match the result of the scanning electron microscope. In addition, it can be seen that there is no shift of the grain peak according to the increase of the thickness of the film, so that the film is not subjected to stress.
도 15는 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리 후 나노 결정질 산화물 반도체 박막의 평면 주사현미경 사진이다. 도 15를 참조하면, 본 발명의 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸(120,120‘,120“, 도 1a, 도 10a, 도 10c 및 도 20b 참조)의 인듐 몰비에 따른 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140,140‘,140", 도 1c, 도 10e 및 도 20d 참조)의 약 450℃ 후속 열처리 후 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 나노 결정질 산화물 반도체 박막(150,150‘,150", 도 1d, 도 10f 및 도 20e 참조)의 평면 주사현미경 사진으로서, 상기 산화화합물 졸의 몰비는 (가) 인듐:갈륨:아연 (1:1:2), (나) 인듐:갈륨:아연 (2:1:2), (다) 인듐:갈륨:아연 (3:1:2) 이다.15 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention. Referring to FIG. 15, the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol (120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B) applied to an embodiment of the present invention is shown. Nanocrystalline indium-gallium-zinc oxide compound thin film, that is, amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E and 20D) after subsequent heat treatment at about 450 ° C. A planar scanning micrograph of a semiconductor thin film, ie, a nanocrystalline oxide semiconductor thin film (150,150 ', 150 ", see FIGS. 1D, 10F, and 20E), wherein the molar ratio of the oxide compound sol is (a) indium: gallium: zinc (1). : 1: 2), (b) indium: gallium: zinc (2: 1: 2), (c) indium: gallium: zinc (3: 1: 2).
즉, 인듐 몰비가 증가함에 따라서 약 450℃ 후속 열처리된 막의 결정립의 크기는 거이 비슷하지만, 화살표로 표기된 공핍(void)이 인듐 몰비가 2이상의 경우 나타나는 것을 확인할 수 있다.That is, as the indium molar ratio increases, the grain size of the film after the heat treatment of about 450 ° C. is about the same, but it can be seen that the void indicated by the arrow appears when the indium molar ratio is 2 or more.
도 16은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 1차 및 2차 후속 열처리 후 나노 결정질 산화물 반도체 박막의 평면 주사현미경 사진이다. 도 16을 참조하면, 본 발명의 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸(120,120‘,120", 도 1a, 도 10a, 도 10c 및 도 20b 참조)의 인듐 몰비에 따른 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140,140‘,140", 도 1c, 도 10e 및 도 20d 참조)의 약 450℃ 1차 후속 열처리 후, 약 700℃ 2차 후속 열처리 후, 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 나노 결정질 산화물 반도체 박막(150,150‘,150", 도 1d, 도 10f 및 도 20e 참조)의 평면 주사현미경 사진으로서, 상기 산화화합물 졸의 몰비는 (가) 인듐:갈륨:아연 (1:1:2), (나) 인듐:갈륨:아연 (2:1:2), (다) 인듐:갈륨:아연 (3:1:2) 이다.16 is a planar scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention. Referring to FIG. 16, the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol (120,120 ', 120 ", FIG. 1A, FIG. 10A, 10C, and 20B) applied to an embodiment of the present invention is shown. According to the amorphous indium-gallium-zinc oxide compound thin film, that is, the amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E, and 20D) after about 450 ° C primary first heat treatment, about 700 ° C secondary second After the heat treatment, a planar scanning microscope image of the nanocrystalline indium-gallium-zinc oxide semiconductor thin film, that is, the nanocrystalline oxide semiconductor thin film (150,150 ', 150 ", see FIGS. 1D, 10F, and 20E). The molar ratios are: (a) Indium: Gallium: Zinc (1: 1: 2), (b) Indium: Gallium: Zinc (2: 1: 2), (C) Indium: Gallium: Zinc (3: 1: 2) .
즉, 인듐의 몰비가 증가할수록 그 결정립의 모양이 둥근 모양으로 변하고 있으면, 화살표로 표기된 공핍(void)이 증가함을 알 수 있다.That is, it can be seen that as the molar ratio of indium increases, the shape of the crystal grains changes to a round shape, and the void represented by the arrow increases.
도 17은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 1차 및 2차 후속 열처리 후 나노 결정질 산화물 반도체 박막의 단면 주사현미경 사진이다. 도 17을 참조하면, 본 발명의 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸(120,120‘,120", 도 1a, 도 10a, 도 10c 및 도 20b 참조)의 인듐 몰비에 따른 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140,140‘,140", 도 1c, 도 10e 및 도 20d 참조)의 약 450℃ 후속 열처리 후, 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 나노 결정질 산화물 반도체 박막(150,150‘,150", 도 1d, 도 10f 및 도 20e 참조)의 단면 주사현미경 사진(가)과, 약 450℃ 1차 후속 열처리 후, 약 700℃ 2차 후속 열처리 후, 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막의 단면 주사현미경 사진(나～라)으로서, 상기 산화화합물 졸의 몰비는 (가, 나) 인듐:갈륨:아연 (1:1:2), (다) 인듐:갈륨:아연 (2:1:2), (라) 인듐:갈륨:아연 (3:1:2) 이다.17 is a cross-sectional scanning microscope photograph of a nanocrystalline oxide semiconductor thin film after the first and second subsequent heat treatments of the amorphous oxide semiconductor thin film according to the molar ratio of the oxidized compound sol applied in the embodiment of the present invention. Referring to FIG. 17, the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol (120,120 ', 120 ", FIG. 1A, FIG. 10A, 10C, and 20B) applied to an embodiment of the present invention is shown. Nanocrystalline indium-gallium-zinc oxide after subsequent heat treatment of the amorphous indium-gallium-zinc oxide compound semiconductor thin film, that is, the amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E and 20D). A cross-sectional scanning micrograph of the compound semiconductor thin film, ie, the nanocrystalline oxide semiconductor thin film (150,150 ', 150 ", see FIGS. 1D, 10F, and 20E), and about 450 ° C. after the first subsequent heat treatment, about 700 ° C. 2 After the subsequent heat treatment, a cross-sectional scanning micrograph of the nanocrystalline indium-gallium-zinc oxide semiconductor thin film (b), wherein the molar ratio of the oxide compound sol is (a, b) indium: gallium: zinc (1: 1: 2), (c) indium: gallium: zinc (2: 1: 2), and (d) indium: gallium: zinc (3: 1: 2).
즉, 인듐 몰비가 증가함에 따라서 약 450℃ 열처리된 나노 결정질 반도체 박막(150,150‘,150")의 경우 그 단면에서의 인듐 몰비에 따른 큰 차이가 없으면 이는 평면 주사전자 현미경 결과와 일치한다. 또한, 약 450℃ 1차 후속 열처리 후, 약 700℃ 2차 후속 열처리 약 10초 동안 3회 반복을 통하여 펄스드 급속 열처리한 막의 경우, 인듐 몰비에 따른 큰 차이를 보이고 있다. 인듐 몰비가 증가함에 따라서 그 나노 결정립의 모양이 막 표면과 수직한 방향에서 수평한 방향으로 기울어지면서 성장하는 것을 확인할 수 있다.That is, in the case of nanocrystalline semiconductor thin films 150, 150 ', and 150 "heat-treated about 450 DEG C as the indium molar ratio increases, this is consistent with the planar scanning electron microscope results unless there is a large difference according to the indium molar ratio in the cross section. In the case of the pulsed rapid heat treatment of the film after the first heat treatment at about 450 ° C. and the third heat treatment at about 700 ° C. for the second subsequent heat treatment, the difference is large according to the indium molar ratio. It can be seen that the shape of the nano grains grows inclined in a horizontal direction from a direction perpendicular to the film surface.
도 18은 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리 후 나노 결정질 산화물 반도체 박막의 X-선 회절 결과를 나타낸 그래프이다. 도 18을 참조하면, 본 발명의 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸(120,120‘,120", 도 1a, 도 10a, 도 10c 및 도 20b 참조)의 인듐 몰비에 따른 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140,140‘,140", 도 1c, 도 10e 및 도 20d 참조)의 약 450℃ 후속 열처리 후 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 나노 결정질 산화물 반도체 박막(150,150‘,150", 도 1d, 도 10f 및 도 20e 참조)의 X-선 회절 결과(가)와, 약 450℃ 1차 후속 열처리 후, 약 700℃ 2차 후속 열처리 후, 나노 결정질 산화막 반도체 박막(150,150‘,150")의 X-선 회절 결과(나)이다.FIG. 18 is a graph showing X-ray diffraction results of nanocrystalline oxide semiconductor thin films after subsequent heat treatment of the amorphous oxide semiconductor thin film according to the molar ratio of the oxide compound sol applied in the embodiment of the present invention. Referring to FIG. 18, the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol (120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B) applied to an embodiment of the present invention is shown. Nanocrystalline indium-gallium-zinc oxide compound thin film, that is, amorphous oxide semiconductor thin film (140,140 ', 140 ", see FIGS. 1C, 10E and 20D) after subsequent heat treatment at about 450 ° C. X-ray diffraction results of the semiconductor thin film, ie, nanocrystalline oxide semiconductor thin film (150,150 ', 150 ", see FIGS. 1D, 10F, and 20E), and about 450 ° C after the first subsequent heat treatment, about 700 ° C 2 X-ray diffraction results (b) of the nanocrystalline oxide semiconductor thin films 150, 150 ', 150 "after the subsequent subsequent heat treatment.
즉, 인듐 몰비에 따른 나노 결정질 산화막 반도체 박막(150,150‘,150")의 그 결정질 상의 변화는 없으며, 나노 결정질은 InGaO3(ZnO)n(n=2)의 상을 가지고 있다. 약 450℃에서 결정화된 나노 결정질의 X-선 피크의 세기는 몰비가 증가함에 따라서 감소하는 경향을 보이고 있는데, 이는 나노 결정립의 크기는 몰비에 따른 큰 차이를 보이고 있지 않지만 공핍(void)에 따른 결정성에 차이를 보이고 있다.That is, there is no change in the crystalline phase of the nanocrystalline oxide semiconductor thin film 150,150 ', 150 "depending on the indium molar ratio, and the nanocrystalline has a phase of InGaO 3 (ZnO) n (n = 2). The intensity of the X-ray peak of the crystallized nanocrystalline tends to decrease as the molar ratio increases. This shows that the size of the nanocrystal grains does not show a significant difference according to the molar ratio but the crystallinity due to voids. have.
또한, 약 450℃ 1차 후속 열처리와 약 700℃ 2차 후속 열처리를 통하여 결정화된 나노 결정질 산화막 반도체 박막(150,150‘,150")의 X-선 피크의 세기를 보면, 인듐 몰비가 증가함에 따라서 그 세기가 감소하고 이는 결정성의 감소를 의미한다.In addition, the intensity of X-ray peaks of the nanocrystalline oxide semiconductor thin films 150, 150 ', and 150 "crystallized through about 450 ° C first and subsequent heat treatments of about 700 ° C is shown as the indium molar ratio increases. The intensity decreases, which means a decrease in crystallinity.
또한, 그 주 성장 방향이 (008)에서 (100)으로 변화하는 것을 확인할 수 있으며, 인듐-갈륨-아연 산화화합물은 서로 다른 육각형(Hexagonal) 구조의 갈륨-아연 화합물과 입방(cubic) 구조의 인듐 화합물이 올라간 구조를 가지고 있다. 여기서, 인듐의 양이 많아질수록 육각형(Hexagonal) 구조의 갈륨-아연 화합물의 주상 성장 구조를 방해하여 결정립이 막과 수평하고 기울어지면서 성장한다. 이는 단면 주사전자 현미경의 사진과 일치한다.In addition, it can be seen that the main growth direction is changed from (008) to (100), and the indium-gallium-zinc oxide compound has different hexagonal structure gallium-zinc compound and cubic structure indium The compound has a raised structure. Here, as the amount of indium increases, the grain growth of the hexagonal gallium-zinc compound interferes with the columnar growth structure, and the grain grows horizontally and inclined with the film. This is consistent with the photograph of the cross-sectional scanning electron microscope.
도 19는 본 발명의 실시예에 적용된 산화화합물 졸의 몰비에 따른 비정질 산화물 반도체 박막의 후속 열처리에 의한 나노 결정질 산화물 반도체 박막의 (008) 주 성장 방향의 상대적 피크의 세기 비교를 설명하기 위한 그래프이다. 도 19를 참조하면, 본 발명의 실시예에 적용된 산화화합물(예컨대, 인듐-갈륨-아연 등) 졸(120,120‘,120", 도 1a, 도 10a, 도 10c 및 도 20b 참조)의 인듐 몰비에 따른 비정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 비정질 산화물 반도체 박막(140,140‘,140", 도 1c, 도 10e 및 도 20d 참조)의 후속 열처리에 의한 나노 결정질 인듐-갈륨-아연 산화화합물 반도체 박막 즉, 나노 결정질 산화물 반도체 박막(150,150‘,150", 도 1d, 도 10f 및 도 20e 참조)의 (008) 주 성장 방향의 상대적 피크의 세기 비교로서, 이때의 열처리 조건은 (가) 약 450℃ 후속 열처리, (나) 약 450℃ 1차 후속 열처리 후, 약 700℃ 2차 후속 열처리이다.FIG. 19 is a graph for explaining a comparison of relative peak intensities of (008) main growth directions of a nanocrystalline oxide semiconductor thin film by subsequent heat treatment of an amorphous oxide semiconductor thin film according to the molar ratio of an oxide compound sol applied to an embodiment of the present invention. . Referring to FIG. 19, the indium molar ratio of an oxidized compound (eg, indium-gallium-zinc, etc.) sol (120,120 ', 120 ", see FIGS. 1A, 10A, 10C, and 20B) applied to an embodiment of the present invention is shown. Nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film according to the subsequent heat treatment of the amorphous indium-gallium-zinc oxide compound semiconductor thin film, that is, the amorphous oxide semiconductor thin film 140, 140 ', 140 ", see FIGS. 1C, 10E and 20D That is, as a comparison of the relative peak intensities of the (008) main growth direction of the nanocrystalline oxide semiconductor thin film (150,150 ', 150 ", see FIGS. 1D, 10F and 20E), the heat treatment conditions at this time (a) is about 450 ℃ Subsequent heat treatment, (b) about 450 ° C. after the first subsequent heat treatment, about 700 ° C., the second subsequent heat treatment.
즉, 상기 2차 후속 열처리에 의한 나노 결정질 산화물 반도체 박막(150,150‘,150")의 결정성이 향상됨을 알 수 있으며, 인듐 몰비가 증가함에 따라서 그 결정성이 감소함을 확인할 수 있다.That is, it can be seen that the crystallinity of the nanocrystalline oxide semiconductor thin film 150, 150 ′, 150 ″ is improved by the second subsequent heat treatment, and the crystallinity decreases as the indium molar ratio increases.
한편, 본 발명의 실시예에서는 예컨대, 인듐-갈륨-아연 산화화합물에서 인듐의 몰비를 조절한 실험 결과를 나타냈지만, 이에 국한하지 않으며, 다른 산화화합물에 대해서도 동일한 결과를 얻을 수 있다.On the other hand, in the embodiment of the present invention, for example, the experimental result of adjusting the molar ratio of indium in the indium-gallium-zinc oxide compound is shown, but not limited to this, the same result can be obtained for other oxide compounds.
(제3 실시예)(Third Embodiment)
도 20a 내지 도 20e는 본 발명의 제3 실시예에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법을 설명하기 위한 단면도로서, 액상제조 기반의 산화물(예컨대, 인듐-갈륨-아연 등) 반도체 박막의 특성 향상 및 두께 조절을 위한 실시예이다.20A to 20E are cross-sectional views illustrating a crystallization method of an oxide semiconductor thin film using a liquid phase manufacturing base according to a third embodiment of the present invention, and a liquid phase based oxide (eg, indium-gallium-zinc, etc.) semiconductor thin film An embodiment for improving the characteristics and adjusting the thickness.
도 20a를 참조하면, 기판(100) 상에 예컨대, 실리콘 산화막 또는 질화막 등으로 이루어진 절연막(110)을 형성한 후, 절연막(110) 상에 전술한 제1 실시예의 졸겔 공정을 거쳐 결정화된 투명한 나노 결정질 산화물 반도체 박막(150)을 형성한다.Referring to FIG. 20A, after forming an insulating film 110 formed of, for example, a silicon oxide film or a nitride film on the substrate 100, the transparent nanocrystals crystallized through the sol-gel process of the first embodiment described above on the insulating film 110. The crystalline oxide semiconductor thin film 150 is formed.
도 20b를 참조하면, 나노 결정질 산화물 반도체 박막(150) 상에 예컨대, 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종 이상의 산화화합물 졸(sol)(예컨대, 인듐-갈륨-아연 졸 등)(120“)을 예컨대, 스핀 코팅 또는 잉크젯 프린팅 등을 이용하여 증착한다.Referring to FIG. 20B, at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the nanocrystalline oxide semiconductor thin film 150 (eg, Indium-gallium-zinc sol, etc.) 120 " is deposited using, for example, spin coating or inkjet printing.
한편, 나노 결정질 산화물 반도체 박막(150)과 산화화합물 졸(120“) 사이에 예컨대, 플라즈마(Plasma) 혹은 용액처리로 친수성 및 소수성을 형성하여 산화화합물 졸(120”)과의 안정적인 결합 향상을 꾀할 수 있다.Meanwhile, hydrophilicity and hydrophobicity may be formed between the nanocrystalline oxide semiconductor thin film 150 and the oxidized compound sol 120 ″, for example, by plasma or solution treatment, thereby improving stable bonding with the oxidized compound sol 120 ″. Can be.
도 20c를 참조하면, 전술한 본 발명의 제1 실시예에 적용된 상기 제1 열처리 공정을 통해 산화화합물 졸(120“)을 건조 및 가열하여 산화화합물 겔(gel)(130”)로 형성한다.Referring to FIG. 20C, an oxide compound sol 120 ″ is dried and heated to form an oxide compound gel 130 ′ through the first heat treatment process applied to the first embodiment of the present invention.
도 20d를 참조하면, 전술한 본 발명의 제1 실시예에 적용된 상기 제2 열처리 공정을 통해 산화화합물 겔(130“)을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막(140”)을 형성한다.Referring to FIG. 20D, the oxidized compound gel 130 ″ is dried and heated through the second heat treatment process applied to the first embodiment of the present invention to form an opaque amorphous oxide semiconductor thin film 140 ″.
도 20e를 참조하면, 전술한 본 발명의 제1 실시예에 적용된 제3 열처리 공정을 통해 불투명 비정질 반도체 박막(140“)을 건조 및 가열하고, 투명 나노 결정질 반도체 박막(150)을 결정화 핵 층으로 이용하여 두꺼워진 제2의 투명 결정질 산화물 반도체 박막(150”)을 형성한다.Referring to FIG. 20E, the opaque amorphous semiconductor thin film 140 ″ is dried and heated through a third heat treatment process applied to the first embodiment of the present invention, and the transparent nanocrystalline semiconductor thin film 150 is converted into a crystallized nucleus layer. The thickened second transparent crystalline oxide semiconductor thin film 150 ″ is formed.
즉, 나노 결정질 반도체 박막(150)을 결정 성장의 핵으로 작용하여 상부 불투명 비정질 반도체 박막(140“)의 그 방향성과 결정성을 향상시키고자 한다. 예컨대, 나노 결정립 인듐-갈륨-아연 산화화합물 반도체 박막은 아연 화합물 산화막 계열에서 막의 방향성 향상 및 용이한 결정립 형성을 위한 결정 성장 핵으로도 작용할 수 있다.That is, the nanocrystalline semiconductor thin film 150 serves as a nucleus for crystal growth to improve the directivity and crystallinity of the upper opaque amorphous semiconductor thin film 140 ″. For example, the nanocrystalline indium-gallium-zinc oxide compound semiconductor thin film may also function as a crystal growth nucleus for improving the orientation of the film and facilitating grain formation in the zinc compound oxide film series.
전술한 바와 같이, 본 발명의 통상의 스퍼터링과 펄스드 레이저 증착 (Pulsed Laser Deposition, PDL)으로 대표되는 진공 증착 방법을 대신하여, 간단하고 저렴한 방법으로 대량 생산이 가능한 액상제조 기반의 산화물 반도체 박막의 결정화 기술을 제공하고, 본 발명에 의해 제작된 비정질 혹은 나노, 미세, 다결정 화합물 반도체 박막은 예컨대, 유기발광다이오드(OLED) 및 액정디스플레이(LCD)와 같은 디스플레이 소자, 또는 태양전지(Solar Cell) 등에 응용되어 질 수 있다.As described above, in place of the conventional vacuum deposition method represented by the sputtering and pulsed laser deposition (PDL) of the present invention, a liquid-based oxide semiconductor thin film that can be mass-produced in a simple and inexpensive manner. Amorphous or nano, fine, polycrystalline compound semiconductor thin film produced by the present invention, which provides a crystallization technique, is, for example, a display device such as an organic light emitting diode (OLED) and a liquid crystal display (LCD), or a solar cell. Can be applied.
또한, 본 발명에 의하면, 기존의 스퍼터링 공정 과정에서 높은 온도 결정화가 필요한 반면 액상제조 방법에서는 낮은 온도에서 결정화가 가능하다. 현재 상용되고 있는 스퍼터링 증착 방법을 이용한 인듐-갈륨-아연 산화화합물 반도체 박막의 응용은 그 비정질 상으로 제한되어 있다. 이는 결정화 시 약 1000℃ 이상의 높은 온도에서의 열처리를 필요로 하고 있기 때문이다.In addition, according to the present invention, high temperature crystallization is required in the existing sputtering process, while the liquid crystal manufacturing method enables crystallization at low temperature. The application of the indium-gallium-zinc oxide compound semiconductor thin film using the sputter deposition method currently available is limited to the amorphous phase. This is because the crystallization requires heat treatment at a high temperature of about 1000 ° C. or higher.
또한, 산화막의 결정질 막에 대한 광학적 구조적 특성에 대한 전반적인 인식이 부족하다. 이에 액상제조 기반의 산화화합물 반도체 박막은 상대적으로 낮은 온도에서 결정화가 가능하고 비정질 상 대비 향상된 구조적, 광학적 특성을 갖는 결정질 산화막 결정화를 제공하고자 한다.In addition, there is a general lack of recognition of the optical structural properties of the crystalline film of the oxide film. Accordingly, the liquid crystal-based oxide compound semiconductor thin film is capable of crystallization at a relatively low temperature and provides crystallization of the crystalline oxide film having structural and optical properties improved compared to an amorphous phase.
또한, 본 발명은 스핀 코팅(Spin Coating), 잉크젯(Inkjet) 프린팅 등을 이용하여 산화화합물 졸 증착 후, 겔 건조 과정과 이에 따른 비정질 박막의 형성, 비정질 반도체 박막의 열처리를 통한 낮은 온도에서 결정화된 나노, 미세, 다결정 결정질 반도체 박막을 제공하여 비정질 반도체 박막에 비해 향상된 투과도 및 구조적 특성을 제공하고자 한다.In addition, the present invention is crystallized at a low temperature through the sol deposition of the oxide compound using spin coating, inkjet printing, etc., after the gel drying process and the formation of the amorphous thin film, the heat treatment of the amorphous semiconductor thin film To provide nano, fine, polycrystalline semiconductor thin film to provide improved transmittance and structural characteristics compared to the amorphous semiconductor thin film.
전술한 본 발명에 따른 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법에 대한 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 특허청구범위와 발명의 상세한 설명 및 첨부한 도면의 범위 안에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 본 발명에 속한다.While a preferred embodiment of the method for crystallizing an oxide semiconductor thin film using a liquid-based manufacturing base according to the present invention has been described above, the present invention is not limited thereto, but the claims and the detailed description of the invention and the accompanying drawings. It is possible to carry out various modifications and this also belongs to this invention.
액상 공정을 이용한 플래쉬 메모리 및 그 형성 방법Flash memory using liquid phase process and its formation method
플래쉬 메모리 소자는 기존의 전형적인 MOS 구조의 유전막 사이에 플로팅 게이트(floating gate)라고 불리우는 전하 저장부를 포함하며, 전원 공급이 차단된 상태에서도 데이터를 저장할 수 있는 특성을 갖는다. 기존의 플래쉬 메모리 소자에서는 전하를 저장하는 플로팅 게이트로서 폴리실리콘을 주로 사용하였으나, 소자간 간섭으로 인한 집적도 향상의 어려움 때문에 최근에는 폴리실리콘을 대체하기 위한 전하 트랩형 메모리 소자(charge trap type memory device)에 관한 연구가 활발히 진행되고 있다. 디램 등의 기존 휘발성 메모리와 마찬가지로, 플래쉬 메모리 소자 역시 전류가 흐르는 채널 영역으로서 실리콘 반도체를 사용하고 있다. 이러한 실리콘 반도체의 채널 영역을 적용할 경우, 채널 도핑, 소스-드레인 도핑, 웰 도핑 등을 위한 이온주입 및 열처리 공정을 수행한다. The flash memory device includes a charge storage unit called a floating gate between dielectric layers of a conventional MOS structure, and has a characteristic of storing data even when a power supply is cut off. In the conventional flash memory device, polysilicon is mainly used as a floating gate for storing charge, but due to the difficulty of improving the integration density due to interference between devices, a charge trap type memory device is recently used to replace polysilicon. There is an active research on. Like conventional volatile memories such as DRAMs, flash memory devices use silicon semiconductors as channel regions through which current flows. When the channel region of the silicon semiconductor is applied, ion implantation and heat treatment processes for channel doping, source-drain doping, and well doping are performed.
플래쉬 메모리 소자의 성능은 데이터 저장 능력과 그 데이타의 쓰기 및 읽기 동작의 안정성 및 속도 등에 의해 결정된다. 플래쉬 등의 비휘발성 메모리 소자 분야에서도 고집적화의 필요성이 증대되고 있다. 이를 위해서 메모리 소자의 크기를 줄이기 위한 노력이 계속되고 있으나 소자 축소에 따른 단채널 효과등 소자 특성의 악화를 방지하기 위한 방안이 요구되고 있다. 고집적화를 위한 다른 방안으로서, 복수 개의 플래쉬 메모리 셀을 수직으로 적층하는 3D(3-dimensional) 적층셀의 구현 가능성이 제시되고 있다. The performance of a flash memory device is determined by the data storage capability and the stability and speed of write and read operations of the data. In the field of nonvolatile memory devices such as flash, the need for high integration is increasing. To this end, efforts have been made to reduce the size of memory devices, but there is a need for a method for preventing deterioration of device characteristics such as short channel effects due to device shrinkage. As another method for high integration, a possibility of implementing a 3D (3-dimensional) stacked cell in which a plurality of flash memory cells are vertically stacked is proposed.
그러나, 실리콘으로 된 채널 영역을 사용하는 경우, 실리콘 반도체의 특성상 높은 온도를 가하면 플래쉬 메모리 셀 특성이 변하기 때문에 단일층 셀만을 구성할 수 있고 적층셀 구조를 구현할 수 없는 문제가 있다. 또한 실리콘 반도체의 채널 영역이 고온에서 형성되기 때문에, 실리콘 반도체 기판이 아닌 유리(glass) 또는 플라스틱 기판 등을 사용하여 플레쉬 메모리 소자를 제조하는 것이 불가능하거나 매우 어렵다. 적층셀 구현 또는 플라스틱 기판 적용의 측면에서, 플로팅 게이트 형성 공정도 기존의 폴리실리콘 형성 온도보다 더욱 저온에서 수행되는 것이 바람직하다.However, in the case of using a channel region made of silicon, since the flash memory cell characteristics change when a high temperature is applied due to the characteristics of the silicon semiconductor, only a single layer cell can be configured and a stacked cell structure cannot be realized. In addition, since the channel region of the silicon semiconductor is formed at a high temperature, it is impossible or very difficult to manufacture a flash memory device using a glass or plastic substrate and the like rather than a silicon semiconductor substrate. In terms of stacked cell implementation or plastic substrate application, the floating gate formation process is also preferably performed at lower temperatures than conventional polysilicon formation temperatures.
이에 본 발명의 실시 예는 액상 공정을 적용함으로써 저온 공정이 가능한 플래쉬 메모리 형성 방법을 제공한다. Accordingly, an embodiment of the present invention provides a flash memory forming method capable of low-temperature processing by applying a liquid phase process.
도 21은 본 발명의 일 실시형태에 따른 플래쉬 메모리 소자의 단면도이다. 도 21은 특히 게이트 구조체(제어 게이트 및 플로팅 게이트 포함)가 기판과 채널 영역 사이에 배치되는 '바텀 제어 게이트형(bottom control gate type)' 플래쉬 메모리셀을 나타낸다. 21 is a cross-sectional view of a flash memory device according to an embodiment of the present invention. FIG. 21 shows a 'bottom control gate type' flash memory cell in particular in which a gate structure (including a control gate and a floating gate) is disposed between the substrate and the channel region.
도 21을 참조하면, 플래쉬 메모리 소자(1000)는 기판(1010) 상에 형성된 제어 게이트(1030), 층간 절연막(interdielectric: 1040), 플로팅 게이트(1070), 터널링 절연막(1070) 및 채널층(108)을 포함한다. 기판(1010)과 제어 게이트(1030) 사이에는 SiO2 버퍼층(103)이 형성되어 버퍼층(1030) 위의 층 구조에의 불순물 혼입을 방지하고 버퍼층(103) 위의 층 구조의 막질을 개선할 수 있다. 채널층(108)의 양단에는 서로 이격 배치된 소스-드레인 전극(1100, 1200)이 배치되어 있다.Referring to FIG. 21, a flash memory device 1000 may include a control gate 1030, an interdielectric layer 1040, a floating gate 1070, a tunneling insulating layer 1070, and a channel layer 108 formed on a substrate 1010. ). A SiO 2 buffer layer 103 is formed between the substrate 1010 and the control gate 1030 to prevent the incorporation of impurities into the layer structure on the buffer layer 1030 and to improve the film quality of the layer structure on the buffer layer 103. have. Source- drain electrodes 1100 and 1200 spaced apart from each other are disposed at both ends of the channel layer 108.
상기 채널층(1080)은 후술하는 바와 같이, 용액 기반의 반도체 산화물 물질을 코팅하여 형성된 것이다. 특히, 스핀 코팅(spin coating), 나노 압인(nano imprinting) 또는 잉크젯 프린팅 등의 저온의 단순한 공정을 이용하여 터널링 절연막(1070) 상에 용액 기반의 IGZO(solution-based Indium Gallium Zinc Oxide)을 코팅함으로써 상기 채널층(1080)을 쉽게 얻을 수 있다. The channel layer 1080 is formed by coating a solution-based semiconductor oxide material, as described below. In particular, by coating a solution-based Indium Gallium Zinc Oxide (IGZO) on the tunneling insulating film 1070 using a simple low-temperature process such as spin coating, nano imprinting or inkjet printing. The channel layer 1080 can be easily obtained.
이 채널층(1080)은 다결정(poly crystalline) IGZO로 이루어진 것이며, 다결정 IGZO는 높은 이동도의 반도체 성질을 가져서 소스-드레인 전극(1100, 1200) 및 제어 게이트(1030)의 전압 인가에 따라 이 채널층(1080)을 통해 동작 전류가 흐르게 된다. 이러한 다결정 IGZO의 채널층(1080)은 별도의 도핑 없이 트랜지스터의 채널로 작용하며 소스-드레인 전극과의 접합을 위한 별도의 불순물 영역(확산 영역 또는 이온 주입 영역)을 필요로 하지 않는다. The channel layer 1080 is made of polycrystalline IGZO. The polycrystalline IGZO has a high mobility semiconductor property, so that the channel is applied to the source- drain electrodes 1100 and 1200 and the control gate 1030 according to the application of the voltage. Operating current flows through layer 1080. The channel layer 1080 of the polycrystalline IGZO acts as a channel of the transistor without any doping and does not require a separate impurity region (diffusion region or ion implantation region) for junction with the source-drain electrode.
기판(1010)으로는 종래의 실리콘 기판 등을 사용할 수 있으나, 유리 기판 또는 PET(polyethyleneterephthalate) 등의 휘어지기 쉬운 플렉시블(flexible) 기판 등을 용이하게 적용할 수 있다. 이는 채널층(1080)이 종래 실리콘 반도체와 달리 용액 기반의 반도체 산화물 물질의 코팅 공정에 의해 저온에서 형성될 수 있기 때문에, 열에 약한 플라스틱, 유리 등 재질을 갖는 기판을 적용해도 기판에 손상이 가해지지 않기 때문이다. 따라서, 본 실시형태에 따른 플래쉬 메모리 셀 구조는 LCD, OLED 등의 디스플레이에 임베디드하여 SOC(system on chip)를 구현할 수 있으며, 플렉시블 메모리 소자 구현에 유리하다. As the substrate 1010, a conventional silicon substrate may be used, but a flexible substrate such as a glass substrate or a flexible substrate such as polyethyleneterephthalate (PET) may be easily applied. Since the channel layer 1080 may be formed at a low temperature by a coating process of a solution-based semiconductor oxide material, unlike a conventional silicon semiconductor, even if a substrate having a material, such as plastic or glass, which is weak to heat, the substrate is not damaged. Because it does not. Accordingly, the flash memory cell structure according to the present embodiment may be embedded in a display such as an LCD or an OLED to implement a system on chip (SOC), which is advantageous for implementing a flexible memory device.
제어 게이트(1030)는 MoW, W, Mo, AlNd, Ag, Cu, MoTa, Cr 등의 금속 또는 합금으로 형성될 수 있다. 층간 절연막(1040)은 제어 게이트(1030)와 플로팅 게이트(1050) 사이에 배치되는 절연막으로서, 제어 게이트(1030)에 인가된 전압을 플로팅 게이트(1050)로 커플링을 통해 전달시켜주는 역할을 한다. 따라서, 층간 절연막(1040)의 커패시턴스(capacitance)값이 큰 것이 바람직하다. 또한 메모리셀의 신뢰성(reliability)에 영향을 주는 주요 특성 중 하나인 리텐션(retention) 특성을 좋게 하기 위해 적절한 두께를 갖는 것이 바람직하다. 본 실시형태에서는, 층간 절연막(1040)은 질화막과 산화막의 이중막 구조를 사용할 수 있는데, 예컨대 약 15nm의 SiNx막(1040a)과 약 10nm의 SiO2막(1040b)의 이중막 구조를 가질 수 있다. 이러한 NO 구조 이외에도, 층간 절연막(1040)은 ONO 구조, 산화막만을 사용하는 구조, 고유전율(high-k) 물질인 Al2O3, HfO2, Zr/산화물/Zr 등의 재질 또는 막 구조를 사용할 수 있다. 채널층(108)으로부터 플로팅 게이트(1050)로의 캐리어 터널링을 위한 터널링 절연막(1070)으로는, 예컨대 Al2O3와 같은 고유전율 산화막을 사용할 수 있다. 그외에도, 터널링 절연막(1070)으로서, SiO2, SiNx, Al2O3, HfO2 등의 고유전율 물질을 사용할 수 있다. The control gate 1030 may be formed of a metal or an alloy such as MoW, W, Mo, AlNd, Ag, Cu, MoTa, Cr, or the like. The interlayer insulating film 1040 is an insulating film disposed between the control gate 1030 and the floating gate 1050, and serves to transfer a voltage applied to the control gate 1030 to the floating gate 1050 through a coupling. . Therefore, it is preferable that the capacitance value of the interlayer insulating film 1040 is large. In addition, it is desirable to have an appropriate thickness in order to improve the retention characteristic, which is one of the main characteristics affecting the reliability of the memory cell. In the present embodiment, the interlayer insulating film 1040 may use a double film structure of a nitride film and an oxide film. For example, the interlayer insulating film 1040 may have a double film structure of a SiNx film 1040a of about 15 nm and a SiO 2 film 1040b of about 10 nm. . In addition to the NO structure, the interlayer insulating film 1040 may use an ONO structure, a structure using only an oxide film, and a material or film structure such as Al 2 O 3 , HfO 2 , Zr / oxide / Zr, which are high-k materials. have. As the tunneling insulating layer 1070 for carrier tunneling from the channel layer 108 to the floating gate 1050, a high dielectric constant oxide such as Al 2 O 3 may be used. In addition, as the tunneling insulating film 1070, a high dielectric constant material such as SiO 2 , SiNx, Al 2 O 3 , HfO 2, or the like may be used.
플로팅 게이트(1050)는 카본 나노튜브층으로 이루어질 수 있다. 후술하는 바와 같이, 카본 나노튜브층 구조의 플로팅 게이트(1050)는 카본 나노튜브(CNT)가 분산되어 있는 용액 기반의 CNT 물질을 스핀 코팅, 나노 압인 또는 잉크젯 프린팅등의 저온 공정으로 코팅하여 쉽게 얻을 수 있다. 이 플로팅 게이트(1050)용 CNT로서 예컨대, SWNT(single wall carbon nanotube) 또는 MWNT(multiwall carbon nanotube)를 사용할 수 있다. 이와 같이 카본 나노튜브 층 구조의 플로팅 게이트(1050)를 사용함으로써, 집적도를 향상시 문제가 되는 셀 간의 간섭 문제를 해결할 뿐만 아니라, 카본 나노튜브의 직경은 1~1.4nm 정도로 매우 작기 때문에 디바이스 스케일링 문제를 해결할 수 있다. 더욱이, 카본 나노튜브 층 구조의 플로팅 게이트(1050)는 후술하는 바와 같이 저온 공정을 통해 비교적 쉽게 제작이 가능하기 때문에, 상술한 다결정 IGZO의 채널층(1070)과 함께 3D 적층셀을 더욱 용이하게 구현할 수 있게 한다. The floating gate 1050 may be formed of a carbon nanotube layer. As will be described later, the floating gate 1050 of the carbon nanotube layer structure is easily obtained by coating a solution-based CNT material in which carbon nanotubes (CNTs) are dispersed by a low temperature process such as spin coating, nano stamping, or inkjet printing. Can be. As the CNT for the floating gate 1050, for example, single wall carbon nanotube (SWNT) or multiwall carbon nanotube (MWNT) can be used. By using the floating gate 1050 of the carbon nanotube layer structure as described above, not only solves the interference problem between cells, which is a problem in improving the integration degree, but also the device scaling problem because the diameter of the carbon nanotube is very small, about 1 to 1.4 nm. Can be solved. Furthermore, since the floating gate 1050 having the carbon nanotube layer structure can be manufactured relatively easily through a low temperature process as described below, the 3D stacked cell can be more easily implemented together with the channel layer 1070 of the polycrystalline IGZO described above. To be able.
플로팅 게이트(1050)는 카본 나노튜브 이외에도, 용액 기반의 반도체 산화 물질로부터 형성될 수도 있다. 후술하는 바와 같이, 용액 기반의 IGZO, 또는 용액 기반의 ZnO, 용액 기반의 IZO, 용액 기반의 ZTO 물질 등을 사용하여 플로팅 게이트를 형성하는 것도 가능하다. 이 경우 역시 저온 공정에 의한 플로팅 게이트 제작이 가능하고, 3D 적층셀 구현에 유리하다. 소스-드레인 전극(1100, 1200)은 예컨대, IZO, Cu, Al, W, MoW, Ti, Ta, Cr 또는 Ag 등을 사용하여 형성될 수 있다. In addition to carbon nanotubes, the floating gate 1050 may be formed from a solution-based semiconductor oxide material. As described below, it is also possible to form a floating gate using a solution-based IGZO, or a solution-based ZnO, a solution-based IZO, a solution-based ZTO material, or the like. In this case, it is also possible to manufacture a floating gate by a low temperature process, which is advantageous for implementing a 3D stacked cell. The source- drain electrodes 1100 and 1200 may be formed using, for example, IZO, Cu, Al, W, MoW, Ti, Ta, Cr, or Ag.
도 22는 본 발명의 다른 실시형태에 따른 플래쉬 메모리 소자(2000)의 단면도이다. 도 22의 실시형태에서는, 기판과 채널 영역 위에 게이트 구조체가 배치되는 '탑 제어 게이트형(top control gate type)' 플래쉬 메모리셀을 나타낸다. 22 is a cross-sectional view of a flash memory device 2000 according to another embodiment of the present invention. In the embodiment of FIG. 22, a 'top control gate type' flash memory cell in which a gate structure is disposed over a substrate and a channel region is shown.
도 22를 참조하면, 기판(2010) 상에 SiO2 버퍼층(2010)과 채널층(2080)이 형성되어 있고, 그 위에 터널링 절연막(2070), 플로팅 게이트(2050), 층간 절연막(2040) 및 제어 게이트(2030)가 순차적으로 적층되어 있다. 채널층(2080)의 양단에는 소스-드레인 전극(2100, 2200)이 서로 이격 배치되어 있다. 기판(2010)을 포함하여 채널층, 플로팅 게이트 등 각 구성 부분(2030~2200)의 재질과 기본 구조는 전술한 실시형태(도 21)와 마찬가지이다. 특히, 채널층(2080)은 스핀 코팅, 나노 압인 또는 잉크젯 프린팅 등의 저온의 단순한 공정을 이용하여 버퍼층(2020) 상에 용액 기반의 IGZO 물질을 코팅함으로써 얻어질 수 있으며, 다결정 IGZO 반도체층 구조로 되어 있다. 또한, 플로팅 게이트(2050)는 용액 기반의 물질을 저온 코팅하여 형성될 수 있는 카본 나노튜브의 층구조이거나 IGZO, ZnO, IZO 또는 ZTO의 층구조일 수 있다. 따라서, 전술한 실시형태(도 21)와 마찬가지로, 저온 공정에 의한 셀 제작에 유리하며 3D 적층셀 구현에 유리하다.Referring to FIG. 22, a SiO 2 buffer layer 2010 and a channel layer 2080 are formed on a substrate 2010, and a tunneling insulating film 2070, a floating gate 2050, an interlayer insulating film 2040, and control are formed thereon. The gates 2030 are sequentially stacked. Source- drain electrodes 2100 and 2200 are spaced apart from each other at both ends of the channel layer 2080. The material and basic structure of each of the component parts 2030 to 2200, such as the channel layer and the floating gate, including the substrate 2010, are the same as in the above-described embodiment (Fig. 21). In particular, the channel layer 2080 may be obtained by coating a solution-based IGZO material on the buffer layer 2020 using a simple low-temperature process such as spin coating, nano stamping or inkjet printing, and has a polycrystalline IGZO semiconductor layer structure. It is. In addition, the floating gate 2050 may be a layer structure of carbon nanotubes or a layer structure of IGZO, ZnO, IZO or ZTO, which may be formed by low temperature coating of a solution-based material. Therefore, like the above-described embodiment (FIG. 21), it is advantageous to manufacture the cell by a low temperature process and to the 3D stacked cell implementation.
이하, 도 23 및 24를 참조하여 본 발명의 실시형태들에 따른 플래쉬 메모리 소자의 제조 방법을 설명한다.Hereinafter, a method of manufacturing a flash memory device according to embodiments of the present invention will be described with reference to FIGS. 23 and 24.
도 23의 (a) 내지 (f)는 본 발명의 실시형태에 따른 플래쉬 메모리 소자의 제조 공정을 설명하기 위한 단면도들로서, 바텀 제어 게이트형 구조를 갖는 플래쉬 메모리 소자 제작에 관련된다. 23A to 23F are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment of the present invention, and are related to fabrication of a flash memory device having a bottom control gate type structure.
먼저, 도 23(a)를 참조하면, 실리콘, 유리 또는 PET 등의 플라스틱 기판(1010) 상에 SiO2 버퍼층(102)을 형성한다. 이 버퍼층(1020)은 이후 적층되는 층에 불순물이 혼입되는 것을 막고 후속 층들의 막질을 양호한 상태로 유지시키는 역할을 한다. 그 후, 도 23(b)에 도시된 바와 같이 버퍼층(1020) 상에 제어 게이트(1030)를 형성한다. 제어 게이트(103)는, MoW, W, Al, AlNd, Ag, Cu, MoTa, 또는 Cr, 등의 물질을 스퍼터링으로 증착하여 형성할 수 있다. First, referring to FIG. 23A, the SiO 2 buffer layer 102 is formed on a plastic substrate 1010 such as silicon, glass, or PET. The buffer layer 1020 serves to prevent impurities from being incorporated into the later stacked layers and to maintain the quality of subsequent layers in a good state. Thereafter, as shown in FIG. 23B, the control gate 1030 is formed on the buffer layer 1020. The control gate 103 may be formed by depositing a material such as MoW, W, Al, AlNd, Ag, Cu, MoTa, or Cr by sputtering.
그 후, 도 23(c)에 도시된 바와 같이, 제어 게이트(1030) 상에 층간 절연막(1040)을 형성한다. 층간 절연막(1040)은 질화막(1040a)과 산화막(1040b)을 순차 형성하여 NO의 이중막 구조로 제작할 수 있다. 이 층간 절연막(1040)은 제어 게이트(1030)와 후속의 플로팅 게이트 사이에 배치되는 것으로서, 전압 커플링을 위해 커패시턴스 값이 큰 물질로 형성되는 것이 바람직하다. 또한 층간 절연막(1040)은 메모리셀의 리텐션 특성을 좋게 하기 위해 적절한 두께로 형성되는 것이 바람직한데, 예컨대, 약 15nm의 질화막(1040a)과 약 10nm의 산화막(1040b)으로 형성될 수 있다. 본 실시형태와 같은 NO의 이중막 대신에 산화막만으로 층간 절연막(1040)을 형성할 수도 있으며, 고유전율 물질인 Al2O3 또는 HfO 등의 산화막으로 층간 절연막(1040)을 형성할 수도 있다. 그 밖에도, 층간 절연막(1040)은 Zr/산화막/Zr의 적층막 구조로 형성할 수도 있다. Thereafter, as shown in FIG. 23C, an interlayer insulating film 1040 is formed on the control gate 1030. The interlayer insulating film 1040 may be formed in a double layer structure of NO by sequentially forming the nitride film 1040a and the oxide film 1040b. The interlayer insulating film 1040 is disposed between the control gate 1030 and the subsequent floating gate, and is preferably formed of a material having a large capacitance value for voltage coupling. In addition, the interlayer insulating film 1040 is preferably formed to an appropriate thickness in order to improve the retention characteristics of the memory cell. For example, the interlayer insulating film 1040 may be formed of a nitride film 1040a of about 15 nm and an oxide film 1040b of about 10 nm. Instead of the double layer of NO as in the present embodiment, the interlayer insulating film 1040 may be formed of only an oxide film, or the interlayer insulating film 1040 may be formed of an oxide film such as Al 2 O 3 or HfO, which is a high dielectric constant material. In addition, the interlayer insulating film 1040 may be formed in a stacked film structure of Zr / oxide film / Zr.
다음으로, 도 23(d)에 도시된 바와 같이, 층간 절연막(1040) 상에 플로팅 게이트(1050)를 형성한다. 플로팅 게이트(1050)는 잘 정제되고 디스퍼션(dispersion)된 SWNT 또는 MWNT 등과 같은 용액 기반의 카본 나노튜브를 층간 절연막(1040) 상에 코팅하여 형성할 수 있다. 용액 기반의 카본 나노튜브 물질 내에는 그라펜(graphene) 또는 플러렌(fullerene) 등이 포함될 수 있다. 카본 나노튜브(CNT)와 분산제를 탈이온수에 첨가하여 CNT가 균일하게 분산되어 있는 용액 기반의 카본 나노튜브 물질을 만들 수 있다. CNT가 분산된 용액(분산액)중 CNT 함량은 특별히 한정되는 것은 아니나, CNT는 예시적으로 10-100mg/L로 분산액 중에 포함될 수 있다. CNT 분산액에 함유되는 분산제로는 벤젠 코니움 클로라이드(benzene konium chloride), 소디움 도데실 설페이트(sodium dodecyl sulfate), 폴리에틸렌이민(polyethylenimine), DMF(Dimethylformamide), ethanol 또는 염화마그네슘이 사용될 수 있다. 상기 분산제 함량은 충분한 분산을 이룰 수 있을 정도로 당업자에게 일반적으로 알려진 중량%로 첨가될 수 있다. Next, as shown in FIG. 23D, a floating gate 1050 is formed on the interlayer insulating film 1040. The floating gate 1050 may be formed by coating a solution-based carbon nanotube such as SWNT or MWNT that is well purified and dispersed on the interlayer insulating film 1040. The solution-based carbon nanotube material may include graphene or fullerene. Carbon nanotubes (CNTs) and dispersants may be added to deionized water to form solution-based carbon nanotube materials with uniform dispersion of CNTs. The CNT content in the solution (dispersion) in which the CNTs are dispersed is not particularly limited, but CNTs may be included in the dispersion at, for example, 10-100 mg / L. As a dispersant contained in the CNT dispersion, benzene konium chloride, sodium dodecyl sulfate, polyethylenimine, dimethylformamide, ethanol or magnesium chloride may be used. The dispersant content may be added in weight percent generally known to those skilled in the art to achieve sufficient dispersion.
스핀 코팅, 나노 압인 또는 잉크젯 프린팅와 같은 저온의(450℃ 미만) 단순한 공정을 사용하여 용액 기반의 카본 나노튜브 물질을 코팅할 수 있다. 코팅 공정중 또는 코팅 공정후에 적절한 온도(예컨대, 250℃ 미만)로 코팅물을 가열하여 수분 등의 용매와 분산제 등의 첨가물질을 날려버리고 카본 나노튜브층을 형성한다. 이로써 적절한 밀도를 갖는 카본 나노튜브층 구조의 플로팅 게이트(1050)를 형성할 수 있다. 플로팅 게이트(1050) 내의 카본 나노튜브 입자는 터널링 절연막을 통해 터널링된 캐리어를 트랩하는 트래핑 사이트로 작용할 수 있다. Solution-based carbon nanotube materials can be coated using simple, low temperature (less than 450 ° C.) processes such as spin coating, nano stamping or inkjet printing. The coating is heated to an appropriate temperature (eg, less than 250 ° C.) during or after the coating process to blow off solvents such as moisture and additives such as dispersants to form a carbon nanotube layer. As a result, the floating gate 1050 having the carbon nanotube layer structure having an appropriate density can be formed. The carbon nanotube particles in the floating gate 1050 may act as trapping sites for trapping the tunneled carrier through the tunneling insulating film.
플로팅 게이트(1050)는 상술한 용액 기반 카본 나노튜브 물질 대신에 용액 기반의 도전성 반도체 산화물을 저온 코팅(스핀 코팅, 나노 압인, 잉크젯 프린팅 등)하여 형성할 수도 있다. 예를 들어, 후술하는 채널층 형성과 마찬가지로 용액 기반의 IGZO 물질을 코팅하거나 용액 기반의 ZnO, IZO(Indium Zinc Oxide) 또는 ZTO(Zinc Tin Oxide) 물질의 코팅을 통하여 플로팅 게이트(105)를 형성할 수도 있다. The floating gate 1050 may be formed by low temperature coating (spin coating, nano stamping, inkjet printing, etc.) of a solution-based conductive semiconductor oxide instead of the above-described solution-based carbon nanotube material. For example, as in the channel layer formation described below, the floating gate 105 may be formed by coating a solution-based IGZO material or by coating a solution-based ZnO, indium zinc oxide (IZO), or zinc tin oxide (ZTO) material. It may be.
다음으로 도 23(e)를 참조하면, 플로팅 게이트(1050) 상에 터널링 절연막(107)을 형성한다. 터널링 절연막(1070)으로는 예컨대 고유전율을 갖는 Al2O3 또는 SiO2, SiNx, HfO2 등의 산화막이나 질화막을 사용할 수 있다. Next, referring to FIG. 23E, a tunneling insulating layer 107 is formed on the floating gate 1050. As the tunneling insulating film 1070, an oxide film or a nitride film such as Al 2 O 3 having a high dielectric constant, SiO 2 , SiNx, HfO 2 , or the like can be used.
다음으로 도 23(f)에 도시된 바와 같이, 터널링 절연막(1070) 상에 용액 기반의 반도체 산화물 물질을 코팅하여 채널층(1080)을 형성하고, 채널층(1080) 양측에 소스-드레인 전극(1100, 1200)을 형성한다. 채널층(1080)은 예를 들어, 용액 기반의 IGZO(Indium Gallium Zinc Oxide) 물질을 스핀 코팅하거나 나노 압인 또는 잉크젯 프린팅을 하여 터널링 절연막(107) 상에 도포한 후 용액 내 첨가물이나 솔벤트를 날려버리고 IGZO로 된 채널층(108)을 형성할 수 있다. 형성된 IGZO 채널층은 다결정으로서 n형 반도체 물질이며 높은 이동도로 캐리어 전송을 위한 도전 영역으로 기능할 수 있다. Next, as shown in FIG. 23 (f), the channel layer 1080 is formed by coating a solution-based semiconductor oxide material on the tunneling insulating layer 1070, and source-drain electrodes on both sides of the channel layer 1080 are formed. 1100, 1200. The channel layer 1080 is coated on the tunneling insulating layer 107 by, for example, spin-coating a solution-based indium gallium zinc oxide (IGZO) material, or by nano stamping or inkjet printing, to blow off additives or solvents in the solution. A channel layer 108 of IGZO can be formed. The formed IGZO channel layer is a polycrystalline n-type semiconductor material and can function as a conductive region for carrier transfer with high mobility.
용액 기반의 반도체 산화물 코팅 공정에 의한 채널층 형성은 450℃ 미만의 저온에서 용이하게 수행될 수 있다. 채널층(1080) 형성에 사용되는 반도체 산화물로는 상술한 IGZO 이외에, ZnO, IZO, ZTO 등을 사용할 수 있다. 용액 기반의 ZnO, IZO 또는 ZTO 물질을 450℃ 미만의 저온에서 스핀 코팅, 나노 압인 또는 잉크젯 프린팅함으로써 반도체 산화물 채널층 구조를 용이하게 형성할 수 있다. 이러한 용액 기반의 반도체 산화물 물질의 코팅(스핀 코팅, 나노 압인 또는 잉크젯 방법)을 통한 채널층 형성은 가격이 저렴한 공정을 사용할 수 있다는 장점과 플렉시블 기판에도 응용이 가능하다는 장점이 있다.Channel layer formation by a solution-based semiconductor oxide coating process can be easily performed at a low temperature of less than 450 ℃. As the semiconductor oxide used to form the channel layer 1080, in addition to the above-described IGZO, ZnO, IZO, ZTO, or the like may be used. Solution based ZnO, IZO or ZTO materials can be easily formed by spin coating, nano stamping or inkjet printing at temperatures below 450 ° C. The channel layer formation through the coating of the solution-based semiconductor oxide material (spin coating, nano stamping or inkjet method) has the advantage of using an inexpensive process and its application to a flexible substrate.
용액 기반의 IGZO 물질은 예를 들어 다음과 같이 마련될 수 있다. 1.0M의 아연 아세테이트 디하이드레이트((Zn(CH3COO)2ㆍ2H2O), 0.5M의 갈륨 니트레이트 하이드레이트(Ga(NO3)3ㆍ3H2O) 및 인듐 나트레이트 하이드레이트(In(NO3)3ㆍxH2O)를 20mL의 2-메톡시에탄올(2-methoxyethanol) 용매에 용해함으로써 IGZO의 프리커서(precursor)를 준비한다. 여기에 모노에탄올라민(monoethanolamine)을 용액 안정제(stabilizer)로 첨가하고 아세트산(CH3COOH)을 떨어뜨린후 스터링(stirring)하면서 균질한 용액을 만들어준다. 60℃ 정도에서 1시간 동안 강하게 스터링한 후, IGZO 용액이 72시간 정도 동안 에이지(aged)되게 한다. Solution-based IGZO materials can be prepared, for example, as follows. 1.0 M zinc acetate dihydrate ((Zn (CH 3 COO) 2 2 H 2 O), 0.5 M gallium nitrate hydrate (Ga (NO 3 ) 3 3 H 2 O) and indium nitrate hydrate (In (NO 3 ) Prepare a precursor of IGZO by dissolving 3 xH 2 O) in 20 mL of 2-methoxyethanol solvent, where monoethanolamine is added as a solution stabilizer. And drop the acetic acid (CH 3 COOH) and stir to make a homogeneous solution, after strong sterling for 1 h at 60 ° C., allow the IGZO solution to age for 72 h .
소스-드레인 전극(1100, 1200)으로는 예컨대, IZO, Cu, Al, W, MoW, Ti, Ta, Cr, 또는 Ag 등의 물질을 사용할 수 있다. 상술한 공정을 통하여 바텀 제어 게이트형 플래쉬 메모리셀을 유리 기판 또는 플렉시블 기판 위에 만들수 있다. 이러한 셀의 장점은 유리 기판을 사용할 수 있기 때문에 LCD, OLED와 같은 디스플레이에 플래쉬 메모리를 임베디드하여 응용함으로써 SOC(System on chip)를 구현할 수 있다. 뿐만 아니라, 플로팅 게이트를 카본 나노튜브로 대체함으로써 플래쉬 메모리 셀 간의 간섭 문제를 해결할 수 있고, 디바이스 스케일링 문제를 해결할 수 있다.As the source- drain electrodes 1100 and 1200, for example, a material such as IZO, Cu, Al, W, MoW, Ti, Ta, Cr, or Ag may be used. Through the above-described process, a bottom control gate type flash memory cell can be made on a glass substrate or a flexible substrate. The advantage of such a cell is that a glass substrate can be used to implement a SOC (System on chip) by embedding flash memory in a display such as an LCD or an OLED. In addition, replacing the floating gate with carbon nanotubes can solve the interference problem between flash memory cells and solve device scaling problems.
도 24는 다른 실시형태에 따른 플래쉬 메모리 소자의 제조 방법을 나타낸 단면도들로서, 탑 제어 게이트형 플래쉬 메모리 소자의 제조 공정에 해당한다.24 are cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment, and correspond to a process of manufacturing a top control gate type flash memory device.
도 24(a)에 도시된 바와 같이, 기판(2010) 상에 SiO2 버퍼층을 형성한 후, 도 24(b)에 도시된 바와 같이 용액 기반의 IGZO 물질, 또는 용액 기반의 ZnO, IZO 혹은 ZTO 물질을 코팅(스핀코팅, 나노 압인, 잉크젯 코팅)하여 채널층(2080)을 형성하고, 그 위에 너널링 절연막(2070)을 형성한다. After forming the SiO 2 buffer layer on the substrate 2010, as shown in FIG. 24 (a), the solution-based IGZO material, or the solution-based ZnO, IZO, or ZTO material, as shown in FIG. 24 (b). Is coated (spin coated, nano stamped, ink jet coated) to form a channel layer 2080, and a nuling insulating film 2070 is formed thereon.
그 후 도 24(c)에 도시된 바와 같이, 용액 기반의 카본 나노튜브 물질, 또는 용액 기반의 IGZO, ZnO, IZO 혹은 ZTO 물질을 코팅하여 플로팅 게이트층(2050)을 형성한다. Thereafter, as shown in FIG. 24C, the floating gate layer 2050 is formed by coating a solution-based carbon nanotube material or a solution-based IGZO, ZnO, IZO or ZTO material.
다음으로, 도 24(d)에 도시된 바와 같이, 층간 절연막(2040) 및 제어 게이트층(203)을 형성한다. Next, as shown in FIG. 24D, an interlayer insulating film 2040 and a control gate layer 203 are formed.
그리고 나서, 도 24(e)에 도시된 바와 같이, 플로팅 게이트층, 층간 절연막 및 제어 게이트층을 패터닝하고, 도 24(f)에 도시된 바와 같이 소스-드레인 전극(2100, 2200) 및 측벽 절연막(2060) 등을 형성한다. Then, as shown in Fig. 24 (e), the floating gate layer, the interlayer insulating film and the control gate layer are patterned, and as shown in Fig. 24 (f), the source- drain electrodes 2100 and 2200 and the sidewall insulating film are shown. 2060 and the like.
도 25는 기존의 실리콘 반도체 기반의 플래쉬 메모리 셀 위에 상술한 본 발명의 플래쉬 메모리셀 구조/제조 방법을 적용하여 만들어진 3D 적층셀 구조의 플래쉬 메모리 소자의 일례를 나타내는 단면도이다. 도 25를 참조하면, 기존의 도핑된 소스-드레인 영역(3100, 3200)을 갖는 실리콘 반도체 기판(3010)과 터널링 절연막(3070), 제1 플로팅 게이트(3070), 층간 절연막(3040) 및 제1 제어 게이트(3030)는 하부 메모리셀(제1 메모리셀부)을 이룬다. 그 위에 추가적으로 전술한 IGZO 등의 채널층을 사용한 상부 메모리셀(제2 메모리셀부)가 적층되어 있다. 즉, 상호접속용(interconnection) 금속층(350)과 금속간 절연막(3600) 상에, 상술한 용액 기반의 IGZO, ZnO, IZO 또는 ZTO을 코팅(스핀코팅, 나노압인, 잉크젯 프린팅 등)하여 반도체 산화물 채널층(3680)을 형성한다. 채널층(3680) 상에는 터널링 절연막(3670), 제2 플로팅 게이트(3650), 층간 절연막(3640) 및 제2 제어 게이트(3630)가 순차 적층되어 있다. 제2 플로팅 게이트(3650)는 전술한 실시예의 플로팅 게이트(1050, 2050)와 마찬가지로, 용액 기반의 나노튜브 물질, 또는 용액 기반의 IGZO, ZnO, IZO 혹은 ZTO을 코팅하여 형성될 수 있다. FIG. 25 is a cross-sectional view illustrating an example of a flash memory device having a 3D stacked cell structure manufactured by applying the above-described flash memory cell structure / manufacturing method to a conventional silicon semiconductor based flash memory cell. Referring to FIG. 25, a silicon semiconductor substrate 3010 having conventional doped source- drain regions 3100 and 3200, a tunneling insulating film 3070, a first floating gate 3070, an interlayer insulating film 3040, and a first The control gate 3030 forms a lower memory cell (first memory cell unit). On top of that, an upper memory cell (second memory cell portion) using a channel layer such as IGZO described above is stacked. That is, the semiconductor oxide is coated on the interconnection metal layer 350 and the intermetallic insulating film 3600 by coating (spin coating, nanopressure, inkjet printing, etc.) based on the above-described solution-based IGZO, ZnO, IZO or ZTO. Channel layer 3680 is formed. The tunneling insulating layer 3670, the second floating gate 3650, the interlayer insulating layer 3640, and the second control gate 3630 are sequentially stacked on the channel layer 3680. The second floating gate 3650 may be formed by coating a solution-based nanotube material or a solution-based IGZO, ZnO, IZO or ZTO, similar to the floating gates 1050 and 2050 of the above-described embodiment.
전술한 바와 같이 용액 기반의 반도체 산화물 또는 카본 나노튜브 물질의 코팅을 통해 제2 플로팅 게이트(3650)과 채널층(3680)을 형성하기 때문에 450℃이하의 저온공정이 가능하다. 따라서, 현재 사용되고 있는 실리콘 기반의 플래쉬 메모리 셀 위에 적층으로 용액 기반의 반도체 산화물을 사용하여 채널층을 형성할 수 있고, 플로팅 게이트(제2 플로팅 게이트)도 저온 공정으로 카본 나노튜브 또는 반도체 산화물로써 용이하게 만들 수 있다. 또한 상부 메모리셀의 저온 공정은 하부에 있는 소스, 드레인 도핑 영역(3100, 3200) 및 채널 도핑 영역 그리고 상호접속용 금속층(3500)에 영향을 거의 주지 않기 때문에, 3D 적층 구조의 플래쉬 메모리셀을 구현할 수 있다. 따라서, 고밀도를 저비용으로 구현할 수 있어 SSD에의 적용에 유리하다. As described above, since the second floating gate 3650 and the channel layer 3680 are formed by coating a solution-based semiconductor oxide or carbon nanotube material, a low temperature process of 450 ° C. or less is possible. Therefore, it is possible to form a channel layer using a solution-based semiconductor oxide by stacking on a silicon-based flash memory cell currently used, and the floating gate (second floating gate) is also easily formed as a carbon nanotube or a semiconductor oxide in a low temperature process. You can make it. In addition, since the low temperature process of the upper memory cell hardly affects the source, drain doped regions 3100 and 3200 and the channel doped region and the interconnection metal layer 3500 at the bottom, it is possible to implement a flash memory cell having a 3D stacked structure. Can be. Therefore, high density can be realized at low cost, which is advantageous for application to SSDs.
도 26은 다른 실시형태에 따른 3D 적층셀 구조의 플래쉬 메모리 소자를 나타낸 단면도이다. 도 26의 실시형태는, 상부 메모리셀뿐만 아니라 하부 메모리셀에서도 상술한 용액 기반의 반도체 산화물 코팅에 의한 채널층 형성을 적용한 것이다. 26 is a cross-sectional view illustrating a flash memory device having a 3D stacked cell structure according to another embodiment. The embodiment of FIG. 26 applies channel layer formation by the above-described solution-based semiconductor oxide coating not only on the upper memory cell but also on the lower memory cell.
도 26을 참조하면, 기판(4010) 상에 SiO2 버퍼층(4020), 용액 기반의 IGZO, ZnO, IZO 또는 ZTO 물질의 코팅에 의해 형성된 반도체 산화물의 제1 채널층(4080), 터널링 절연막(4070), 제1 플로팅 게이트(4050) 및 제1 제어 게이트(4030)은 하부의 제1 메모리셀부를 이룬다. 그 위에 상호접속용 금속층(4500)과 금속간 절연막(4600)이 형성되어 있다. 금속층(4500)을 사이에 두고, 제1 메모리셀부 위에는, 용액 기반의 IGZO, ZnO, IZO 또는 ZTO 물질의 코팅에 의해 형성된 제2 채널층(4680), 터널링 절연막(4670), 제2 플로팅 게이트(4650) 및 제2 제어 게이트(4630)를 구비하는 제2 메모리셀부가 적층되어 있다. 제1 및 제2 플로팅 게이트(4050, 4650)는 전술한 실시예의 플로팅 게이트(1050, 2050)와 마찬가지로, 용액 기반의 나노튜브 물질, 또는 용액 기반의 IGZO, ZnO, IZO 혹은 ZTO을 코팅하여 형성될 수 있다. 제1 채널층(4080)의 양측에는 소스-드레인 전극(4100, 4200)이 배치되어 있다.Referring to FIG. 26, a SiO 2 buffer layer 4020, a first channel layer 4080 of a semiconductor oxide formed by coating a solution-based IGZO, ZnO, IZO, or ZTO material on a substrate 4010, and a tunneling insulating layer 4070. The first floating gate 4050 and the first control gate 4030 form a lower first memory cell unit. An interconnect metal layer 4500 and an intermetallic insulating film 4600 are formed thereon. The second channel layer 4680, the tunneling insulating film 4670, and the second floating gate (not formed by coating a solution-based IGZO, ZnO, IZO, or ZTO material on the first memory cell portion with the metal layer 4500 interposed therebetween). A second memory cell unit including a 4650 and a second control gate 4630 is stacked. The first and second floating gates 4050 and 4650 may be formed by coating a solution-based nanotube material or a solution-based IGZO, ZnO, IZO or ZTO, similar to the floating gates 1050 and 2050 of the above-described embodiment. Can be. Source- drain electrodes 4100 and 4200 are disposed at both sides of the first channel layer 4080.
액상 공정을 이용한 산화물 박막 트랜지스터 및 그 형성 방법Oxide thin film transistor using liquid phase process and its formation method
산화물 반도체는 기존의 실리콘(Si)을 이용하는 반도체 공정을 대체할 수 있을 것으로 기대하고 있는데, 특히, 산화물 반도체를 이용한 유기발광다이오드(Organic Light Emitting Diodes; OLED) 등의 능동구동소자의 제조에 많은 관심이 집중되고 있다. 또한, 기존 비정질실리콘 반도체소자(Amorphous Si TFT)를 이용하는 액정표시장치(TFT-LCD)의 경우 낮은 이동도로 인해 초고해상도(Ultra High Definition; UHD) 이상의 해상도를 구현하는 것이 어려운데, 이러한 문제를 해결 할 수 있는 대안으로 여겨진다.Oxide semiconductors are expected to replace conventional semiconductor processes using silicon (Si). In particular, much attention is paid to the production of active driving devices such as organic light emitting diodes (OLEDs) using oxide semiconductors. This is concentrated. In addition, in the case of a liquid crystal display (TFT-LCD) using an amorphous Si TFT, it is difficult to realize a resolution higher than Ultra High Definition (UHD) due to low mobility. It is considered to be an alternative.
더욱이 산화물 반도체의 높은 이동도 및 높은 신뢰성 때문에 다른 평판디스플레이로서, 예컨대, 폴리실리콘 액정표시장치, 플렉시블 액정표시장치 등에 이용되는 소자로서 주목받고 있다. 특히, 유기발광다이오드(Organic Light Emitting Diodes; OLED) 등의 능동구동소자에 있어서는, 유기발광다이오드(OLED) 등의 특성 상 소자의 안정성(Stability)이 무엇보다도 중요하기 때문에, 지금까지는 폴리 실리콘(Poly-Si) 등을 이용하여 이러한 소자의 양산에 적용하였다. 하지만 그 제조를 위해 사용하는 ELA(Excimer Laser Annealing)의 특성 상 5세대 이상의 대면적에는 그 적용이 어렵다는 단점이 있다.Moreover, due to the high mobility and high reliability of oxide semiconductors, attention has been drawn to other flat panel displays, for example, as elements used in polysilicon liquid crystal displays, flexible liquid crystal displays, and the like. Particularly, in active driving devices such as organic light emitting diodes (OLEDs), the stability of the devices is important because of the characteristics such as organic light emitting diodes (OLEDs). -Si) and the like was applied to mass production of these devices. However, due to the characteristics of the ELA (Excimer Laser Annealing) used for the manufacturing, there is a disadvantage that the application is difficult to large area of 5 generations or more.
이러한 어려움을 극복하기 위해 산화물 반도체가 제안되었다. 또한 기존의 스퍼터(Sputter) 방법이나 ALD(Atomic Layer Deposition) 등의 진공증착 방법 등이 제안되었지만 그 제조원가가 비싸기 때문에 진공장비에 따른 제조 비용을 감소시키기 위해 스핀코팅(Spin Coating) 또는 잉크젯 방법 등이 제안되었다. 이러한 방법으로 반도체층을 형성하기 위해서는 반도체 물질을 액상으로 만드는 것이 중요한데 이를 졸-겔(Sol-Gel)법이라고 한다. In order to overcome these difficulties, oxide semiconductors have been proposed. In addition, the conventional sputtering method and the vacuum deposition method such as ALD (Atomic Layer Deposition) have been proposed, but the manufacturing cost is high, so spin coating or inkjet method is used to reduce the manufacturing cost according to the vacuum equipment. Proposed. In order to form the semiconductor layer in this way, it is important to make the semiconductor material in a liquid state, which is called a sol-gel method.
하지만, 이러한 졸-겔법을 이용한 방법은, 졸-겔을 만들기 위해 첨가제로써 솔벤트 등이 필요한데, 이러한 첨가제는 후 열처리를 통해 날려보내고 우리가 얻고자하는 순순한 산화물만 남기게 된다. 후 열처리를 위해서는 기존에는 Furnace 등을 이용하여 전체적으로 열을 전달한다. 이러한 열처리는 보통 수백 ℃에서 행해지는데, 그 이하의 온도에서는 산화물이 형성되지 않아서 반도체 특성을 보이지 않게 때문이다. 하지만, 이러한 열처리는 제조비용이 많이 소요되며 Flexible 기판에 적용하는데 걸림돌이 된다.However, the sol-gel method requires a solvent, etc. as an additive in order to make the sol-gel, and these additives are blown through the post-heat treatment and leave only the pure oxide that we want to obtain. For post-heat treatment, conventionally, heat is transferred using Furnace. This heat treatment is usually carried out at several hundred degrees Celsius, since oxides are not formed at temperatures below that and thus exhibit no semiconductor properties. However, this heat treatment is expensive to manufacture and is an obstacle to applying to a flexible substrate.
이에 본 발명의 실시 예는 기판으로의 직접적인 열 전달을 차단할 수 있는 산화물 반도체 박막 및 산화물 박막 트랜지스터 형성 방법을 제공한다.Accordingly, an embodiment of the present invention provides an oxide semiconductor thin film and an oxide thin film transistor forming method capable of blocking direct heat transfer to a substrate.
도 27a 및 도 27b는 본 발명의 일 실시예에 따른 산화물 반도체 박막의 제조방법을 설명하기 위한 단면도이다.27A and 27B are cross-sectional views illustrating a method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention.
먼저, 도 27a에 도시된 바와 같이, 기판(200) 상에 액상 제조공정에 의한 산화물 반도체 수용액(210)을 형성한다. 구체적으로, 예컨대, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 어느 1개 또는 2개 이상의 성분을 포함하는 산화물 반도체를 예컨대, 졸-겔(Sol-Gel)법 등과 같이 액상으로 제조하여 기판(200) 상에 도포한다.First, as shown in FIG. 27A, an oxide semiconductor aqueous solution 210 is formed on a substrate 200 by a liquid phase manufacturing process. Specifically, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 An oxide semiconductor comprising any one or two or more components of O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3 , for example It is manufactured in a liquid state such as a sol-gel method and coated on the substrate 200.
여기서, 기판(200)은 예컨대, 유리, 플라스틱, 실리콘 또는 합성수지와 같은 절연성을 띠는 재질로 형성할 수 있으며, 유리 기판과 같은 투명 기판이 바람직한데, 이에 국한하지는 않는다.Here, the substrate 200 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
이러한 기판(200) 상에 산화물 반도체 수용액(210)을 도포하는 방법으로는, 예컨대, 스크린 프린팅(Screen Printing)법, 스핀 코팅(Spin Coating)법 또는 잉크젯(Ink-jet)법 등을 이용하는 것이 가능하며, 이에 국한되지는 않는다.As a method of coating the oxide semiconductor aqueous solution 210 on the substrate 200, for example, a screen printing method, a spin coating method, or an ink-jet method may be used. It is not limited thereto.
먼저, 스크린 프린팅(Screen Printing)법이라 함은 예컨대, 소정의 산화물 반도체를 액상 제조하여 예컨대, 졸-겔을 형성한 후 예컨대, 실크스크린(Silk Screen) 또는 스테인리스 메쉬(Stainless Mesh) 등의 방법을 통해 눌러 도장 찍듯이 상기 액상 제조된 산화물 반도체를 기판 상에 도포하는 방법이다.First, the screen printing method is, for example, by forming a predetermined oxide semiconductor in a liquid phase, for example, forming a sol-gel, and then, for example, a method such as silk screen or stainless mesh. It is a method of coating the liquid oxide prepared oxide semiconductor on a substrate as if pressed through the coating.
즉, 스크린 프린팅(Screen Printing)법은 예컨대, 일정한 패턴이 형성된 스크린을 기판(200) 상에 올려놓고 예컨대, 소정의 페이스트(Paste)를 압착 전사시킴으로서 원하는 패턴을 기판에 인쇄하는 방법으로서, 공정이 단순하고 설비 비용이 저렴하기 때문에 제품의 양산 시 그 제조단가를 낮출 수 있는 가능성이 있다.That is, the screen printing method is a method of printing a desired pattern on a substrate by, for example, placing a screen on which a predetermined pattern is formed on the substrate 200 and, for example, compressing and transferring a predetermined paste. Because of its simplicity and low cost of equipment, there is a possibility of lowering the manufacturing cost when mass-producing products.
이러한, 스크린 프린팅 방법의 공정 메카니즘(Mechanism)은 예컨대, 스퀴지(Squeegee)와 스크린(Screen), 기판 등이 접촉하는 부위에서 상기 페이스트(Paste)가 스퀴지(Squeegee)보다 정면 방향으로 회전하게 되고, 스크린의 개구부를 아래로 이동시켜 기판과 접촉하여 패턴 부에 충진되는데, 스퀴지가 지나간 후 스크린이 기판에서 분리될 때, 페이스트는 기판 상에 잔존한다. 이때의 스퀴지는 스크린과 기판의 밀착을 균일하고 안정되게 하고, 페이스트의 회전을 안정되게 하는 작용을 하게된다. The process mechanism of the screen printing method is, for example, the paste is rotated in the front direction than the squeegee at the site where the squeegee, the screen, the substrate and the like contact, the screen The opening of is moved downwards in contact with the substrate and filled in the pattern portion. When the screen is separated from the substrate after the squeegee passes, the paste remains on the substrate. At this time, the squeegee serves to make the adhesion between the screen and the substrate uniform and stable, and to stabilize the rotation of the paste.
한편, 스크린 프린팅 방법의 인쇄조건에 크게 영향을 미치는 4 가지 변수는 예컨대, 스크린의 분리를 위한 클리어런스(Clearance), 페이스트의 회전을 위한 스퀴지(Squeegee)의 각도, 기판과의 균일한 밀착을 위해 실제로 가해지는 압력 및 페이스트의 적정한 유동을 위한 스퀴지(Squeegee)의 속도 등이 있다.On the other hand, the four variables that greatly affect the printing conditions of the screen printing method are, for example, the clearance for the separation of the screen, the angle of the squeegee for the rotation of the paste, and the uniform adhesion with the substrate. Pressure applied and the speed of the squeegee for proper flow of the paste.
다음으로, 스핀 코팅법은 졸-겔법에서 가장 많이 이용하는 방법 중 하나이며, 마지막으로, 잉크젯 방법은 향후 플렉시블 디스플레이(Flexible display)에서 가장 주목받을 수 있는 박막 형성 방법으로서, 예컨대, 코팅 후 반도체층에 대한 패터닝(Patterning)이 따로 필요 치 않아서 공정 비용을 줄일 수 있는 장점이 있다. Next, the spin coating method is one of the most used in the sol-gel method, and finally, the inkjet method is a thin film formation method that can be most noticed in a flexible display in the future, for example, to a semiconductor layer after coating There is an advantage in that the process cost can be reduced because there is no need for patterning.
한편, 도27b를 참조하면, 산화물 반도체 수용액(도 27a의 210)을 열처리하여 기판(200) 상에 산화물 반도체 박막(210')을 형성한다.Meanwhile, referring to FIG. 27B, an oxide semiconductor thin film 210 ′ is formed on the substrate 200 by heat treating the oxide semiconductor aqueous solution (210 of FIG. 27A).
상기 열처리는 산화물 반도체 수용액(도 27a의 210)의 제조상 필요한 예컨대, 솔벤트(Solvents) 또는 안정제 등의 첨가제를 증발시켜 제거하기 위한 공정으로서, 본 발명의 일 실시예에 따른 산화물 반도체 박막의 제조방법에서는 예컨대, 레이저(Laser)를 이용하여 열처리함이 바람직하다.The heat treatment is a process for evaporating and removing additives such as solvents or stabilizers necessary for the preparation of the oxide semiconductor aqueous solution (210 of FIG. 27A), and in the method of manufacturing an oxide semiconductor thin film according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
이때, 이용되는 레이저의 종류는 특별히 한정되지 않으며, 예컨대, 엑시머 레이저(Excimer Laser) 등, 본 발명의 일 실시예에 적용할 수 있는 한 다양한 종류의 레이저를 이용하는 것이 가능하다.In this case, the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
이러한 레이저를 이용한 열처리는, 예컨대, 종래의 퍼내스(Furnace)등에 의한 열처리와는 달리, 산화물 반도체 수용액(도 27a의 210)의 열처리 시 수반되는 예컨대, 약 300 ℃ 이상의 고온을 기판(200) 상에 직접 가하는 것을 방지할 수 있기 때문에, 예컨대, 저온에서 이용 가능한 비교적 저렴한 기판을 이용할 수 있게 됨으로서 제조 비용을 절감할 수 있으며, 예컨대, 플렉시블(Flexible )기판 등을 이용하는 것을 가능하게 한다.The heat treatment using the laser is, for example, unlike the conventional heat treatment by Furnace, etc., a high temperature of, for example, about 300 ° C. or higher accompanying the heat treatment of the oxide semiconductor aqueous solution (210 in FIG. 27A) is performed on the substrate 200. Since it is possible to prevent the direct addition to the substrate, for example, it is possible to use a relatively inexpensive substrate that can be used at a low temperature, thereby reducing the manufacturing cost, and making it possible to use, for example, a flexible substrate.
한편, 본 발명의 일 실시예에 따른 산화물 반도체 박막(210')의 제조방법에 따르면, 상기 열처리 후 형성된 산화물 반도체 박막(110') 상에 서로 다른 특성을 갖는 적어도 2개의 영역(P1 및 P2)을 일괄 형성하는 것이 가능하다.Meanwhile, according to the method of manufacturing the oxide semiconductor thin film 210 'according to the embodiment of the present invention, at least two regions P1 and P2 having different characteristics on the oxide semiconductor thin film 110' formed after the heat treatment. It is possible to form a batch.
즉, 1회의 열처리 공정(즉, 레이저빔의 조사에 의한 열처리)을 통하여, 산화물 반도체 박막(210') 상에, 적어도 2개의 영역(P1 및 P2)을 동시에 형성하는 것이 가능한데, 예컨대, 산화물 반도체 박막 상에 반도체 영역(Semi-conductor) 및 도체 영역(Conductor) 등을 동시에 형성하는 것이 가능하다.That is, it is possible to simultaneously form at least two regions P1 and P2 on the oxide semiconductor thin film 210 'through one heat treatment process (that is, heat treatment by irradiation of a laser beam), for example, an oxide semiconductor. It is possible to simultaneously form a semiconductor region (Semi-conductor), a conductor region (Conductor) and the like on the thin film.
이때, 상기 반도체 영역은 예컨대, 캐리어가 약 1×1013 cm-3 내지 9×1016 cm-3 포함되는 것을 말하며, 도체 영역은 예컨대, 캐리어가 약 9×1017 cm-3 이상 포함되는 영역을 말한다. 또한, 이 두 영역은 비결정상(Amorphous phase) 및 다결정질상(Polycrystalline phase) 등을 가질 수 있다.In this case, the semiconductor region refers to, for example, about 1 × 10 13 cm −3 to 9 × 10 16 cm −3 , and the conductor region includes, for example, about 9 × 10 17 cm −3 or more of the carrier. Say In addition, these two regions may have an amorphous phase, a polycrystalline phase, or the like.
한편, 산화물 반도체 박막(210') 상에 형성된 적어도 2개의 영역(P1 및 P2)은, 예컨대, 하프-톤 마스크(Half-tone mask)(M)를 이용함으로서 형성하는 것이 가능한데, 이에 국한하지는 않으며, 하프-톤 마스크(Half-tone mask)(M)와 동일한 기능을 갖는 다른 어떤 수단을 이용하는 것도 가능하다.Meanwhile, at least two regions P1 and P2 formed on the oxide semiconductor thin film 210 'may be formed by using, for example, a half-tone mask M, but is not limited thereto. It is also possible to use any other means having the same function as the half-tone mask M.
즉, 상기 각각의 영역(P1 및 P2)(예컨대, 반도체(Semi-conductor) 영역 및 도체(Conductor) 영역 등)에 대응하도록, 하프-톤 마스크(Half-tone mask)(M) 상의 적어도 2개의 영역(P1' 및 P2')에 대한 밀도(Density)를 달리한 후, 이러한 하프-톤 마스크((Half-tone mask)(M)를 통해 레이저를 조사함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능하다.That is, at least two on the half-tone mask M so as to correspond to the respective regions P1 and P2 (e.g., semi-conductor regions and conductor regions, etc.). After varying the density for the regions P1 'and P2', the lasers with different energy densities are irradiated simultaneously by irradiating the laser through this half-tone mask (M). It is possible to do
예컨대, 하프-톤 마스크(M)의 밀도에 따라 레이저의 투과율을 달리함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능하다.For example, by varying the transmittance of the laser according to the density of the half-tone mask M, it is possible to simultaneously irradiate lasers having different energy densities.
이에 따라, 기판(200) 상에 산화물 반도체 박막(210')을 형성함에 있어서 1회의 열처리 공정으로 적어도 2개의 영역(P1 및 P2)을 동시에 형성할 수 있기 때문에, 예컨대, 마스크 공정의 회수를 줄임으로서, 공정 시간 및 공정 비용 등을 줄일 수 있다.Accordingly, in forming the oxide semiconductor thin film 210 ′ on the substrate 200, at least two regions P1 and P2 may be simultaneously formed in one heat treatment process, thereby reducing the number of mask processes, for example. As a result, the process time and the process cost can be reduced.
도 28a 내지 도 28e 는 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법을 설명하기 위한 단면도로서, 바텀 게이트(Bottom Gate)방식을 적용한 구조이다.28A to 28E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a bottom gate method.
먼저, 도 28a에 도시된 바와 같이, 버퍼층(B)이 형성된 기판(300) 상에 게이트 전극(310)을 형성한다. 여기서, 게이트 전극(310)은 기판(300) 상에 투명성을 띠는 도전성 금속, 예컨대 ITO(indium tin oxide), IZO(indium zinc oxide), ITZO(indium tin zinc oxide), GZO(gallium zinc oxide) 또는 반투명 메탈 중 어느 하나의 금속을 예컨대, 스퍼텅링 등에 의해 증착한 뒤, 이를 소정 형상으로 패터닝하여 형성할 수 있는데, 이에 국한하지는 않는다.First, as shown in FIG. 28A, the gate electrode 310 is formed on the substrate 300 on which the buffer layer B is formed. Here, the gate electrode 310 is a conductive metal having transparency on the substrate 300, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and gallium zinc oxide (GZO). Alternatively, any one of the translucent metals may be formed by depositing, for example, sputtering or the like, and then patterning the metal into a predetermined shape, but is not limited thereto.
또한, 기판(300)은 예컨대, 유리, 플라스틱, 실리콘 또는 합성수지와 같은 절연성을 띠는 재질로 형성할 수 있으며, 유리 기판과 같은 투명 기판이 바람직한데, 이에 국한하지는 않는다.In addition, the substrate 300 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
또한, 버퍼층(B)은 예컨대, 후술할 채널영역(도 2d의 P2)을 형성하는 과정에서 하부 기판(300)에 의한 오염 등을 방지하는 역할을 하며, 필요에 따라서는 버퍼층(B)을 생략하는 것도 가능하다.In addition, the buffer layer B serves to prevent contamination by the lower substrate 300 in the process of forming a channel region (P2 of FIG. 2D), which will be described later. For example, the buffer layer B may be omitted. It is also possible.
한편, 필요에 따라서는, 레이저(Laser)를 이용한 열처리 시 발생할 수 있는 열이 기판(300)으로의 전달되는 것을 막고, 이러한 열을 효과적으로 외부로 배출시킬 수 있는 연전달 방지막(미도시)을 기판(300) 상에 더 형성하는 것도 가능하다.On the other hand, if necessary, it is possible to prevent the heat generated during the heat treatment using a laser (Laser) to prevent the transfer to the substrate 300, the anti-transmission film (not shown) that can effectively discharge such heat to the substrate It is also possible to form further on 300.
이어서, 도 28b에 도시된 바와 같이, 게이트 전극(310)을 포함한 기판(300) 상에 게이트 절연층(320)을 형성한다. 게이트 절연층(320)은 예컨대, 산화막, 질화막 또는 투명 절연성 재료를 예컨대, PECVD(plasma Enhanced Chemical Vapor Deposition) 법 등으로 증착하여 형성할 수 있는데, 이에 국한하지는 않는다.Subsequently, as illustrated in FIG. 28B, a gate insulating layer 320 is formed on the substrate 300 including the gate electrode 310. The gate insulating layer 320 may be formed by, for example, depositing an oxide film, a nitride film, or a transparent insulating material by, for example, a plasma enhanced chemical vapor deposition (PECVD) method, but is not limited thereto.
다음으로, 도 28c에 도시된 바와 같이, 게이트 절연층(320) 상에 산화물 반도체 수용액(330)을 형성하게 된다.Next, as shown in FIG. 28C, the oxide semiconductor aqueous solution 330 is formed on the gate insulating layer 320.
여기서, 산화물 반도체 수용액(230)은 예컨대, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 어느 1개 또는 2개 이상의 성분을 포함하는 산화물 반도체를 예컨대, 졸-겔(Sol-Gel)법 등과 같이 액상으로 제조하여 게이트 절연층(320) 상에 도포하는 것이 가능한데, 예컨대, 스크린 프린팅(Screen Printing)법, 스핀 코팅(Spin Coating)법 또는 잉크젯(Ink-jet)법 등을 이용하는 것이 가능하며, 이에 국한되지는 않는다.Here, the oxide semiconductor aqueous solution 230 is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 At least one of TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3 For example, the oxide semiconductor may be manufactured in a liquid state, such as a sol-gel method, and applied to the gate insulating layer 320. For example, a screen printing method and a spin coating method may be used. It is possible to use the method or the ink-jet (Ink-jet) method and the like, but is not limited thereto.
한편, 도28d에 도시된 바와 같이, 산화물 반도체 수용액(330)을 열처리하여 기판(300) 상에 산화물 반도체 박막(330')을 형성한다.Meanwhile, as shown in FIG. 28D, the oxide semiconductor aqueous solution 330 is heat-treated to form an oxide semiconductor thin film 330 ′ on the substrate 300.
상기 열처리는 산화물 반도체 수용액(도 28c의 330)의 제조상 필요한 예컨대, 솔벤트(Solvents) 또는 안정제 등의 첨가제를 증발시켜 제거하기 위한 공정으로서, 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법에서는 예컨대, 레이저(Laser)를 이용하여 열처리함이 바람직하다.The heat treatment is a process for evaporating and removing additives such as solvents or stabilizers, which are necessary for manufacturing an oxide semiconductor solution (330 of FIG. 28C), and in the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
이때, 이용되는 레이저의 종류는 특별히 한정되지 않으며, 예컨대, 엑시머 레이저(Excimer Laser) 등, 본 발명의 일 실시예에 적용할 수 있는 한 다양한 종류의 레이저를 이용하는 것이 가능하다.In this case, the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
이러한 레이저를 이용한 열처리는, 예컨대, 종래의 퍼내스(Furnace)등에 의한 열처리와는 달리, 산화물 반도체 수용액(도 28c의 330)의 열처리 시 수반되는 예컨대, 약 300 ℃ 이상의 고온을 기판(300) 상에 직접 가하는 것을 방지할 수 있기 때문에, 예컨대, 저온에서 이용 가능한 비교적 저렴한 기판(300)을 이용할 수 있도록 함으로서 제조 비용을 절감할 수 있으며, 예컨대, 플렉시블(Flexible )기판(300) 등을 이용하는 것을 가능하게 한다.Such a heat treatment using the laser is, for example, unlike the conventional heat treatment by Furnace (Furnace, etc.), a high temperature, for example, about 300 ℃ or more involved in the heat treatment of the oxide semiconductor aqueous solution (330 in FIG. 28C) on the substrate 300 Since direct application can be prevented, the manufacturing cost can be reduced, for example, by using a relatively inexpensive substrate 300 that can be used at a low temperature. For example, it is possible to use a flexible substrate 300 or the like. Let's do it.
이때, 상기 열처리 후 형성된 산화물 반도체 박막(330') 상에는 서로 다른 특성을 갖는 적어도 2개의 영역(P1 및 P2)을 일괄 형성하는 것이 가능하다.In this case, at least two regions P1 and P2 having different characteristics may be collectively formed on the oxide semiconductor thin film 330 ′ formed after the heat treatment.
즉, 1회의 열처리 공정(즉, 레이저빔의 조사에 의한 열처리)을 통하여, 산화물 반도체 박막(330') 상에, 적어도 2개의 영역을 동시에 형성하는 것이 가능한데, 예컨대, 소스/드레인 전극을 형성하기 위한 영역(P1) 및 채널 영역(P2) 등을 동시에 형성하는 것이 가능하다.That is, it is possible to simultaneously form at least two regions on the oxide semiconductor thin film 330 'through one heat treatment process (that is, heat treatment by irradiation of a laser beam), for example, to form a source / drain electrode. It is possible to simultaneously form the region P1 and the channel region P2.
이는, 예컨대, 하프-톤 마스크(Half-tone mask)(M)를 이용함으로서 형성하는 것이 가능한데, 이에 국한하지는 않으며, 하프-톤 마스크(Half-tone mask)(M)와 동일한 기능을 갖는 다른 어떤 수단을 이용하는 것도 가능하다.This can be formed, for example, by using a half-tone mask (M), but is not limited to any other having the same function as the half-tone mask (M). It is also possible to use means.
즉, 상기 각각의 영역(예컨대, 소스/드레인 전극을 형성하기 위한 영역(P1) 및 채널 영역(P2) 등)에 대응하도록, 서로 다른 밀도의 적어도 2개의 영역(P1' 및 P2')을 갖는 하프-톤 마스크(Half-tone mask)(M)를 준비한 후, 이러한 하프-톤 마스크((Half-tone mask)(M)를 통해 레이저를 조사함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능하다. That is, at least two regions P1 'and P2' of different densities are provided to correspond to the respective regions (e.g., regions P1 and channel regions P2 for forming source / drain electrodes, etc.). After preparing a half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously by irradiating a laser through the half-tone mask M. It is possible.
예컨대, 하프-톤 마스크(M)의 밀도에 따라 레이저의 투과율을 달리함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능한데, 예컨대, 소오스/드레인 형성 영역(P1)에서는 채널 영역(P2)에서 보다 더 높은 에너지 밀도를 갖는 레이저빔이 조사될 수 있도록, 예컨대, 채널 영역(P2)과 대응하는 일정 영역에 대해서만 하프-톤 마스크(M)에 의해 가려지도록 함으로서, 산화물 반도체 박막(330') 상에 서로 다른 특성을 갖는 2개의 영역을 일괄 형성하는 것이 가능하다.For example, by varying the transmittance of the laser according to the density of the half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously. For example, in the source / drain formation region P1, in the channel region P2, The laser beam having a higher energy density can be irradiated, for example, by being covered by the half-tone mask M only for a certain region corresponding to the channel region P2, thereby forming an image on the oxide semiconductor thin film 330 '. It is possible to collectively form two regions having different characteristics in the.
한편, 레이저에 의한 열처리는, 높은 온도의 열처리를 통하여 소오스/드레인 전극 형성 영역(P1)의 저항을 낮춤으로서 그 영역에 대한 접촉저항(Contact Resistance)의 개선에 따른 TFT 특성을 향상시키는 것도 가능하다.On the other hand, the heat treatment by the laser can improve the TFT characteristics according to the improvement of the contact resistance for the region by lowering the resistance of the source / drain electrode forming region P1 through the heat treatment at a high temperature. .
이후, 필요에 따라서는, 형성된 산화물 반도체 박막(330')을 소정 패턴으로 패터닝 한다. 예컨대, 섬 모양 등으로 패터닝 할 수 있다. Thereafter, as needed, the formed oxide semiconductor thin film 330 'is patterned in a predetermined pattern. For example, it can pattern in an island shape.
도 28e를 참조하면, 상기 형성된 전체 상부에 층간절연층(340)을 형성하고, 층간절연층의 일정영역을 패터닝하여 소오스/드레인 전극(350 및 350')을 형성한다.Referring to FIG. 28E, the interlayer insulating layer 340 is formed on the entire formed portion, and a predetermined region of the interlayer insulating layer is patterned to form source / drain electrodes 350 and 350 ′.
한편, 이러한 바텀 게이트 구조는, 다른 말로 역스태거드(Inverted staggered) 구조라고도 하며, 현재 예컨대, AMLCD 등에서 보편적으로 사용하는 구조로서 여러 가지 장점을 가지는데, 특히 마스크(Mask)의 저감이 용이하여 양산 시 경비를 절감할 수 있는 이점이 있다.On the other hand, such a bottom gate structure, also referred to as an inverted staggered structure, in other words, has a number of advantages as a structure commonly used in, for example, AMLCD, etc. In particular, the mask (Mask) is easy to mass-produce There is an advantage in reducing city expenses.
도 29a 내지 도 29e는 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법을 설명하기 위한 단면도로서, 톱 게이트(Top Gate)방식을 적용한 구조이다.29A to 29E are cross-sectional views illustrating a method of manufacturing an oxide thin film transistor according to an exemplary embodiment of the present invention and have a top gate method.
먼저, 도 29a에 도시된 바와 같이, 버퍼층(B)이 형성된 기판(400) 상에 산화물 반도체 수용액(410)을 형성한다.First, as illustrated in FIG. 29A, the oxide semiconductor aqueous solution 410 is formed on the substrate 400 on which the buffer layer B is formed.
여기서, 기판(400)은 예컨대, 유리, 플라스틱, 실리콘 또는 합성수지와 같은 절연성을 띠는 재질로 형성할 수 있으며, 유리 기판과 같은 투명 기판이 바람직한데, 이에 국한하지는 않는다.Here, the substrate 400 may be formed of an insulating material such as, for example, glass, plastic, silicon, or synthetic resin, and a transparent substrate such as a glass substrate is preferable, but is not limited thereto.
또한, 버퍼층(B)은 예컨대, 채널 영역(도 3b의 P2)을 형성하는 과정에서 하부 기판(400)에 의한 오염 등을 방지하는 역할을 하며, 필요에 따라서는 버퍼층(B)을 생략하는 것도 가능하다.In addition, the buffer layer B serves to prevent, for example, contamination by the lower substrate 400 in the process of forming the channel region (P2 of FIG. 3B), and omits the buffer layer B as necessary. It is possible.
이때, 필요에 따라서는, 레이저(Laser)를 이용한 열처리 시 발생할 수 있는 열이 기판(400)으로의 전달되는 것을 막고, 이러한 열을 효과적으로 외부로 배출시킬 수 있는 연전달 방지막(미도시)을 기판(400) 상에 더 형성하는 것도 가능하다.At this time, if necessary, the substrate prevents the heat generated during the heat treatment using a laser (Laser) to prevent the transfer to the substrate 400, the anti-transmission film (not shown) that can effectively discharge the heat to the substrate It is also possible to form further on 400.
한편, 산화물 반도체 수용액(410)은 예컨대, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 어느 1개 또는 2개 이상의 성분을 포함하는 산화물 반도체를 예컨대, 졸-겔(Sol-Gel)법 등을 통해 액상으로 제조하여 도포하는 것이 가능한데, 예컨대, 스크린 프린팅(Screen Printing)법, 스핀 코팅(Spin Coating)법 또는 잉크젯(Ink-jet)법 등을 이용하는 것이 가능하며, 이에 국한되지는 않는다.On the other hand, the oxide semiconductor aqueous solution 410 is, for example, InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 At least one of TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5, or TiSrO 3 For example, the oxide semiconductor may be manufactured and applied in a liquid phase through a sol-gel method, for example, a screen printing method, a spin coating method, or an ink-jet method. Law, etc., but is not limited to such.
이후, 도29b에 도시된 바와 같이, 산화물 반도체 수용액(410)을 열처리하여 기판(400) 상에 산화물 반도체 박막(410')을 형성한다.Thereafter, as shown in FIG. 29B, the oxide semiconductor aqueous solution 410 is heat-treated to form an oxide semiconductor thin film 410 ′ on the substrate 400.
상기 열처리는 산화물 반도체 수용액(도 29a의 410)의 제조상 필요한 예컨대, 솔벤트(Solvents), 안정제 등의 첨가제를 증발시켜 제거하기 위한 공정으로서, 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법에서는 예컨대, 레이저(Laser)를 이용하여 열처리함이 바람직하다.The heat treatment is a process for evaporating and removing additives, for example, solvents and stabilizers, which are necessary for the preparation of an aqueous oxide semiconductor solution (410 of FIG. 29A), and in the method of manufacturing an oxide thin film transistor according to an embodiment of the present invention, For example, it is preferable to heat-treat using a laser.
이때, 이용되는 레이저의 종류는 특별히 한정되지 않으며, 예컨대, 엑시머 레이저(Excimer Laser) 등, 본 발명의 일 실시예에 적용할 수 있는 한 다양한 종류의 레이저를 이용하는 것이 가능하다.In this case, the type of laser used is not particularly limited, and various kinds of lasers can be used as long as it can be applied to an embodiment of the present invention, such as an excimer laser.
이러한 레이저를 이용한 열처리는, 전술한 바와 같이, 산화물 반도체 수용액(도 29a의 410)의 열처리 시 수반되는 예컨대, 약 300 ℃ 이상의 고온을 기판(400) 상에 직접 가하는 것을 방지할 수 있기 때문에, 예컨대, 저온에서 이용 가능한 비교적 저렴한 기판(400)을 이용할 수 있도록 함으로서 제조 비용을 절감할 수 있으며, 예컨대, 플렉시블(Flexible)기판(400) 등을 이용하는 것을 가능하게 한다.As described above, the heat treatment using the laser can prevent direct application of a high temperature of, for example, about 300 ° C. or higher, which is involved in the heat treatment of the oxide semiconductor aqueous solution (410 of FIG. 29A), directly on the substrate 400. By using a relatively inexpensive substrate 400 that can be used at low temperatures, the manufacturing cost can be reduced, and for example, the flexible substrate 400 can be used.
이때, 상기 열처리 후 형성된 산화물 반도체 박막(410') 상에는 서로 다른 특성을 갖는 적어도 2개의 영역(P1 및 P2)을 일괄 형성하는 것이 가능하다.In this case, at least two regions P1 and P2 having different characteristics may be collectively formed on the oxide semiconductor thin film 410 ′ formed after the heat treatment.
즉, 1회의 열처리 공정(즉, 레이저빔의 조사에 의한 열처리)을 통하여, 산화물 반도체 박막(410') 상에, 적어도 2개의 영역을 동시에 형성하는 것이 가능한데, 예컨대, 소스/드레인 전극을 형성하기 위한 영역(P1) 및 채널 영역(P2) 등을 동시에 형성하는 것이 가능하다.That is, it is possible to simultaneously form at least two regions on the oxide semiconductor thin film 410 'through one heat treatment process (that is, heat treatment by irradiation of a laser beam), for example, to form source / drain electrodes. It is possible to simultaneously form the region P1 and the channel region P2.
이는, 예컨대, 하프-톤 마스크(Half-tone mask)(M)를 이용함으로서 형성하는 것이 가능한데, 이에 국한하지는 않으며, 하프-톤 마스크(Half-tone mask)(M)와 동일한 기능을 갖는 다른 어떤 수단을 이용하는 것도 가능하다.This can be formed, for example, by using a half-tone mask (M), but is not limited to any other having the same function as the half-tone mask (M). It is also possible to use means.
즉, 상기 각각의 영역(예컨대, 소스/드레인 전극을 형성하기 위한 영역(P1) 및 채널 영역(P2) 등)에 대응하도록, 서로 다른 밀도의 적어도 2개의 영역(P1' 및 P2')을 갖는 하프-톤 마스크(Half-tone mask)(M)를 준비한 후, 이러한 하프-톤 마스크((Half-tone mask)(M)를 통해 레이저를 조사함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능하다. That is, at least two regions P1 'and P2' of different densities are provided to correspond to the respective regions (for example, regions P1 and channel regions P2 for forming source / drain electrodes, etc.). After preparing a half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously by irradiating a laser through the half-tone mask M. It is possible.
예컨대, 하프-톤 마스크(M)의 밀도에 따라 레이저의 투과율을 달리함으로서 서로 다른 에너지 밀도를 갖는 레이저를 동시에 조사하는 것이 가능한데, 예컨대, 소오스/드레인 형성 영역(P1)에서는 채널 영역(P2)에서 보다 더 높은 에너지 밀도를 갖는 레이저빔이 조사될 수 있도록, 예컨대, 채널 영역(P2)과 대응하는 일정 영역에 대해서만 하프-톤 마스크(M)에 의해 가려지도록 함으로서, 산화물 반도체 박막(310‘) 상에 서로 다른 특성을 갖는 2개의 영역을 일괄 형성하는 것이 가능하다.For example, by varying the transmittance of the laser according to the density of the half-tone mask M, it is possible to irradiate lasers having different energy densities simultaneously. For example, in the source / drain formation region P1, in the channel region P2, The laser beam having a higher energy density can be irradiated, for example, by being covered by the half-tone mask M only for a certain region corresponding to the channel region P2, thereby forming an image on the oxide semiconductor thin film 310 '. It is possible to collectively form two regions having different characteristics in the.
한편, 레이저에 의한 열처리는, 높은 온도의 열처리를 통하여 소오스/드레인 전극 형성 영역(P1)의 저항을 낮춤으로서 그 영역에 대한 접촉저항(Contact Resistance)의 개선에 따른 TFT 특성을 향상시키는 것도 가능하다.On the other hand, the heat treatment by the laser can improve the TFT characteristics according to the improvement of the contact resistance for the region by lowering the resistance of the source / drain electrode forming region P1 through the heat treatment at a high temperature. .
이후, 필요에 따라서는, 형성된 산화물 반도체 박막(310')을 소정 패턴으로 패터닝 한다. 예컨대, 섬 모양으로 패터닝 할 수 있다. Then, if necessary, the formed oxide semiconductor thin film 310 'is patterned in a predetermined pattern. For example, it can pattern in an island shape.
이어서, 도 29c에 도시된 바와 같이, 산화물 반도체 박막(410')의 상부에 게이트 절연층(420)을 형성한다.Next, as illustrated in FIG. 29C, a gate insulating layer 420 is formed on the oxide semiconductor thin film 410 ′.
게이트 절연층(420)은 예컨대, 산화막, 질화막 또는 투명 절연성 재료를 예컨대, PECVD(plasma Enhanced Chemical Vapor Deposition) 법 등으로 증착하여 형성할 수 있는데, 이에 국한하지는 않는다.The gate insulating layer 420 may be formed by, for example, depositing an oxide film, a nitride film, or a transparent insulating material by, for example, a plasma enhanced chemical vapor deposition (PECVD) method, but is not limited thereto.
이후, 도 29d에 도시된 바와 같이, 게이트 전연층(420) 상에 게이트 전극(430)을 형성한다. 구체적으로, 기판(400) 상에 투명성을 띠는 도전성 금속, 예컨대 ITO(indium tin oxide), IZO (indium zinc oxide), ITZO(indium tin zinc oxide), GZO(gallium zinc oxide) 또는 반투명 메탈 중 어느 하나의 금속을 예컨대, 스퍼텅링 등에 의해 증착한 뒤, 이를 소정 형상으로 패터닝하여 형성할 수 있는데, 이에 국한하지는 않는다.Thereafter, as shown in FIG. 29D, the gate electrode 430 is formed on the gate leading layer 420. Specifically, any conductive metal having transparency on the substrate 400, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), or translucent metal One metal may be formed by depositing, for example, sputtering or the like, and then patterning the metal into a predetermined shape, but is not limited thereto.
도 29e를 참조하면, 상기 형성된 전체 상부에 층간절연층(440)을 형성하고, 층간절연층(440)의 일정영역을 패터닝하여 소오스/드레인 전극(450 및 450')을 형성한다.Referring to FIG. 29E, an interlayer insulating layer 440 is formed over the entire formed layer, and a region of the interlayer insulating layer 440 is patterned to form source / drain electrodes 450 and 450 ′.
한편, 이러한 탑 게이트 구조는, 다른 말로 코플라나(Coplanar) 구조라고 부르며, 채널 영역(P1)의 형성 이후에 게이트 메탈이 형성되기 때문에 채널 영역(P1) 형성 시 열 전달이 고르게 일어날 수 있는 장점이 있다.On the other hand, the top gate structure, in other words, the coplanar structure (Coplanar) structure, because the gate metal is formed after the formation of the channel region (P1) has the advantage that the heat transfer can occur evenly when forming the channel region (P1). have.
이러한 탑 게이트 구조는, 본 발명의 일 실시예에서와 같이 엑시머 레이저(ELA) 또는 SLS 등과 같은 레이저 열처리(Laser Annealing)을 이용하는 폴리 실리콘(P-Si) TFT의 경우 이 구조를 주로 채택한다. 이는 레이저 에너지가 하부 게이트 메탈에 의해 국부적으로 달라지는 것을 방지할 수 있기 때문에 그레인 사이즈(Grain Size)를 일정하게 형성할 수 있기 때문이다.This top gate structure mainly adopts this structure in the case of a polysilicon (P-Si) TFT using laser annealing such as excimer laser (ELA) or SLS as in one embodiment of the present invention. This is because the grain size can be made constant because the laser energy can be prevented from being locally changed by the lower gate metal.
도 30 및 도 31은 본 발명의 일 실시예에 따른 산화물 박막 트랜지스터의 제조방법이 적용된 액정표시장치의 백플레인구조를 설명하기 위한 평면도 및 단면도로서, 바텀 게이트(Bottom Gate)방식을 일 예로서 설명하였지만, 이에 국한되지는 않으며 톱 게이트(Top Gate)가 적용되는 것도 가능하다.30 and 31 are plan views and cross-sectional views illustrating a backplane structure of a liquid crystal display device to which a method of manufacturing an oxide thin film transistor according to an embodiment of the present invention is applied, but the bottom gate method is described as an example. However, the present invention is not limited thereto, and a top gate may be applied.
도 30 및 도 31을 참조하면, 액정표시장치의 백플레인은 기판(500) 상에 서로 교차되는 복수개의 게이트 라인들(510)과 데이터 라인들(520)을 구비하고 이들에 의해 정의되는 각 단위픽셀(L1 및 L2)들 및 이들이 교차되는 영역에 형성된 박막트랜지스터를 구비한다.30 and 31, a backplane of a liquid crystal display includes a plurality of gate lines 510 and data lines 520 crossing each other on a substrate 500, and each unit pixel defined by them. L1 and L2 and the thin film transistor formed in the area where they cross.
박막 트랜지스터는 게이트 라인(510)의 일부가 돌출되어 형성된 게이트 전극(510)과, 선택적으로 패터닝되어 있는 산화물 반도체 박막(530)을 구비하고, 게이트 전극(510)과 산화물 반도체 박막(530)을 전기적으로 절연시키는 게이트 절연층(540)을 구비한다.The thin film transistor includes a gate electrode 510 formed by protruding a portion of the gate line 510, and an oxide semiconductor thin film 530 that is selectively patterned, and electrically connects the gate electrode 510 and the oxide semiconductor thin film 530. A gate insulating layer 540 is insulated from the substrate.
이때, 본 발명의 일 실시예에 적용된 산화물 반도체 박막(530)은, 게이트 절연층(540)의 일정 영역에 산화물 반도체 수용액을 도포한 후, 전술한 도 28c 및 도28d를 통해 설명한 바와 같이, 일정 패턴의 하프-톤 마스크(Half-tone mask) 및 레이저빔을 이용한 열처리 공정을 수행함으로서 형성될 수 있는데, 산화물 반도체 박막(530) 상에는 각각의 소스/드레인 전극 형성 영역(P1) 및 채널영역(P2)이 일괄 형성될 수 있다. In this case, in the oxide semiconductor thin film 530 applied to the exemplary embodiment of the present invention, after the oxide semiconductor aqueous solution is applied to a predetermined region of the gate insulating layer 540, as described above with reference to FIGS. 28C and 28D, It can be formed by performing a heat treatment process using a half-tone mask of the pattern and a laser beam, each of the source / drain electrode formation region (P1) and the channel region (P2) on the oxide semiconductor thin film 530. ) May be formed in a batch.
이러한 산화물 반도체 박막(530)의 소스/드레인 전극 형성 영역(P1)은 픽셀(L1 및 L2) 내에서 데이터 신호를 전달하기 위한 소정의 전극을 형성하기 위한 영역으로 활용하는 것이 가능하다.The source / drain electrode formation region P1 of the oxide semiconductor thin film 530 may be used as a region for forming a predetermined electrode for transmitting a data signal in the pixels L1 and L2.
예컨대, 액정표시장치에 있어서는 데이터 라인(520)을 통해 인가되는 데이터 신호를 박막트랜지스터를 통해 전달하고, 전달된 데이터 신호는 액정의 양단 중 일면에 전압을 인가하기 위한 화소전극(550)으로 전달할 수 있다.For example, in the liquid crystal display, a data signal applied through the data line 520 may be transmitted through the thin film transistor, and the transferred data signal may be transferred to the pixel electrode 550 for applying a voltage to one surface of both ends of the liquid crystal. have.
전술한 본 발명에 따른 산화물 반도체 박막 및 산화물 박막 트랜지스터의 제조방법에 대한 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 특허청구범위와 발명의 상세한 설명 및 첨부한 도면의 범위 안에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 본 발명에 속한다.Although preferred embodiments of the method for manufacturing the oxide semiconductor thin film and the oxide thin film transistor according to the present invention have been described above, the present invention is not limited thereto, but the scope of the claims and the detailed description of the invention and the accompanying drawings are various. It is possible to carry out the transformation by the branch and this also belongs to this invention.
본 발명의 실시 예들은 스퍼터링 증착법을 이용한 산화물 반도체 박막을 대신하여, 트랜지스터 액정 디스플레이, 유기 전계발광 디스플레이, 태양전지, 이미지 센서 등에 필요한 투명 산화막을 제공할 뿐만 아니라 기존의 비정질 혹은 다결정 실리콘 박막의 대체도 가능하다.Exemplary embodiments of the present invention provide a transparent oxide film required for a transistor liquid crystal display, an organic electroluminescent display, a solar cell, an image sensor, etc. in place of an oxide semiconductor thin film using a sputtering deposition method, and also replaces an existing amorphous or polycrystalline silicon thin film. It is possible.
본 발명의 실시 예들은 저온 플래쉬 메모리 공정에 적용할 수 있다.Embodiments of the present invention can be applied to a low temperature flash memory process.
본 발명의 실시 예들은 유리 기판 또는 PET 등의 플렉시블 기판의 적용 가능성으로 인해, LCD, OLED와 같은 디스플레이에 플래쉬 메모리 소자를 임베디드하여 SOC(system on chip)을 구현하는 데에 효과적이다.Embodiments of the present invention are effective in implementing a system on chip (SOC) by embedding a flash memory device in a display such as an LCD or an OLED due to the applicability of a flexible substrate such as a glass substrate or PET.
본 발명의 실시 예들은 3D 적층셀 구현으로 고집적도의 비휘발성 메모리 장치를 저비용으로 제작할 수 있고 이로써 대용량 SSD에의 적용에 유리하다.Embodiments of the present invention can manufacture a highly integrated nonvolatile memory device at low cost by implementing a 3D stacked cell, which is advantageous for application to a large capacity SSD.

Claims (54)

  1. (a) 기판 상에 절연막을 형성하는 단계;(a) forming an insulating film on the substrate;
    (b) 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계;(b) depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film;
    (c) 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계;(c) drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel;
    (d) 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계; 및(d) drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And
    (e) 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계를 포함하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.(e) drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
  2. 제1 항에 있어서,According to claim 1,
    상기 단계(a)에서, 상기 절연막은 실리콘 산화막 또는 질화막인 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.In the step (a), the insulating film is a silicon oxide film or a nitride film crystallization method of the oxide semiconductor thin film using a liquid manufacturing base, characterized in that.
  3. 제1 항에 있어서,According to claim 1,
    상기 단계(a) 이후에, 상기 기판과 산화화합물 졸의 안정적인 결합 향상을 위하여 플라즈마 혹은 용액처리를 수행하는 단계를 더 포함하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.After the step (a), further comprising the step of performing a plasma or solution treatment to improve the stable bond between the substrate and the oxide compound sol crystallization method of the oxide semiconductor thin film using a liquid manufacturing base.
  4. 제1 항에 있어서,According to claim 1,
    상기 단계(b)에서, 상기 산화화합물 졸은 스핀 코팅 또는 잉크젯 프린팅을 이용하여 증착하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.In the step (b), the oxide sol is deposited by using spin coating or inkjet printing crystallization method of the oxide semiconductor thin film using a liquid manufacturing base.
  5. 제1 항에 있어서,According to claim 1,
    상기 단계(c) 이후에, 상기 단계(b) 및 단계(c)의 졸겔 공정을 적어도 한 번 반복 수행하는 단계를 더 포함하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.After the step (c), further comprising repeating the sol-gel process of step (b) and step (c) at least once, crystallization method of the oxide semiconductor thin film using a liquid-based manufacturing base.
  6. 제1 항에 있어서,According to claim 1,
    상기 단계(e) 이후에, 상기 단계(b) 내지 단계(d)를 재 수행한 후 상기 최초 투명 결정질 반도체 박막을 결정화 핵 층으로 이용하여 상기 단계(e)를 재 수행하는 단계를 더 포함하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.After the step (e), after performing the steps (b) to (d) again, further comprising the step of performing the step (e) again using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer Crystallization method of an oxide semiconductor thin film using a liquid manufacturing base, characterized in that.
  7. 제1 항에 있어서,According to claim 1,
    상기 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물 중 선택된 적어도 어느 하나의 산화화합물의 몰비를 조절하여 상기 투명 결정질 산화물 반도체 박막의 결정화를 조절하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.Oxide semiconductor using a liquid-based manufacturing method characterized in that to control the crystallization of the transparent crystalline oxide semiconductor thin film by adjusting the molar ratio of at least one oxide selected from the zinc compound, indium compound, gallium compound, tin compound and tantalum compound Crystallization method of thin film.
  8. 제1 항에 있어서,According to claim 1,
    상기 제1 열처리 공정은 상기 산화화합물 졸에 포함되어 있는 용매와 안정제들을 증발시키고 각 화합물의 화학적 분해를 도와주는 것으로서, 상기 제1 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 250℃ 내지 450℃ 온도 범위로 1시간 동안 수행하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.The first heat treatment process is to help evaporate the solvents and stabilizers contained in the oxidized compound sol and to chemically decompose each compound. The first heat treatment process is performed to change the temperature according to the treatment time, and is 250 ° C. to Crystallization method of the oxide semiconductor thin film using a liquid-based manufacturing, characterized in that carried out for 1 hour at 450 ℃ temperature range.
  9. 제1 항에 있어서,According to claim 1,
    상기 제2 열처리 공정은 화합물에 포함된 유기적 성분들이 다 증발되어 산화막 반도체로 이루어지게 하는 것으로서, 상기 제2 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 600℃ 내지 800℃ 온도 범위로 24시간 동안 수행하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.The second heat treatment process is to allow the organic components contained in the compound to be evaporated to form an oxide semiconductor, the second heat treatment process is performed so that the temperature is changed according to the treatment time, 24 to 600 ℃ to 800 ℃ temperature range Crystallization method of an oxide semiconductor thin film using a liquid-based manufacturing, characterized in that carried out for a time.
  10. 제1 항에 있어서,According to claim 1,
    상기 제3 열처리 공정을 통해 비정질 상의 막을 투명한 나노 결정질 상의 막으로 이루어지게 하는 것으로서, 상기 제3 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 900℃ 내지 1100℃ 온도 범위로 24시간 동안 수행하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.Through the third heat treatment process to make the amorphous phase of the film as a transparent nano-crystalline phase, the third heat treatment process is performed so that the temperature is changed in accordance with the treatment time, carried out in a temperature range of 900 ℃ to 1100 ℃ 24 hours Crystallization method of the oxide semiconductor thin film using a liquid manufacturing base, characterized in that.
  11. (a') 기판 상에 절연막을 형성하는 단계;(a ') forming an insulating film on the substrate;
    (b') 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계;(b ') depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film;
    (c') 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계;(c ') drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel;
    (d') 상기 산화화합물 겔 상에 상기 단계(b‘) 및 단계(c’)의 졸겔 공정을 적어도 한 번 반복 수행하는 단계;(d ') repeating the sol-gel process of steps (b') and (c ') at least once on the oxidized compound gel;
    (e') 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계; 및(e ') drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film; And
    (f') 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계를 포함하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.(f ') drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film.
  12. (a") 기판 상에 절연막을 형성하는 단계;(a ") forming an insulating film on the substrate;
    (b") 상기 절연막 상에 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물로 이루어진 군 중에서 선택된 적어도 1종의 산화화합물 졸을 증착하는 단계;(b ") depositing at least one oxide sol selected from the group consisting of zinc compounds, indium compounds, gallium compounds, tin compounds, and tantalum compounds on the insulating film;
    (c") 제1 열처리 공정을 통해 상기 산화화합물 졸을 건조 및 가열하여 산화화합물 겔로 형성하는 단계;(c ") drying and heating the oxidized compound sol through a first heat treatment process to form an oxidized compound gel;
    (d") 제2 열처리 공정을 통해 상기 산화화합물 겔을 건조 및 가열하여 불투명 비정질 산화물 반도체 박막을 형성하는 단계;(d ") drying and heating the oxidized compound gel through a second heat treatment process to form an opaque amorphous oxide semiconductor thin film;
    (e") 제3 열처리 공정을 통해 상기 불투명 비정질 반도체 박막을 건조 및 가열하여 투명 결정질 산화물 반도체 박막을 형성하는 단계; 및(e ") drying and heating the opaque amorphous semiconductor thin film through a third heat treatment process to form a transparent crystalline oxide semiconductor thin film; and
    (f") 상기 투명 결정질 산화물 반도체 박막 상에 상기 단계(b“) 내지 단계(d”)를 재 수행한 후, 상기 최초 투명 결정질 반도체 박막을 결정화 핵 층으로 이용하여 상기 단계(e“)를 재 수행하는 단계를 포함하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.(f ") re-performing the steps (b") to (d ") on the transparent crystalline oxide semiconductor thin film, and then using the first transparent crystalline semiconductor thin film as a crystallization nucleus layer, performing step (e"). Crystallization method of an oxide semiconductor thin film using a liquid-based manufacturing step comprising the step of performing again.
  13. 제12 항에 있어서,The method of claim 12,
    상기 단계(f)에서, 상기 최초 투명 결정질 산화물 반도체 박막과 상기 단계(b")에서의 산화화합물 졸 사이에 안정적인 결합 향상을 위하여 플라즈마 혹은 용액처리로 친수성 및 소수성을 형성하는 단계를 더 포함하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.In the step (f), further comprising the step of forming hydrophilicity and hydrophobicity by plasma or solution treatment to improve the stable bonding between the first transparent crystalline oxide semiconductor thin film and the oxide compound sol in step (b ") Crystallization method of an oxide semiconductor thin film using the liquid-based manufacturing method.
  14. 제11 항 또는 제12 항에 있어서,The method of claim 11 or 12,
    상기 아연화합물, 인듐화합물, 갈륨화합물, 주석화합물 및 탄탈륨화합물 중 선택된 적어도 어느 하나의 산화화합물의 몰비를 조절하여 상기 투명 결정질 산화물 반도체 박막의 결정화를 조절하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.Oxide semiconductor using a liquid-based manufacturing method characterized in that to control the crystallization of the transparent crystalline oxide semiconductor thin film by adjusting the molar ratio of at least one oxide selected from the zinc compound, indium compound, gallium compound, tin compound and tantalum compound Crystallization method of thin film.
  15. 제11 항 또는 제12 항에 있어서,The method of claim 11 or 12,
    상기 제1 열처리 공정은 상기 산화화합물 졸에 포함되어 있는 용매와 안정제들을 증발시키고 각 화합물의 화학적 분해를 도와주는 것으로, 상기 제1 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 250℃ 내지 450℃ 온도 범위로 1시간 동안 수행하고,The first heat treatment process is to evaporate the solvents and stabilizers contained in the oxidized compound sol and to help the chemical decomposition of each compound, the first heat treatment process is performed so that the temperature is changed according to the treatment time, 250 ℃ to 1 hour in the 450 ℃ temperature range,
    상기 제2 열처리 공정은 화합물에 포함된 유기적 성분들이 다 증발되어 산화막 반도체로 이루어지게 하는 것으로, 상기 제2 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 600℃ 내지 800℃ 온도 범위로 24시간 동안 수행하며,The second heat treatment process is such that the organic components contained in the compound are all evaporated to form an oxide semiconductor, and the second heat treatment process is performed so that the temperature is changed according to the treatment time, and the temperature range is 600 ° C. to 800 ° C. 24. For hours,
    상기 제3 열처리 공정을 통해 비정질 상의 막을 투명한 나노 결정질 상의 막으로 이루어지게 하는 것으로, 상기 제3 열처리 공정은 처리 시간에 따라 온도가 변화되도록 수행하며, 900℃ 내지 1100℃ 온도 범위로 24시간 동안 수행하는 것을 특징으로 하는 액상제조 기반을 이용한 산화물 반도체 박막의 결정화 방법.Through the third heat treatment process to make the amorphous phase of the film as a transparent nano-crystalline phase, the third heat treatment process is carried out to change the temperature according to the treatment time, carried out in the temperature range of 900 ℃ to 1100 ℃ 24 hours Crystallization method of the oxide semiconductor thin film using a liquid manufacturing base, characterized in that.
  16. 기판, 채널층, 플로팅 게이트 및 제어 게이트를 구비하는 플래쉬 메모리 소자의 제조 방법에 있어서, In the method of manufacturing a flash memory device having a substrate, a channel layer, a floating gate and a control gate,
    상기 채널층은 용액 기반의 반도체 산화물 물질을 코팅하여 형성되는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The channel layer is formed by coating a solution-based semiconductor oxide material, characterized in that the flash memory device manufacturing method.
  17. 제16항에 있어서,The method of claim 16,
    상기 채널층은 용액 기반의 IGZO 물질을 코팅하여 형성되는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The channel layer is a method of manufacturing a flash memory device, characterized in that formed by coating a solution-based IGZO material.
  18. 제16항에 있어서,The method of claim 16,
    상기 채널층은 용액 기반의 ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The channel layer may be formed by coating a material selected from a solution-based ZnO, IZO and ZTO.
  19. 제16항에 있어서,The method of claim 16,
    상기 플로팅 게이트는 용액 기반의 카본 나노튜브 물질을 코팅하여 형성되는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The floating gate is a method of manufacturing a flash memory device, characterized in that formed by coating a solution-based carbon nanotube material.
  20. 제19항에 있어서,The method of claim 19,
    상기 카본 나노튜브 물질은 SWNT, MWNT, 그라펜(graphene) 및 플러렌(fullerene) 중 적어도 1종을 포함하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The carbon nanotube material may include at least one of SWNT, MWNT, graphene, and fullerene.
  21. 제16항에 있어서,The method of claim 16,
    상기 플로팅 게이트는 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성되는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The floating gate is formed by coating a material selected from a solution-based IGZO, ZnO, IZO and ZTO.
  22. 제16항에 있어서,The method of claim 16,
    상기 채널층은 스핀 코팅(spin coating), 나노 압인(nano imprinting) 및 잉크젯 프린팅 중에서 선택된 공정을 이용하여 형성되는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.And the channel layer is formed using a process selected from spin coating, nano imprinting, and inkjet printing.
  23. 제16항에 있어서,The method of claim 16,
    상기 플래쉬 메모리 소자는 바텀 제어 게이트형 소자이고, 상기 기판 위에 상기 제어 게이트와 플로팅 게이트를 형성한 후에 상기 채널층을 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The flash memory device is a bottom control gate type device, and the channel layer is formed after the control gate and the floating gate are formed on the substrate.
  24. 제16항에 있어서,The method of claim 16,
    상기 플래쉬 메모리 소자는 탑 제어 게이트형 소자이고, 상기 기판 위에 상기 채널층을 형성한 후에 상기 플로팅 게이트 및 제어 게이트를 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The flash memory device is a top control gate type device, wherein the floating gate and the control gate are formed after the channel layer is formed on the substrate.
  25. 제16항에 있어서,The method of claim 16,
    상기 기판은 유리 기판, 플라스틱 기판 및 실리콘 기판 중에서 어느 하나의 기판인 것을 특징으로 하는 플래쉬 메모리 소자의 제조 방법.The substrate is a method of manufacturing a flash memory device, characterized in that any one of a glass substrate, a plastic substrate and a silicon substrate.
  26. 기판과 상기 기판 상에 형성된 채널층, 플로팅 게이트 및 제어 게이트를 구비하는 플래쉬 메모리 소자에 있어서, A flash memory device comprising a substrate and a channel layer, a floating gate, and a control gate formed on the substrate,
    상기 채널층은 용액 기반의 IGZO 물질의 코팅을 통해 형성된 다결정 IGZO로 이루어진 것을 특징으로 하는 플래쉬 메모리 소자.And the channel layer is made of polycrystalline IGZO formed by coating a solution-based IGZO material.
  27. 제26항에 있어서,The method of claim 26,
    상기 플로팅 게이트는 카본 나노튜브, IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 층 구조인 것을 특징으로 하는 플래쉬 메모리 소자.The floating gate is a flash memory device, characterized in that the layer structure consisting of a material selected from carbon nanotubes, IGZO, ZnO, IZO and ZTO.
  28. 제26항에 있어서,The method of claim 26,
    상기 기판 위에 제어 게이트가 배치되고, 상기 제어 게이트 위에 상기 플로팅 게이트가 배치되고, 상기 플로팅 게이트 위에 상기 채널층이 배치되는 바텀 제어 게이트형 플래쉬 메모리 소자인 것을 특징으로 하는 플래쉬 메모리 소자.And a bottom control gate type flash memory device in which a control gate is disposed on the substrate, the floating gate is disposed on the control gate, and the channel layer is disposed on the floating gate.
  29. 제26항에 있어서,The method of claim 26,
    상기 기판 위에 채널층이 배치되고, 상기 채널층 위에 상기 플로팅 게이트가 배치되고, 상기 플로팅 게이트 위에 상기 제어 게이트가 배치되는 탑 제어 게이트형 플래쉬 메모리 소자인 것을 특징으로 하는 플래쉬 메모리 소자.And a channel layer disposed on the substrate, the floating gate disposed on the channel layer, and the control gate disposed on the floating gate.
  30. 제26항에 있어서,The method of claim 26,
    상기 기판은 유리 기판, 플라스틱 기판 및 실리콘 기판 중에서 어느 하나의 기판인 것을 특징으로 하는 플래쉬 메모리 소자.The substrate is a flash memory device, characterized in that any one of a glass substrate, a plastic substrate and a silicon substrate.
  31. 기판 상에 제1 플로팅 게이트층 및 제1 제어 게이트층을 형성하는 단계; 및 Forming a first floating gate layer and a first control gate layer on the substrate; And
    상기 제1 게이트층 위에 상부 채널층, 제2 플로팅 게이트층 및 제2 제어 게이트층을 형성하는 단계를 포함하고, Forming an upper channel layer, a second floating gate layer, and a second control gate layer over the first gate layer,
    상기 상부 채널층은 용액 기반의 반도체 산화물 물질을 코팅하여 형성하는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법. And the upper channel layer is formed by coating a solution-based semiconductor oxide material.
  32. 제31항에 있어서,The method of claim 31, wherein
    상기 상부 채널층은 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성되는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.And the upper channel layer is formed by coating a material selected from a solution-based IGZO, ZnO, IZO, and ZTO.
  33. 제31항에 있어서,The method of claim 31, wherein
    상기 기판은 실리콘 반도체로 이루어진 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.The substrate is a method of manufacturing a flash memory device having a 3D stacked cell structure, characterized in that the silicon semiconductor.
  34. 제32항에 있어서,33. The method of claim 32,
    상기 제1 플로팅 게이트는 폴리실리콘 물질로 형성되는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.And the first floating gate is formed of a polysilicon material.
  35. 제31항에 있어서,The method of claim 31, wherein
    상기 제1 플로팅 게이트 형성 전에 상기 기판 상에 용액 기반의 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 하부 채널층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.And forming a lower channel layer by coating a material selected from solution-based IGZO, ZnO, IZO, and ZTO on the substrate before forming the first floating gate to form a lower channel layer. Method of preparation.
  36. 제31항에 있어서,The method of claim 31, wherein
    상기 제2 플로팅 게이트는 용액 기반의 카본 나노튜브, IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질을 코팅하여 형성되는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.The second floating gate is formed by coating a material selected from solution-based carbon nanotubes, IGZO, ZnO, IZO and ZTO, 3D stacked cell structure flash memory device manufacturing method.
  37. 제31항에 있어서,The method of claim 31, wherein
    상기 상부 채널층은 스핀 코팅, 나노 압인 및 잉크젯 프린팅 중에서 선택된 공정을 이용하여 형성되는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자의 제조 방법.And the upper channel layer is formed using a process selected from spin coating, nano stamping and inkjet printing.
  38. 기판 상에 형성된 제1 플로팅 게이트 및 제1 제어 게이트를 구비하는 제1 메모리셀부; 및A first memory cell unit having a first floating gate and a first control gate formed on the substrate; And
    상기 제1 메모리셀부 상에 형성된 상부 채널층, 제2 플로팅 게이트층 및 제2 제어 게이트층을 구비하는 제2 메모리셀부를 포함하고, A second memory cell unit including an upper channel layer, a second floating gate layer, and a second control gate layer formed on the first memory cell unit;
    상기 상부 채널층은 용액 기반의 IGZO 물질의 코팅에 통해 형성된 다결정 IGZO로 이루어진 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자.And the upper channel layer is formed of polycrystalline IGZO formed by coating a solution-based IGZO material.
  39. 제38항에 있어서,The method of claim 38,
    상기 기판은 실리콘 반도체로 이루어진 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자.The substrate is a flash memory device having a 3D stacked cell structure, characterized in that the silicon semiconductor.
  40. 제39항에 있어서,The method of claim 39,
    상기 제1 플로팅 게이트는 폴리실리콘 물질로 이루어진 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자.And the first floating gate is made of polysilicon material.
  41. 제38항에 있어서,The method of claim 38,
    상기 제1 메모리셀부는 상기 기판 상에 형성되고 IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 하부 채널층을 더 구비하는 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자.The first memory cell unit is formed on the substrate and further comprises a lower channel layer made of a material selected from IGZO, ZnO, IZO and ZTO flash memory device of 3D stacked cell structure.
  42. 제38항에 있어서,The method of claim 38,
    상기 제2 플로팅 게이트는 카본 나노튜브, IGZO, ZnO, IZO 및 ZTO 중에서 선택된 물질로 이루어진 층 구조인 것을 특징으로 하는 3D 적층셀 구조의 플래쉬 메모리 소자.The second floating gate is a flash memory device having a 3D stacked cell structure, characterized in that the layer structure consisting of a material selected from carbon nanotubes, IGZO, ZnO, IZO and ZTO.
  43. 기판 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성하는 단계; 및Forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on a substrate; And
    상기 산화물 반도체 수용액 상에 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계를 포함하되,Irradiating a laser beam on the oxide semiconductor aqueous solution to form an oxide semiconductor thin film by heat treatment,
    상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 하는 산화물 반도체 박막의 제조방법.When the laser beam is irradiated, at least two regions having different characteristics on the oxide semiconductor thin film is formed in a batch by using a half-tone mask.
  44. 제43 항에 있어서, 44. The method of claim 43,
    상기 산화물 반도체는 InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 선택된 어느 하나의 물질 또는 상기 물질들의 화합물이 포함되어 이루어지는 것을 특징으로 하는 산화물 반도체 박막의 제조방법. The oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5 or TiSrO 3 characterized in that any one material or a compound of the above materials is included. Method for producing an oxide semiconductor thin film.
  45. 제43 항에 있어서, 44. The method of claim 43,
    상기 산화물 반도체 수용액은 졸-겔(Sol-GEL)법을 이용하여 형성하는 것을 특징으로 하는 산화물 반도체 박막의 제조방법.The oxide semiconductor aqueous solution is a method of manufacturing an oxide semiconductor thin film, characterized in that formed using a sol-gel (Sol-GEL) method.
  46. 제43 항에 있어서, 44. The method of claim 43,
    상기 기판 상에 산화물 반도체 수용액을 형성하는 방법으로는 스크린 프린팅 (Screen Printing), 스핀 코팅(Spin Coating) 또는 잉크젯(Ink-Jet) 방법 중 선택된 어느 하나의 방법을 이용하는 것을 특징으로 하는 산화물 반도체 박막의 제조방법. An oxide semiconductor thin film may be formed on the substrate by using any one of screen printing, spin coating, and ink jet printing. Manufacturing method.
  47. 기판 상에 게이트 전극을 형성하는 단계;Forming a gate electrode on the substrate;
    상기 게이트 전극 상에 게이트 절연층을 형성하는 단계; 및Forming a gate insulating layer on the gate electrode; And
    상기 게이트 절연층 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성한 후 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계를 포함하되,Forming an oxide semiconductor thin film by heat treatment after forming an oxide semiconductor aqueous solution by a liquid phase manufacturing process on the gate insulating layer,
    상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.When irradiating the laser beam, a method of manufacturing an oxide thin film transistor, characterized in that at least two areas having different characteristics are collectively formed on the oxide semiconductor thin film using a half-tone mask.
  48. 기판 상에 액상 제조공정에 의한 산화물 반도체 수용액을 형성한 후 레이저빔을 조사하여 열처리에 의한 산화물 반도체 박막을 형성하는 단계;Forming an oxide semiconductor thin film by heat treatment after forming an aqueous oxide semiconductor solution by a liquid phase manufacturing process on a substrate;
    상기 산화물 반도체 박막 상에 게이트 절연층을 형성하는 단계; 및Forming a gate insulating layer on the oxide semiconductor thin film; And
    상기 게이트 절연층 상에 게이트 전극을 형성하는 단계를 포함하되,Forming a gate electrode on the gate insulating layer;
    상기 레이저빔의 조사 시, 하프-톤 마스크를 이용하여 상기 산화물 반도체 박막 상에 서로 다른 특성을 갖는 적어도 2개의 영역이 일괄 형성되도록 하는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.When irradiating the laser beam, a method of manufacturing an oxide thin film transistor, characterized in that at least two areas having different characteristics are collectively formed on the oxide semiconductor thin film using a half-tone mask.
  49. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 적어도 2개의 영역 중 적어도 1개의 영역은 소오스 및 드레인 전극으로 사용하기 위한 영역인 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.At least one of the at least two regions is a region for use as a source and a drain electrode.
  50. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 적어도 2개의 영역 중 적어도 1개의 영역은 채널 영역인 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.And at least one of the at least two regions is a channel region.
  51. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 레이저빔은 상기 적어도 2개의 영역 중 소오스 및 드레인 전극으로 사용하기 위한 영역에서 에너지 밀도를 가장 크게 하여 조사되도록 하는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.And the laser beam is irradiated with the largest energy density in a region for use as a source and a drain electrode among the at least two regions.
  52. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 산화물 반도체는 InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgZnO, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5 또는 TiSrO3 중 선택된 어느 하나의 물질 또는 상기 물질들의 화합물이 포함되어 이루어지는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법. The oxide semiconductor is InGaZnO, ZnO, ZrInZnO, InZnO, ZnO, InGaZnO 4 , ZnInO, ZnSnO, In 2 O 3 , Ga 2 O 3 , HfInZnO, GaInZnO, HfO 2 , SnO 2 , WO 3 , TiO 2 , Ta 2 O 5 , In 2 O 3 SnO 2 , MgZnO, ZnSnO 3 , ZnSnO 4 , CdZnO, CuAlO 2 , CuGaO 2 , Nb 2 O 5 or TiSrO 3 characterized in that any one material or a compound of the above materials is included. Method for producing an oxide thin film transistor.
  53. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 산화물 반도체 수용액은 졸-겔(Sol-GEL)법을 이용하여 형성하는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.The oxide semiconductor aqueous solution is formed using a sol-gel (Sol-GEL) method.
  54. 제47 항 또는 제48 항에 있어서, 49. The method of claim 47 or 48,
    상기 산화물 반도체 수용액을 형성하는 방법으로는 스크린 프린팅 (Screen Printing), 스핀 코팅(Spin Coating) 또는 잉크젯(Ink-Jet) 방법 중 선택된 어느 하나의 방법을 이용하는 것을 특징으로 하는 산화물 박막 트랜지스터의 제조방법.The method of forming the oxide semiconductor aqueous solution is a method of manufacturing an oxide thin film transistor, characterized in that using any one selected from the screen printing (Spin Printing), spin coating (Ink-Jet) method.
PCT/KR2010/003263 2010-05-24 2010-05-24 Forming method and crystallization method for an oxide semiconductor thin film using a liquid-phase process, and a method for forming semiconductor elements by using the same WO2011149118A1 (en)

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