WO2012057603A1 - Isfet device with membrane - Google Patents

Isfet device with membrane Download PDF

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Publication number
WO2012057603A1
WO2012057603A1 PCT/MY2010/000288 MY2010000288W WO2012057603A1 WO 2012057603 A1 WO2012057603 A1 WO 2012057603A1 MY 2010000288 W MY2010000288 W MY 2010000288W WO 2012057603 A1 WO2012057603 A1 WO 2012057603A1
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WO
WIPO (PCT)
Prior art keywords
membrane
polysilicon
nanostructures
oxide
layer
Prior art date
Application number
PCT/MY2010/000288
Other languages
French (fr)
Inventor
Chia Sheng Daniel Bien
Mohd Saman Rahimah
Aishah Mohamad Badaruddin Siti
Mohd Zain Azlina
Ramdzan Buyong Muhamad
Fairuz Amir Mohamad
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2012057603A1 publication Critical patent/WO2012057603A1/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4146—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS involving nanosized elements, e.g. nanotubes, nanowires

Definitions

  • the present invention relates to an ion sensitive filed effect transistor (ISFET) device with membrane to improve the performance of the ISFET sensor.
  • ISFET ion sensitive filed effect transistor
  • ISFET is used as a sensor device for sensing ion concentrations in a solution via its membrane.
  • the solution is used as the gate electrode and when the ion concentration changes, the current through the transistor will change accordingly as a voltage between the substrate and oxide surfaces arises due to an ions sheath.
  • ISFET device with planar semiconductor structure which has chemically active, geometrically and spatially very small areas, known as nano-spots that are embedded in the chemically inactive surface.
  • This structure has passivated contact and a chemically inert surface, which is in direct contact with the surrounding medium of fluid or gas.
  • the present invention is made in view of the prior arts described above where typically a conventional ISFET device is fabricated with planar membrane as the sensing gate and it has been associated with problems of limited ion concentration that can be sensed. Due to this limited exposed area to the ions in the sample to be tested, the sensitivity and efficiency of the device is limited. Also, although there are improvements made by using nano-spots in the ISFET, the invention is only chemically active in the nano region and not in the membrane or structure.
  • the present invention proposes an ISFET sensor and method to fabricate the ISFET sensor device with nanostructured membrane which will improve the sensitivity and efficiency of the device.
  • the nanostructures design of the membrane increase the membrane surface area exposed to the sample solution or electrolyte which improves the sensitivity of the device.
  • the nanostructures on the membrane can be in unlimited shapes of nanowires, nanorings or nanoparticles which are fabricated using silicon based compatible processes.
  • Fig. 1 is a schematic drawing of the ISFET device with nanostructured membrane.
  • Fig. 2a is a schematic drawing showing the patterning of Si0 2 .
  • Fig. 2b is a schematic drawing showing the deposition of polysilicon.
  • Fig. 2c is a schematic drawing showing the polysilicon spacer etched for spacer
  • Fig. 2d is a schematic drawing showing the removal of Si0 2 .
  • Fig. 2e is a schematic drawing showing the halfway etching of Si 3 N 4 .
  • Fig. 2f is a schematic drawing showing the removal of polysilicon.
  • Fig. 3a is a schematic drawing showing the patterning of poly.
  • Fig. 3b is a schematic drawing showing the deposition of Si 3 N 4 .
  • Fig. 3c is a schematic drawing showing the Si 3 N 4 spacer etched for spacer formation.
  • Fig. 3d is a schematic drawing showing the etching of poly.
  • the invention involves an ISFET sensor device with nanostructured membrane to increase the membrane surface area exposed to the sample solution or electrolyte.
  • the nanostructures can be in the form of nanowires, nanorings or nanoparticles.
  • the nanostructured membrane is fabricated using silicon based compatible processes.
  • the fabrication of the ISFET device begins with the implantation of the source-drain region on semiconductor substrate [20] such as silicon. This is followed by the 88
  • FIG. 1 shows the ISFET device fabricated with silicon dioxide (Si0 2 ) as the oxide insulating layer [26], silicon nitride (Si 3 N 4 ) nanostructures [28] membrane and aluminium as the metal contact [30].
  • the metal contact is next to oxide dielectric layer at a source-drain region.
  • the gate membrane is next to oxide dielectric layer at another source-drain region. Notice that the nanostructures provide an increased contact area of membrane to increase the sensitivity of the ISFET.
  • the membrane and membrane nanostructures are common ISFET gate material such as silicon nitride, polysilicon, metal oxides, tantalum pentoxide or hafnium oxide.
  • the membrane nanostructures are in the form of nanowires, nanorings or nanoparticles.
  • the nanostructured membrane can be fabricated via two options under the nanofabrication techniques, which are the pattern transfer and direct forming methods.
  • the process begins with the formation of the oxide structures. From the example of ISFET device highlighted in Fig 1 , where the substrate of silicon [20] is deposited with Si0 2 [26] followed by Si 3 N 4 [32], a layer of Si0 2 [26] is deposited on the Si 3 N 4 [32] where it is lithographically patterned and etched, stopping on the desired location of underlying nanostructures Si 3 N 4 [32] as shown in Fig 2a. This is followed by a second stage of silicon based nanostructures formation.
  • a layer of polysilicon [34] is deposited on the patterned Si0 2 [26] as shown in Fig. 2b and then blanket etched to form polysilicon spacers [36] as shown in Fig. 2c. This is followed by the removal of the Si0 2 [26] oxide to form polysilicon nanostructures [38] shown in Fig. 2d.
  • the last stage is the formation of the Si 3 N 4 nanostructures [28] where the underlying Si 3 N 4 [32] is etched halfway using the polysilicon nanostructures [38] as transfer mask as shown in Fig. 2e and followed by the removal of the polysilicon nanostructures [38], leaving behind the completed Si 3 N 4 nanostructures [28] as shown in Fig. 2f. 88
  • the process uses the formation of polysilicon [34] structures as template to form nanostructures.
  • a layer of polysilicon [34] is deposited on the Si 3 N 4 [32] where it is 5 lithographically patterned and etched, stopping on the desired location of underlying nanostructures Si 3 N 4 [34] as shown in Fig 3a.
  • a second stage of Si 3 N 4 nanostructures formation A layer of Si 3 N 4 [32] is deposited on the patterned polysilicon [34] as shown in Fig. 3b and then blanket etched to form Si 3 N 4 spacers [40] as shown in Fig. 3c.
  • the removal of the polysilicon [34] to form Si 3 N 4 10 nanostructures [28] shown in Fig. 3d.
  • the nanostructured membrane can also be formed using other material such as polysilicon [34] and metallic nanowires, for example, not limited to, tantalum pentoxide (Ta 2 0 5 ), aluminium oxide (Al 2 0 3 ), WO x or hafmium oxide (Hf0 2 ).
  • tantalum pentoxide Ti 2 0 5
  • aluminium oxide Al 2 0 3
  • WO x hafmium oxide
  • the invention disclosed a method to fabricate an ISFET sensor device with nanostructured membrane which will improve the sensitivity and efficiency of the device.
  • the nanostructures can be in unlimited shape or design, in the form of nanowires, nanorings or nanoparticles that are fabricated using silicon based compatible processes. 0
  • the nanostructures have a function to increase the sensor sensitivity by increasing the surface area of the membrane exposed to the sample solution or electrolyte.
  • the nanostructured membrane can be formed either by nanofabrication techniques which includes lithographic patterning, pattern transfer, thin film deposition and etching methods or by spin coating of nanomaterials and nanowires. The fabrication options for
  • 25 nanofabrication techniques include pattern transfer method and direct forming method.
  • This nanostructured membrane can be fabricated using various materials such as polysilicon [34] and metallic nanowires, for example, not limited to, Si 3 N 4 [32], Ta 2 0 5 , Al 2 0 3 , WO x or Hf0 2 .

Abstract

The present invention provides an ISFET sensor device and a method to fabricate the ISFET sensor device with nanostructured membrane which will improve the sensitivity and efficiency of the device. The nanostructures can be in unlimited shape or design, in the form of nanowires, nanorings or nanoparticles, fabricated with the function to increase the sensor sensitivity by increasing the surface area of the membrane exposed to the sample solution or electrolyte. The nanostructured membrane can be formed either by nanofabrication techniques which includes lithographic patterning, pattern transfer, thin film deposition and etching methods or by spin coating of nanomaterials and nanowires using various materials, not limited to, such as, Si3N4 [32], polysilicon [34] and metallic nanowires.

Description

Y2010/000288
1
ISFET DEVICE WITH MEMBRANE
The present invention relates to an ion sensitive filed effect transistor (ISFET) device with membrane to improve the performance of the ISFET sensor.
BACKGROUND ART
ISFET is used as a sensor device for sensing ion concentrations in a solution via its membrane. The solution is used as the gate electrode and when the ion concentration changes, the current through the transistor will change accordingly as a voltage between the substrate and oxide surfaces arises due to an ions sheath.
Presently, there is a prior art which teaches how to fabricate ISFET structure as such that the external electrical contact to the P+ source and drain regions is made through individual holes etched from the back to the source and drain regions with side wall isolation being provided in the holes and metallization covering its surface of said sidewalls and extending to contact pads on the back of the ISFET.
Another prior art listed the fabrication of ISFET device with planar semiconductor structure which has chemically active, geometrically and spatially very small areas, known as nano-spots that are embedded in the chemically inactive surface. This structure has passivated contact and a chemically inert surface, which is in direct contact with the surrounding medium of fluid or gas.
The present invention is made in view of the prior arts described above where typically a conventional ISFET device is fabricated with planar membrane as the sensing gate and it has been associated with problems of limited ion concentration that can be sensed. Due to this limited exposed area to the ions in the sample to be tested, the sensitivity and efficiency of the device is limited. Also, although there are improvements made by using nano-spots in the ISFET, the invention is only chemically active in the nano region and not in the membrane or structure.
SUMMARY OF INVENTION 010 000288
2
The present invention proposes an ISFET sensor and method to fabricate the ISFET sensor device with nanostructured membrane which will improve the sensitivity and efficiency of the device. The nanostructures design of the membrane increase the membrane surface area exposed to the sample solution or electrolyte which improves the sensitivity of the device. The nanostructures on the membrane can be in unlimited shapes of nanowires, nanorings or nanoparticles which are fabricated using silicon based compatible processes.
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 is a schematic drawing of the ISFET device with nanostructured membrane.
Fig. 2a is a schematic drawing showing the patterning of Si02.
Fig. 2b is a schematic drawing showing the deposition of polysilicon.
Fig. 2c is a schematic drawing showing the polysilicon spacer etched for spacer
formation.
Fig. 2d is a schematic drawing showing the removal of Si02.
Fig. 2e is a schematic drawing showing the halfway etching of Si3N4.
Fig. 2f is a schematic drawing showing the removal of polysilicon.
Fig. 3a is a schematic drawing showing the patterning of poly.
Fig. 3b is a schematic drawing showing the deposition of Si3N4.
Fig. 3c is a schematic drawing showing the Si3N4 spacer etched for spacer formation.
Fig. 3d is a schematic drawing showing the etching of poly.
DESCRIPTION OF EMBODIMENTS
Hereinafter, the present invention is described in detail.
The invention involves an ISFET sensor device with nanostructured membrane to increase the membrane surface area exposed to the sample solution or electrolyte. The nanostructures can be in the form of nanowires, nanorings or nanoparticles. The nanostructured membrane is fabricated using silicon based compatible processes.
The fabrication of the ISFET device begins with the implantation of the source-drain region on semiconductor substrate [20] such as silicon. This is followed by the 88
3 deposition of an oxide dielectric layer [26] and then the nanostructured membrane formation [28] at the membrane area [22]. The oxide dielectric layer [26] is next to the substrate [20] having source-drain region surface. Nanostructures are formed either by nanofabrication techniques or spin coating of nanomaterials and nanowires. The ISFET device is completed with the metallization at the contact pad area [24] for conductive contact to the source-drain region. Fig. 1 shows the ISFET device fabricated with silicon dioxide (Si02) as the oxide insulating layer [26], silicon nitride (Si3N4) nanostructures [28] membrane and aluminium as the metal contact [30]. The metal contact is next to oxide dielectric layer at a source-drain region. The gate membrane is next to oxide dielectric layer at another source-drain region. Notice that the nanostructures provide an increased contact area of membrane to increase the sensitivity of the ISFET.
The membrane and membrane nanostructures are common ISFET gate material such as silicon nitride, polysilicon, metal oxides, tantalum pentoxide or hafnium oxide. The membrane nanostructures are in the form of nanowires, nanorings or nanoparticles.
The nanostructured membrane can be fabricated via two options under the nanofabrication techniques, which are the pattern transfer and direct forming methods. In the pattern transfer method, the process begins with the formation of the oxide structures. From the example of ISFET device highlighted in Fig 1 , where the substrate of silicon [20] is deposited with Si02 [26] followed by Si3N4 [32], a layer of Si02 [26] is deposited on the Si3N4 [32] where it is lithographically patterned and etched, stopping on the desired location of underlying nanostructures Si3N4 [32] as shown in Fig 2a. This is followed by a second stage of silicon based nanostructures formation. A layer of polysilicon [34] is deposited on the patterned Si02 [26] as shown in Fig. 2b and then blanket etched to form polysilicon spacers [36] as shown in Fig. 2c. This is followed by the removal of the Si02 [26] oxide to form polysilicon nanostructures [38] shown in Fig. 2d. The last stage is the formation of the Si3N4 nanostructures [28] where the underlying Si3N4 [32] is etched halfway using the polysilicon nanostructures [38] as transfer mask as shown in Fig. 2e and followed by the removal of the polysilicon nanostructures [38], leaving behind the completed Si3N4 nanostructures [28] as shown in Fig. 2f. 88
4
As for the direct forming method, the process uses the formation of polysilicon [34] structures as template to form nanostructures. From the example of ISFET device highlighted in Fig 1, where the substrate of silicon [20] is deposited with Si02 [26] followed by Si3N4 [32], a layer of polysilicon [34] is deposited on the Si3N4 [32] where it is 5 lithographically patterned and etched, stopping on the desired location of underlying nanostructures Si3N4 [34] as shown in Fig 3a. This is followed by a second stage of Si3N4 nanostructures formation. A layer of Si3N4 [32] is deposited on the patterned polysilicon [34] as shown in Fig. 3b and then blanket etched to form Si3N4 spacers [40] as shown in Fig. 3c. This is followed by the removal of the polysilicon [34] to form Si3N4 10 nanostructures [28] shown in Fig. 3d.
Besides Si3N4 [32], the nanostructured membrane can also be formed using other material such as polysilicon [34] and metallic nanowires, for example, not limited to, tantalum pentoxide (Ta205), aluminium oxide (Al203), WOx or hafmium oxide (Hf02).
I 5
Accordingly, the invention disclosed a method to fabricate an ISFET sensor device with nanostructured membrane which will improve the sensitivity and efficiency of the device. The nanostructures can be in unlimited shape or design, in the form of nanowires, nanorings or nanoparticles that are fabricated using silicon based compatible processes. 0 The nanostructures have a function to increase the sensor sensitivity by increasing the surface area of the membrane exposed to the sample solution or electrolyte. The nanostructured membrane can be formed either by nanofabrication techniques which includes lithographic patterning, pattern transfer, thin film deposition and etching methods or by spin coating of nanomaterials and nanowires. The fabrication options for
25 nanofabrication techniques include pattern transfer method and direct forming method.
This nanostructured membrane can be fabricated using various materials such as polysilicon [34] and metallic nanowires, for example, not limited to, Si3N4 [32], Ta205, Al203, WOx or Hf02.
30

Claims

An ISFET device with membrane, comprising:
a substrate [20] with implanted source-drain region;
an oxide dielectric layer [26] next to the substrate [20] having source-drain region surface;
a metal contact [30] next to oxide dielectric layer [26] at a source-drain region; a gate membrane [32] next to oxide dielectric layer [26] at another source-drain region;
characterized in that,
the membrane has membrane nanostructures [28].
An ISFET device according to claim 1 , wherein the membrane and membrane nanostructures are silicon nitride, polysilicon, metal oxides, tantalum pentoxide or hafnium oxide.
An ISFET device according to claim 1 , wherein the membrane nanostructures are nanowires, nanorings or nanoparticles.
A method of fabricating an ISFET device with membrane characterized in that,
forming membrane nanostructures [28] at the membrane area [22] on top of the oxide dielectric layer with substrate having implanted source-drain region.
A method according to claim 4, wherein forming membrane nanostructures, comprising:
depositing a layer of oxide on top of membrane material;
lithographically patterning and etching the oxide, stopping on the desired location of underlying nanostructure membrane material;
depositing a layer of polysilicon [34] on top of the patterned oxide;
blanket etching the polysilicon [34] to form polysilicon spacers [36];
removing the oxide to form polysilicon structures [38];
etching underlying membrane material layer using the polysilicon structure [38] as transfer mask; and
removing the polysilicon structure [38], leaving behind the formed nanostructures on the membrane.
6. A method according to claim 4, wherein forming membrane nanostructures, comprising:
depositing a layer of polysilicon [34] on top of membrane material;
lithographically patterning and etching the polysilicon [34], stopping on the desired location of underlying membrane material;
depositing a layer of membrane material on top of the patterned polysilicon [34]; blanket etching membrane material to form spacers;
removing the polysilicon [34], leaving behind the formed nanostructures on the membrane.
PCT/MY2010/000288 2010-10-29 2010-11-24 Isfet device with membrane WO2012057603A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI201070079 2010-10-29
MYPI2010070079 2010-10-29

Publications (1)

Publication Number Publication Date
WO2012057603A1 true WO2012057603A1 (en) 2012-05-03

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050095698A1 (en) * 2003-09-03 2005-05-05 Receptors Llc Sensors employing combinatorial artificial receptors
US20080319298A1 (en) * 2007-03-08 2008-12-25 Interuniversitair Microelektronica Centrum (Imec) CMOS Compatible Microneedle Structures
US20090278556A1 (en) * 2006-01-26 2009-11-12 Nanoselect, Inc. Carbon Nanostructure Electrode Based Sensors: Devices, Processes and Uses Thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050095698A1 (en) * 2003-09-03 2005-05-05 Receptors Llc Sensors employing combinatorial artificial receptors
US20090278556A1 (en) * 2006-01-26 2009-11-12 Nanoselect, Inc. Carbon Nanostructure Electrode Based Sensors: Devices, Processes and Uses Thereof
US20080319298A1 (en) * 2007-03-08 2008-12-25 Interuniversitair Microelektronica Centrum (Imec) CMOS Compatible Microneedle Structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WANG, YUN ET AL.: "A capacitive humidity sensor based on ordered macroporous s ilicon with thin film surface coating.", SENSORS AND ACTUATORS B: CHEMICAL., vol. 149, August 2010 (2010-08-01), pages 136 - 142 *

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