WO2012075303A3 - A system and method for analyzing an electronics device including a logic analyzer - Google Patents

A system and method for analyzing an electronics device including a logic analyzer Download PDF

Info

Publication number
WO2012075303A3
WO2012075303A3 PCT/US2011/062910 US2011062910W WO2012075303A3 WO 2012075303 A3 WO2012075303 A3 WO 2012075303A3 US 2011062910 W US2011062910 W US 2011062910W WO 2012075303 A3 WO2012075303 A3 WO 2012075303A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic analyzer
under test
computing device
device under
embedded logic
Prior art date
Application number
PCT/US2011/062910
Other languages
French (fr)
Other versions
WO2012075303A2 (en
Inventor
James Ray Bailey
Christopher W. Case
Michael Anthony Marra, Iii
James Patrick Sharpe
James Alan Ward
Original Assignee
Lexmark International, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/308,286 external-priority patent/US9170901B2/en
Application filed by Lexmark International, Inc. filed Critical Lexmark International, Inc.
Publication of WO2012075303A2 publication Critical patent/WO2012075303A2/en
Publication of WO2012075303A3 publication Critical patent/WO2012075303A3/en

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers

Abstract

A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.
PCT/US2011/062910 2010-12-01 2011-12-01 A system and method for analyzing an electronics device including a logic analyzer WO2012075303A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US41884910P 2010-12-01 2010-12-01
US61/418,849 2010-12-01
US13/308,286 US9170901B2 (en) 2009-08-18 2011-11-30 System and method for analyzing an electronics device including a logic analyzer
US13/308,286 2011-11-30

Publications (2)

Publication Number Publication Date
WO2012075303A2 WO2012075303A2 (en) 2012-06-07
WO2012075303A3 true WO2012075303A3 (en) 2012-08-02

Family

ID=46172575

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/062910 WO2012075303A2 (en) 2010-12-01 2011-12-01 A system and method for analyzing an electronics device including a logic analyzer

Country Status (1)

Country Link
WO (1) WO2012075303A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5881217A (en) * 1996-11-27 1999-03-09 Hewlett-Packard Company Input comparison circuitry and method for a programmable state machine
US6389558B1 (en) * 1996-10-28 2002-05-14 Altera Corporation Embedded logic analyzer for a programmable logic device
US20030078752A1 (en) * 1999-05-14 2003-04-24 Chakravarthy K. Allamsetty System and method for testing a circuit implemented on a programmable logic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6389558B1 (en) * 1996-10-28 2002-05-14 Altera Corporation Embedded logic analyzer for a programmable logic device
US5881217A (en) * 1996-11-27 1999-03-09 Hewlett-Packard Company Input comparison circuitry and method for a programmable state machine
US20030078752A1 (en) * 1999-05-14 2003-04-24 Chakravarthy K. Allamsetty System and method for testing a circuit implemented on a programmable logic device

Also Published As

Publication number Publication date
WO2012075303A2 (en) 2012-06-07

Similar Documents

Publication Publication Date Title
WO2014150306A8 (en) System and method for coordinating field user testing results for a mobile application across various mobile devices
WO2015023930A3 (en) Automatically capturing user interactions and evaluating user interfaces in software programs using field testing
EP2627041A3 (en) Method and apparatus for testing and displaying test results
WO2007103591A3 (en) Method and apparatus for testing a data processing system
WO2009033023A3 (en) A method for test suite reduction through system call coverage criterion
WO2007133599A3 (en) Vehicle testing and simulation using integrated simulation model and physical parts
MX2014007127A (en) Methods of calibration transfer for a testing instrument.
WO2013138356A3 (en) System and method for robust estimation of color dependent measurements
EP3499371A3 (en) Real time analysis and control for a multiprocessor system
WO2010033983A3 (en) Testing machine with workflow based test procedure
WO2013181344A3 (en) Modular alternator and starter tester with a four link hood hinge
WO2011162874A3 (en) System for identifying and inferring web session events
WO2014031754A3 (en) Imaging and diagnostic methods, systems, and computer-readable media
WO2014113892A3 (en) Computer-aided localization of site of origin of cardiac activation with discriminator leads
EP2952866A4 (en) Method for evaluating residual stress by using instrumented indentation test technique, storage medium storing computer program including same, and indentation test apparatus for performing instrumented indentation test by operating storage medium
WO2012075082A3 (en) Method of evaluating performance characteristics
WO2015130675A3 (en) Apparatus and method for testing computer program implementation against a design model
WO2014169217A3 (en) Systems and methods for establishing the stiffness of a bone using mechanical response tissue analysis
WO2014006035A3 (en) Test device
GB2515920A (en) Physical Performance Assessment
IN2014CN02498A (en)
WO2013073105A3 (en) Information processing apparatus, information processing method and program
GB2490626A (en) Measurement method for a component of the gravity vector
EP3029595A3 (en) Apparatuses, mobile devices, methods and computer programs for evaluating runtime information of an extracted set of instructions based on at least a part of a computer program
WO2014080354A3 (en) Reporting scores on computer programming ability under a taxonomy of test cases

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11845437

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11845437

Country of ref document: EP

Kind code of ref document: A2