WO2012079901A1

WO2012079901A1 - Analog-to-digital converter, method for operating an analog-to-digital converter and method for converting an analog input signal into a digital output signal

Info

Publication number: WO2012079901A1
Application number: PCT/EP2011/070240
Authority: WO
Inventors: Philipp Kruppa; Alexander Frey; Ingo KÜHNE
Original assignee: Siemens Aktiengesellschaft
Priority date: 2010-12-17
Filing date: 2011-11-16
Publication date: 2012-06-21
Also published as: DE102010063405A1

Abstract

The invention relates to an analog-to-digital converter (10) which functions on the basis of the principle of successive approximation and comprises a network (11) with weighted reference elements (12), which are formed at least partially by capacitors (C), which each have a first plate (19) and a second plate (20), a comparator (14), the first input of said comparator being connected to the second plates (20) of the capacitors, and a reference voltage (V_ref) being applied to the second input of said comparator, a first switching unit (22), via which the first plates (19) can optionally be connected to a first input voltage (V_in1) or to ground, a second switching unit (24), via which the second plates (20) can optionally be connected to a second input voltage (V_in2) or so as to be highly resistive, and a monitoring unit (15), which is connected downstream of the comparator (14) and which comprises a data register (26) for buffer-storing output signals from the comparator (14) and a control unit (27) for driving the network (11) as well as the first switching unit (22) and the second switching unit (24). The differential analog-to-digital converter according to the invention is characterized by a low level of complexity in terms of circuitry, a low area requirement and a low power consumption.

Description

description

Analog-to-digital converter, method for operating an analog-to-digital converter and method for converting an analog input signal into a digital output signal

The invention relates to an analog-to-digital converter for converting an analog input signal into a digital Aus ^¬ output signal according to the principle of successive approximation, a method for operating an analog-to-digital converter according to the invention and a method for converting an analog input signal, which from the Difference of a first analog input voltage and a second analog input voltage is formed in a digital Ausgangssig- signal according to the principle of successive approximation.

Analog / digital converters - often referred to as A / D converters, A / D converters or A / D converters - are electronic circuits which convert an analog input voltage, eg a measurement signal of a sensor, into a proportional digital output voltage. which can be, for example, output as binary coded for ^¬ output voltage, convert. Many A / D converter types are known for the analog / digital conversion, for example parallel A / D converters (flash converters), cascade A / D converters (subranging converters) and according to the weighing method or the principle of the successive ones Approximation working A / D converter (see Tietze, Schenk, semiconductor circuit technology, 10th edition, especially pages 774 ff).

In the method of successive approximation, the data bits of a digital output variable from an input variable in progress are successively determined in succession. 1 shows the basic structure of a successive approximation A / D converter 1 described, for example, in German Patent DE 101 39 488 C1. The A / D converter 1 has on the input side a sample and hold circuit 2 for sampling and storing an analogue input circuit 2. Voltage UE on. In the sample and hold circuit 2, the input voltage UE is latched to ensure that changes in the input voltage UE do not cause an error during the conversion period. Furthermore, a comparator 3 is provided for comparing the stored analog input voltage UE with the analog comparison voltage UZ derived from the digital output voltage UD. The analog comparison voltage UZ results from the feedback of the digital output voltage UD generated by a SAR register 4 (SAR = successive approximation register) and subsequent digital / analog conversion. For this purpose, an n-bit D / AWandler 5 is provided, where n here designates the resolution of the D / A conversion.

In the successive approximation, the

Most significant bit (MSB bit) set and then determined by means of the digital / analog converter, the associated value of an analog chip ^¬ tion. Is to be converted input analog voltage UE is greater than the determined output analog voltage UZ of the digital / analog converter, then the set bit remains ge ^¬ sets. In the opposite case, it is reset again. ^Subsequently , the next least significant bit is determined in the same way. In this way, the process will be continued sets ^¬ until all successive bits of the digital / analog converter are determined.

The function of the sample-and-hold circuit can be integrated into the D / A converter by modifying the transducer method and thus be dispensed with as a separate circuit and function block. Thus, e.g. the analog input voltage through

Charge redistribution on a capacity network integrated into the D / A converter for the time of conversion are cached. Such a designed A / D converter is described, for example, in J. Sauerbrey, D. Schmitt-Landsiedel and R. Thewes; "A 0.5V, Ιμΐ / tf Successive Approximation ADC"; IEEE

Journal of Solid State Circuits; vol. 38 no. 7; Pages 1261 - 1265; 2003 described. In this case, in a sampling phase first plates of the capacitors of the capacitance network on a first switch connected to the analog input voltage and second plates of the capacitors of the capacitance network connected via a second switch to ground. In a subsequent holding phase, which also serves as a conversion phase, the first plates of the capacitors are connected to ground and the second plates are switched high impedance, so that at the input of a comparator, the negative input voltage is applied. Through the capacity network, this voltage is "held" during the conversion phase. In this case, the comparator no longer compares the analog input voltage with the analog reference voltage. Instead, the difference between the measuring voltage and the reference voltage is compared with a constant reference voltage at the second comparator input. The actual transformation with the help of the successive approximation remains unchanged.

The result of the conversion can be falsified by interference signals, for example in the form of interference voltages, which are superimposed on the analog input voltage, for example a measurement signal of a sensor. If the A / D converter is operated with a so-called "single-ended" voltage input, the interference signals are amplified with respect to an ideal system reference ground and ver ^¬ deteriorate on the signal-to-noise ratio, the converter ^¬ resolution.

To optimize the converter accuracy, it is known to provide A / D converter with differential voltage inputs. With a differential voltage input, the difference between two input voltages (measuring signals) is formed and converted into a digital data word. In this way, interference signals, with which both input voltages are applied in the same way, compensated.

Such an A / D converter with differential voltage input is known for example from US 2003/0206038 AI.

However, a major disadvantage of the known A / D converters with differential voltage inputs is that a second D / A converter or a second capacitance network and a fully differential comparator are required, which significantly increases both the circuitry complexity and thus the cost and space requirements. In addition, such A / D converter also have a relatively high power requirement.

The invention has for its object to provide an analog-to-digital converter with differential voltage inputs and an associated method for converting an analog input signal into a digital output signal, wel ^¬ che avoid the disadvantages mentioned above. Another object of the invention is to provide an analog-to-digital converter, which in addition to the differential operation without large circuit overhead allows a "single-ended" mode.

The first object is achieved by an analog-to-digital converter for converting an analog input signal into a digital output signal according to the principle of successive approximation, which comprises:

, Wel ^¬ che each have a network having weighted reference elements, which are at least partially formed by a first capacitor plate and a second plate up, -

a comparator whose first input is connected to the second plates of the capacitors of the network and to whose second input a reference voltage is applied,

- a first controllable switching unit, which is such ausges ^¬ taltet that the first plates of the capacitors of the network are alternatively be wired with at least one first analog input voltage or to ground,

- a second controllable switching unit, which is designed such Removing that the second plates of the capacitors of the network are optionally substituted with a second analog input voltage or a high resistance A ^¬ be wired, and -, wel ^¬ comprises at least one downstream of the comparator control unit che a data register, in particular a sukzes ^¬ immersive approximation register, for the intermediate storage of output signals of the comparator and a control unit for controlling the network as well as the first and the second switching unit.

The first object is also achieved by a method for converting an analog input signal, which is formed from the difference of a first analog input voltage and a second analog input voltage, into a digital output signal with the aid of a network with weighted reference ^elements , which are at least partially connected by capacitors are formed, each having a first plate and a second plate. Here, the first analog input voltage and to the second plates of the capacitors, the second analog input voltage is applied in a sample ^¬ phase on the first plates of the capacitors. In ei ^¬ ner following the sampling phase conversion phase then the first plates of the capacitors are connected to ground, switched the second plates of the capacitors high impedance and then determines a digital output voltage using sukzes ^¬ siver approximation. The invention is based on the basic idea, to implement differential voltage inputs, not to feed the two input voltages into separate networks, but into a common network, wherein in one sampling phase one of the input voltages to the lower and the other input voltage to the upper plates of the capacitors of the network be created. For the applicability of the invention, it is irrelevant whether the reference elements are completely formed by capacitors (capacitance network) or whether part of the network is also realized by other reference elements, such as resistors (hybrid network).

The system architecture according to the invention is characterized

in that a differential operation of the A / D Converter with only one (single) D / A converter or network is made possible, moreover, no fully differential comparator is required. Both have a positive effect on the circuit complexity, the costs and the necessary space requirement. Also, power consumption is significantly reduced compared to conventional differential A / D converters.

According to one disclosed embodiment of the invention, the second controllable switching unit is configured such that the two ^¬ ten plates of the capacitors of the network are be wired not only with the second analog input voltage or a high resistance, but alternatively also with the reference voltage, which as well as at the comparator constant comparison voltage is used. In this way, an A / D converter is provided with very simple switching ^¬ technical means, which in addition to the differential also allows a "single-ended" mode of operation. Depending on whether the second plates of the capacitors of the network are connected to the second input voltage or the reference voltage in the sampling phase via the second controllable switching unit, a differential mode (first operating mode) or a "single-ended" mode (second operating mode) realized. According to one disclosed embodiment of the invention, the operation mode is fixed ^¬ can be laid by a user of the analog-digital converter. For this purpose, the second controllable switching unit can be controllable, for example, depending on an external control signal that can be predetermined by a user.

Further features and advantages of the invention will become apparent from exemplary embodiments, which are explained below with reference to the drawings. Show it: 1 is a schematic block diagram of a known, working on the principle of successive approximation A / D Umsetz zers and #

Fig. 2 is a schematic representation of an inventive ^¬ SEN analog-to-digital converter according to a possible disclosed embodiment.

The A / D converter 10 shown schematically in FIG. 2 has a network 11 with weighted reference elements 12 connected in parallel. In the illustrated embodiment, the network 11 is designed as a pure capacitance network, which has as reference elements 12 exclusively capacitors C ^¬ . But for the applicability of the invention is also sufficient if only a part of the reference elements 12 is designed as capacitors C and the other Refe ^¬ rence elements 12 otherwise, eg in the form of resistors (resistor network), realized. Such a network consisting of several subnetworks with different reference elements is often referred to as a hybrid network. In addition, the A / D converter 10 has a comparator 14 and a control unit 15.

To a first input 16 of the A / D-imple dec 10 is a ERS te analog input voltage Vj_ _n i and to a second input 17 of the A / D-imple decomp 1 is a second analog input clamping ^¬ voltage Vi _n 2 can be applied. The input voltages Vj_ _n i and _n 2 Vi can in this case be, for example, measuring signals of a sensor, not shown. The input voltages Vj_ _n i and _n 2 Vi may be present directly in the form of voltage signals or current signals from, are discharged via a resistor not shown, for example. At a third input 18 of the A / D converter 10 is finally a reference voltage V _ref anleg ^¬ bar.

The network 11 has a plurality of capacitors Co to C _n -i, each having a first plate 19 and a second plate 20 and which except for the capacitor Co are respectively connected in series to a controllable switch 21-1 to 21-n. As an alternative to the illustrated embodiment, however, the capacitor Co may also be connected in series with a controllable switch. The controllable formwork ter 21-1 to 21-n permit the selective connection of the first plates 19 of capacitors Co through C _n-i with a Be ^¬ operating voltage VDD, which is advantageously stabilized, or 22, with a first controllable switching unit the steuerba ^The switches 21-1 to 21-nl can be controlled via control signals S _c , as will be explained in more detail below. The network 11 with the switchable reference elements 12 in the form of the capacitors C fulfills the function of a digital / analog converter and a sample-and-hold circuit, as they are inherent in a successively approximating A / D converter. The capacitance values of the capacitors Co to C _n -i are binary-weighted, the capacitance of the capacitor C _n -i corresponding to the sum of the capacitances of the lower-value capacitors C _n -i i to Co. The capacitor C _n -i corresponds to the highest-order capacitor in an n-bit converter, while the capacitor Co corresponds to the lowest-value capacitor. For reference elements 12, which are designed, for example, as resistors, a corresponding weighting can be achieved with the aid of the resistance values. Is connected via the first controllable switching unit 22 out ^¬ leads Darge ^¬ exemplary embodiment illustrated as a simple switch 23, the first plates 19 of the capacitors C of the network 11 can be wired either with the first analog input voltage Vi _n i or ground. Via a second controllable switching unit 24, the second plates 20 of the capacitors C of the network 11 can be selectively connected to the second ana ^¬ logen input voltage Vi _n 2 or the constant reference voltage V _ref or high impedance. On the output side of the network 11, the comparator 14 is connected downstream, wherein a first input of the comparator 14 with egg ^¬ nem the second plates 20 of the capacitors C with each other connecting node 25 is connected. At the second input of the comparator, the reference voltage V _{ref is applied} .

Downstream of the comparator 14 is the control unit 15, which has at least one data register 26 and a control unit 27. The data register 26 is, in the case of a successive approximation A / D converter ^¬ typi cally a successive approximation register (SAR). In the data register 26, the output signals of the comparator 14, that is, the respective comparison results V _comp , are buffered. Depending on the result of a V _comp per ^¬ weils current comparison in the comparator 14, the control unit 27 generates a control signal S _c for the network 11, especially the switches 21, and control signals Sl for the controllable switching units 22 and 24th

The control unit 15 may contain a SAR which binä ^¬ ren A / D converters 10 is proper. Additionally or alternatively, however, any configuration of the data register 26 may be provided here. For example, the control unit 15 may contain any Wandlungsalgorythmus for He averaging ^¬ the bits of a digital output signal. In particular, the control unit 15 may also be designed for a non-binary A / D converter. For example, it is conceivable that the inventive A / D

Converter is designed with a redundancy, which is ^{insbesonde ¬} re in terms of the speed of the A / D converter of ^¬ part before. In the following, however, the structure and operation of such a successively approximating A / D converter with redundancy will not be discussed in more detail, since the latter

Basic structure and functionality from the prior art is already well known.

The second controllable switching unit 24 comprises in the ones shown, presented embodiment, two switches 28 and 29. The first switch 28 serves to control flow of the A / D conversion, in particular the changeover between a Abtastpha ^¬ se and subsequent conversion phase, the consequences - will be explained in more detail. The second switch 29 is used to set or determine an operating mode of the A / D converter 10. Depending on the position of the second switch 29, the second plates 20 of the capacitors C with closed first switch 28 with the second input voltage Vi _n 2 or Reference voltage V _ref connected, which corresponds to a differential mode of operation or a "single-ended" ^¬ operating mode. The second switch 29 is controlled via an externally definable by a user control signal D. The second controllable switching unit 24 can also be configured in a different form, in particular can be dispensed with the possibility of switching to a "single-ended" Mo ^¬ dus. The mode of operation of the inventive A / D converter 10 from FIG. 2 for a differential mode of operation will now be explained.

In a sampling phase is applied to the first plates 19 of the capacitors C, the first analog input voltage Vj_ _n i and the second plates 20 of the capacitors C, the second analog input voltage Vi _n 2. For this purpose, the switches 21 of the network 11, the switch 23 of the first switching unit 22 and the switches 28 and 29 of the second switching unit 24 by the control unit 27 of the control unit 15 according to ^¬ controlled, in particular by closing the first

Switch 28 of the second switching unit 24, the Abstastphase started. In a conversion phase following the sampling phase, the first plates 19 of the capacitors C are connected to ground and the second plates 20 of the capacitors C are switched to high impedance (opening of the first switch 28 of the second switching unit 24). Thus, a voltage V _x is applied to the non-inverting input of the comparator 14 on the basis of the Ladungsum ^¬ distribution which Vj_ _n i and _n 2 Vi corresponding to the difference of the examples the analog input voltages. At ^¬ closing the digital output voltage is ^¬ on the conversion phase determined in a known manner using sukzes ^¬ sive approximation, as for example in James L. McCreary and Paul R. Gray; "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques Part I", IEEE Journal of Solid State Circuits, 12/1975, pages 371-379, is described in detail.

Claims

claims

1. analog-to-digital converter (10) for converting an analog input signal into a digital output signal according to the principle of successive approximation with

a network (11) with weighted reference elements

(12) which are at least partially formed by capacitors (C) each having a first plate (19) and a second plate (20),

a comparator (14) whose first input is connected to the second plates (20) of the capacitors of the network and to whose second input a reference voltage (V _re f) is applied,

- A first controllable switching unit (22), which is designed such that the first plates (19) of the capacitors (C) of the network (11) optionally with at least ei ^¬ ner first analog input voltage (Vi _n i) or can be connected to ground .

- A second controllable switching unit (24) which is designed such that the second plates (20) of the

Capacitors (C) of the network (11) optionally with a second analog input voltage (Vj_ _n 2) or high impedance can be switched ^¬ , and

- a comparator (14) downstream of the control unit (15), which at least one data register (26), in particular a successive approximation register, for temporary storage of output signals of the comparator (14) and a control unit (27) for controlling the network (11) and the first (22) and second switching units (24).

2. An analog-to-digital converter according to claim 1, wherein the second controllable switching unit (24) is configured such that the second plates (20) of the capacitors (C) of the network (11) optionally with the second analog input voltage

(Vj_ _n 2) or with the reference voltage (V _ref ) or high impedance can be switched ^¬ .

3. Analog-to-digital converter according to claim 2, wherein the second controllable switching unit (24) is controlled in dependence on an external by a user presettable control signal (D).

4. A method for converting an analog input signal, which is formed from the difference of a first analog input voltage (Vini) and a second analog input voltage (Vj_ _n 2), into a digital output signal by means of a network (11) with weighted reference elements (12). which are at least partially formed by capacitors (C) each having a first plate (19) and a second plate (20), in which

- In a sampling phase to the first plates (19) of the capacitors (C), the first analog input voltage (Vj_ _n i) and to the second plates (20) of the capacitors (C), the second analog input voltage (Vj_ _n 2) applied will and

- in one of the sampling phase following conversion phase, the ers ^¬ th plates (19) of the capacitors (C) are connected to ground, the second plates (20) of the capacitors are switched (C) a high resistance and then a digital output voltage using successive approximation is determined ,

5. A method for operating an analog-to-digital converter according to one of claims 2 or 3, wherein during a sampling phase in a first operating mode to the second plates (20) of the capacitors, the second analog input voltage (Vj_ _n 2) and in a second operating mode the reference voltage (V _ref ) is applied.

6. The method of claim 5 in reference to claim 3, wherein the mode of operation by a user of the analog-to-digital converter (10) can be fixed.